664 lines
24 KiB
C
664 lines
24 KiB
C
//*****************************************************************************
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//
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// udma.h
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//
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// Prototypes and macros for the uDMA controller.
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//
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// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//*****************************************************************************
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#ifndef __UDMA_H__
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#define __UDMA_H__
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//*****************************************************************************
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//
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// If building with a C++ compiler, make all of the definitions in this header
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// have a C binding.
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//
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//*****************************************************************************
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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//*****************************************************************************
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//
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//! \addtogroup uDMA_Micro_Direct_Memory_Access_api
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//! @{
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// A structure that defines an entry in the channel control table. These
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// fields are used by the uDMA controller and normally it is not necessary for
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// software to directly read or write fields in the table.
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//
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//*****************************************************************************
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typedef struct
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{
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//
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// The ending source address of the data transfer.
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//
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volatile void *pvSrcEndAddr;
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//
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// The ending destination address of the data transfer.
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//
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volatile void *pvDstEndAddr;
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//
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// The channel control mode.
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//
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volatile unsigned long ulControl;
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//
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// An unused location.
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//
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volatile unsigned long ulSpare;
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}
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tDMAControlTable;
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//*****************************************************************************
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//
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//! A helper macro for building scatter-gather task table entries.
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//!
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//! \param ulTransferCount is the count of items to transfer for this task.
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//! \param ulItemSize is the bit size of the items to transfer for this task.
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//! \param ulSrcIncrement is the bit size increment for source data.
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//! \param pvSrcAddr is the starting address of the data to transfer.
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//! \param ulDstIncrement is the bit size increment for destination data.
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//! \param pvDstAddr is the starting address of the destination data.
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//! \param ulArbSize is the arbitration size to use for the transfer task.
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//! \param ulMode is the transfer mode for this task.
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//!
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//! This macro is intended to be used to help populate a table of uDMA tasks
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//! for a scatter-gather transfer. This macro will calculate the values for
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//! the fields of a task structure entry based on the input parameters.
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//!
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//! There are specific requirements for the values of each parameter. No
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//! checking is done so it is up to the caller to ensure that correct values
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//! are used for the parameters.
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//!
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//! The \e ulTransferCount parameter is the number of items that will be
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//! transferred by this task. It must be in the range 1-1024.
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//!
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//! The \e ulItemSize parameter is the bit size of the transfer data. It must
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//! be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32.
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//!
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//! The \e ulSrcIncrement parameter is the increment size for the source data.
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//! It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16,
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//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE.
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//!
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//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source
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//! data.
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//!
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//! The \e ulDstIncrement parameter is the increment size for the destination
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//! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16,
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//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE.
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//!
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//! The \e pvDstAddr parameter is a void pointer to the beginning of the
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//! location where the data will be transferred.
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//!
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//! The \e ulArbSize parameter is the arbitration size for the transfer, and
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//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on
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//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in
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//! powers of 2, from 1 to 1024.
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//!
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//! The \e ulMode parameter is the mode to use for this transfer task. It
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//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO,
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//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note
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//! that normally all tasks will be one of the scatter-gather modes while the
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//! last task is a task list will be AUTO or BASIC.
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//!
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//! This macro is intended to be used to initialize individual entries of
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//! a structure of tDMAControlTable type, like this:
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//!
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//! \verbatim
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//! tDMAControlTable MyTaskList[] =
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//! {
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//! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8,
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//! UDMA_SRC_INC_8, MySourceBuf,
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//! UDMA_DST_INC_8, MyDestBuf,
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//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER),
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//! uDMATaskStructEntry(Task2Count, ... ),
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//! }
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//! \endverbatim
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//!
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//! \return Nothing; this is not a function.
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//
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//*****************************************************************************
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#define uDMATaskStructEntry(ulTransferCount, \
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ulItemSize, \
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ulSrcIncrement, \
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pvSrcAddr, \
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ulDstIncrement, \
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pvDstAddr, \
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ulArbSize, \
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ulMode) \
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{ \
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(((ulSrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \
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((void *)(&((unsigned char *)(pvSrcAddr))[((ulTransferCount) << \
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((ulSrcIncrement) >> 26)) - 1]))), \
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(((ulDstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) : \
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((void *)(&((unsigned char *)(pvDstAddr))[((ulTransferCount) << \
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((ulDstIncrement) >> 30)) - 1]))), \
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(ulSrcIncrement) | (ulDstIncrement) | (ulItemSize) | (ulArbSize) | \
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(((ulTransferCount) - 1) << 4) | \
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((((ulMode) == UDMA_MODE_MEM_SCATTER_GATHER) || \
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((ulMode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \
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(ulMode) | UDMA_MODE_ALT_SELECT : (ulMode)), 0 \
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}
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//*****************************************************************************
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//
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// Close the Doxygen group.
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//! @}
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Flags that can be passed to uDMAChannelAttributeEnable(),
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// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet().
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//
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//*****************************************************************************
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#define UDMA_ATTR_USEBURST 0x00000001
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#define UDMA_ATTR_ALTSELECT 0x00000002
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#define UDMA_ATTR_HIGH_PRIORITY 0x00000004
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#define UDMA_ATTR_REQMASK 0x00000008
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#define UDMA_ATTR_ALL 0x0000000F
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//*****************************************************************************
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//
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// DMA control modes that can be passed to uDMAModeSet() and returned
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// uDMAModeGet().
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//
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//*****************************************************************************
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#define UDMA_MODE_STOP 0x00000000
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#define UDMA_MODE_BASIC 0x00000001
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#define UDMA_MODE_AUTO 0x00000002
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#define UDMA_MODE_PINGPONG 0x00000003
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#define UDMA_MODE_MEM_SCATTER_GATHER \
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0x00000004
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#define UDMA_MODE_PER_SCATTER_GATHER \
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0x00000006
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#define UDMA_MODE_ALT_SELECT 0x00000001
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//*****************************************************************************
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//
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// Flags to be OR'd with the channel ID to indicate if the primary or alternate
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// control structure should be used.
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//
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//*****************************************************************************
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#define UDMA_PRI_SELECT 0x00000000
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#define UDMA_ALT_SELECT 0x00000020
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//*****************************************************************************
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//
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// uDMA interrupt sources, to be passed to uDMAIntRegister() and
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// uDMAIntUnregister().
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//
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//*****************************************************************************
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#define UDMA_INT_SW INT_UDMA
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#define UDMA_INT_ERR INT_UDMAERR
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//*****************************************************************************
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//*****************************************************************************
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//
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// Channel configuration values that can be passed to uDMAControlSet().
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//
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//*****************************************************************************
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#define UDMA_DST_INC_8 0x00000000
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#define UDMA_DST_INC_16 0x40000000
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#define UDMA_DST_INC_32 0x80000000
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#define UDMA_DST_INC_NONE 0xc0000000
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#define UDMA_SRC_INC_8 0x00000000
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#define UDMA_SRC_INC_16 0x04000000
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#define UDMA_SRC_INC_32 0x08000000
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#define UDMA_SRC_INC_NONE 0x0c000000
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#define UDMA_SIZE_8 0x00000000
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#define UDMA_SIZE_16 0x11000000
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#define UDMA_SIZE_32 0x22000000
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#define UDMA_ARB_1 0x00000000
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#define UDMA_ARB_2 0x00004000
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#define UDMA_ARB_4 0x00008000
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#define UDMA_ARB_8 0x0000c000
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#define UDMA_ARB_16 0x00010000
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#define UDMA_ARB_32 0x00014000
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#define UDMA_ARB_64 0x00018000
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#define UDMA_ARB_128 0x0001c000
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#define UDMA_ARB_256 0x00020000
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#define UDMA_ARB_512 0x00024000
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#define UDMA_ARB_1024 0x00028000
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#define UDMA_NEXT_USEBURST 0x00000008
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//*****************************************************************************
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//
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// Values that can be passed to uDMAChannelAssign() to select peripheral
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// mapping for each channel. The channels named RESERVED may be assigned
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// to a peripheral in future parts.
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//
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//*****************************************************************************
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//
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// Channel 0
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//
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#define UDMA_CH0_TIMERA0_A 0x00000000
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#define UDMA_CH0_SHAMD5_CIN 0x00010000
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#define UDMA_CH0_SW 0x00030000
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//
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// Channel 1
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//
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#define UDMA_CH1_TIMERA0_B 0x00000001
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#define UDMA_CH1_SHAMD5_DIN 0x00010001
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#define UDMA_CH1_SW 0x00030001
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//
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// Channel 2
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//
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#define UDMA_CH2_TIMERA1_A 0x00000002
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#define UDMA_CH2_SHAMD5_COUT 0x00010002
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#define UDMA_CH2_SW 0x00030002
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//
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// Channel 3
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//
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#define UDMA_CH3_TIMERA1_B 0x00000003
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#define UDMA_CH3_DES_CIN 0x00010003
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#define UDMA_CH3_SW 0x00030003
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//
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// Channel 4
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//
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#define UDMA_CH4_TIMERA2_A 0x00000004
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#define UDMA_CH4_DES_DIN 0x00010004
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#define UDMA_CH4_I2S_RX 0x00020004
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#define UDMA_CH4_SW 0x00030004
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//
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// Channel 5
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//
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#define UDMA_CH5_TIMERA2_B 0x00000005
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#define UDMA_CH5_DES_DOUT 0x00010005
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#define UDMA_CH5_I2S_TX 0x00020005
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#define UDMA_CH5_SW 0x00030005
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//
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// Channel 6
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//
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#define UDMA_CH6_TIMERA3_A 0x00000006
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#define UDMA_CH6_GSPI_RX 0x00010006
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#define UDMA_CH6_GPIOA2 0x00020006
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#define UDMA_CH6_SW 0x00030006
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//
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// Channel 7
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//
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#define UDMA_CH7_TIMERA3_B 0x00000007
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#define UDMA_CH7_GSPI_TX 0x00010007
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#define UDMA_CH7_GPIOA3 0x00020007
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#define UDMA_CH7_SW 0x00030007
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//
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// Channel 8
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//
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#define UDMA_CH8_UARTA0_RX 0x00000008
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#define UDMA_CH8_TIMERA0_A 0x00010008
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#define UDMA_CH8_TIMERA2_A 0x00020008
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#define UDMA_CH8_SW 0x00030008
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//
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// Channel 9
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//
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#define UDMA_CH9_UARTA0_TX 0x00000009
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#define UDMA_CH9_TIMERA0_B 0x00010009
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#define UDMA_CH9_TIMERA2_B 0x00020009
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#define UDMA_CH9_SW 0x00030009
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//
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// Channel 10
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//
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#define UDMA_CH10_UARTA1_RX 0x0000000A
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#define UDMA_CH10_TIMERA1_A 0x0001000A
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#define UDMA_CH10_TIMERA3_A 0x0002000A
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#define UDMA_CH10_SW 0x0003000A
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//
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// Channel 11
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//
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#define UDMA_CH11_UARTA1_TX 0x0000000B
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#define UDMA_CH11_TIMERA1_B 0x0001000B
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#define UDMA_CH11_TIMERA3_B 0x0002000B
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#define UDMA_CH11_SW 0x0003000B
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//
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// Channel 12
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//
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#define UDMA_CH12_LSPI_RX 0x0000000C
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#define UDMA_CH12_SW 0x0003000C
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//
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// Channel 13
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//
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#define UDMA_CH13_LSPI_TX 0x0000000D
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#define UDMA_CH13_SW 0x0003000D
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//
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// Channel 14
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//
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#define UDMA_CH14_ADC_CH0 0x0000000E
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#define UDMA_CH14_SDHOST_RX 0x0002000E
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#define UDMA_CH14_SW 0x0003000E
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//
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// Channel 15
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//
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#define UDMA_CH15_ADC_CH1 0x0000000F
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#define UDMA_CH15_SDHOST_TX 0x0002000F
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#define UDMA_CH15_SW 0x0003000F
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//
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// Channel 16
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//
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#define UDMA_CH16_ADC_CH2 0x00000010
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#define UDMA_CH16_TIMERA2_A 0x00010010
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#define UDMA_CH16_SW 0x00030010
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//
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// Channel 17
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//
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#define UDMA_CH17_ADC_CH3 0x00000011
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#define UDMA_CH17_TIMERA2_B 0x00010011
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#define UDMA_CH17_SW 0x00030011
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//
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// Channel 18
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//
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#define UDMA_CH18_GPIOA0 0x00000012
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#define UDMA_CH18_AES_CIN 0x00010012
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#define UDMA_CH18_I2S_RX 0x00020012
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#define UDMA_CH18_SW 0x00030012
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//
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// Channel 19
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//
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#define UDMA_CH19_GPOIA1 0x00000013
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#define UDMA_CH19_AES_COUT 0x00010013
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#define UDMA_CH19_I2S_TX 0x00020013
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#define UDMA_CH19_SW 0x00030013
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//
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// Channel 20
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//
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#define UDMA_CH20_GPIOA2 0x00000014
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#define UDMA_CH20_AES_DIN 0x00010014
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#define UDMA_CH20_SW 0x00030014
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//
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// Channel 21
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//
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#define UDMA_CH21_GPIOA3 0x00000015
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#define UDMA_CH21_AES_DOUT 0x00010015
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#define UDMA_CH21_SW 0x00030015
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//
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// Channel 22
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//
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#define UDMA_CH22_CAMERA 0x00000016
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#define UDMA_CH22_GPIOA4 0x00010016
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#define UDMA_CH22_SW 0x00030016
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//
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// Channel 23
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//
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#define UDMA_CH23_SDHOST_RX 0x00000017
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#define UDMA_CH23_TIMERA3_A 0x00010017
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#define UDMA_CH23_TIMERA2_A 0x00020017
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#define UDMA_CH23_SW 0x00030017
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//
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// Channel 24
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//
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#define UDMA_CH24_SDHOST_TX 0x00000018
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#define UDMA_CH24_TIMERA3_B 0x00010018
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#define UDMA_CH24_TIMERA2_B 0x00020018
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#define UDMA_CH24_SW 0x00030018
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//
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// Channel 25
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//
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#define UDMA_CH25_SSPI_RX 0x00000019
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#define UDMA_CH25_I2CA0_RX 0x00010019
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#define UDMA_CH25_SW 0x00030019
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//
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// Channel 26
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//
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#define UDMA_CH26_SSPI_TX 0x0000001A
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#define UDMA_CH26_I2CA0_TX 0x0001001A
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#define UDMA_CH26_SW 0x0003001A
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//
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// Channel 27
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//
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#define UDMA_CH27_GPIOA0 0x0001001B
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#define UDMA_CH27_SW 0x0003001B
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//
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// Channel 28
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//
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#define UDMA_CH28_GPIOA1 0x0001001C
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#define UDMA_CH28_SW 0x0003001C
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//
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// Channel 29
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//
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#define UDMA_CH29_GPIOA4 0x0000001D
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#define UDMA_CH29_SW 0x0003001D
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//
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// Channel 30
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//
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#define UDMA_CH30_GSPI_RX 0x0000001E
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#define UDMA_CH30_SDHOST_RX 0x0001001E
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#define UDMA_CH30_I2CA0_RX 0x0002001E
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#define UDMA_CH30_SW 0x0003001E
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//
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// Channel 31
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//
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#define UDMA_CH31_GSPI_TX 0x0000001F
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#define UDMA_CH31_SDHOST_TX 0x0001001F
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#define UDMA_CH31_I2CA0_RX 0x0002001F
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#define UDMA_CH31_SW 0x0003001F
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//*****************************************************************************
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//
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// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
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|
//
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//*****************************************************************************
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#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End
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// Pointer
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#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address
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// End Pointer
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#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word
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//*****************************************************************************
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|
//
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// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
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//
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//*****************************************************************************
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#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer
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#define UDMA_SRCENDP_ADDR_S 0
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|
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//*****************************************************************************
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//
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|
// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
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|
//
|
|
//*****************************************************************************
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|
#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer
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#define UDMA_DSTENDP_ADDR_S 0
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|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the UDMA_O_CHCTL register.
|
|
//
|
|
//*****************************************************************************
|
|
#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment
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#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
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|
#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
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|
#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
|
|
#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
|
|
#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size
|
|
#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
|
|
#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
|
|
#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
|
|
#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment
|
|
#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
|
|
#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
|
|
#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
|
|
#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
|
|
#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size
|
|
#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
|
|
#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
|
|
#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
|
|
#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size
|
|
#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
|
|
#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
|
|
#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
|
|
#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
|
|
#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
|
|
#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
|
|
#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
|
|
#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
|
|
#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
|
|
#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
|
|
#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
|
|
#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1)
|
|
#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst
|
|
#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode
|
|
#define UDMA_CHCTL_XFERMODE_STOP \
|
|
0x00000000 // Stop
|
|
#define UDMA_CHCTL_XFERMODE_BASIC \
|
|
0x00000001 // Basic
|
|
#define UDMA_CHCTL_XFERMODE_AUTO \
|
|
0x00000002 // Auto-Request
|
|
#define UDMA_CHCTL_XFERMODE_PINGPONG \
|
|
0x00000003 // Ping-Pong
|
|
#define UDMA_CHCTL_XFERMODE_MEM_SG \
|
|
0x00000004 // Memory Scatter-Gather
|
|
#define UDMA_CHCTL_XFERMODE_MEM_SGA \
|
|
0x00000005 // Alternate Memory Scatter-Gather
|
|
#define UDMA_CHCTL_XFERMODE_PER_SG \
|
|
0x00000006 // Peripheral Scatter-Gather
|
|
#define UDMA_CHCTL_XFERMODE_PER_SGA \
|
|
0x00000007 // Alternate Peripheral
|
|
// Scatter-Gather
|
|
#define UDMA_CHCTL_XFERSIZE_S 4
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// API Function prototypes
|
|
//
|
|
//*****************************************************************************
|
|
extern void uDMAEnable(void);
|
|
extern void uDMADisable(void);
|
|
extern unsigned long uDMAErrorStatusGet(void);
|
|
extern void uDMAErrorStatusClear(void);
|
|
extern void uDMAChannelEnable(unsigned long ulChannelNum);
|
|
extern void uDMAChannelDisable(unsigned long ulChannelNum);
|
|
extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannelNum);
|
|
extern void uDMAControlBaseSet(void *pControlTable);
|
|
extern void *uDMAControlBaseGet(void);
|
|
extern void *uDMAControlAlternateBaseGet(void);
|
|
extern void uDMAChannelRequest(unsigned long ulChannelNum);
|
|
extern void uDMAChannelAttributeEnable(unsigned long ulChannelNum,
|
|
unsigned long ulAttr);
|
|
extern void uDMAChannelAttributeDisable(unsigned long ulChannelNum,
|
|
unsigned long ulAttr);
|
|
extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannelNum);
|
|
extern void uDMAChannelControlSet(unsigned long ulChannelStructIndex,
|
|
unsigned long ulControl);
|
|
extern void uDMAChannelTransferSet(unsigned long ulChannelStructIndex,
|
|
unsigned long ulMode, void *pvSrcAddr,
|
|
void *pvDstAddr,
|
|
unsigned long ulTransferSize);
|
|
extern void uDMAChannelScatterGatherSet(unsigned long ulChannelNum,
|
|
unsigned ulTaskCount, void *pvTaskList,
|
|
unsigned long ulIsPeriphSG);
|
|
extern unsigned long uDMAChannelSizeGet(unsigned long ulChannelStructIndex);
|
|
extern unsigned long uDMAChannelModeGet(unsigned long ulChannelStructIndex);
|
|
extern void uDMAIntRegister(unsigned long ulIntChannel,
|
|
void (*pfnHandler)(void));
|
|
extern void uDMAIntUnregister(unsigned long ulIntChannel);
|
|
extern unsigned long uDMAIntStatus(void);
|
|
extern void uDMAIntClear(unsigned long ulChanMask);
|
|
extern void uDMAChannelAssign(unsigned long ulMapping);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Mark the end of the C bindings section for C++ compilers.
|
|
//
|
|
//*****************************************************************************
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif // __UDMA_H__
|