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source/firmware/arch/stm32f4xx/lib/stdperiph/CMSIS/Documentation/CMSIS-SVD_Schema_1_0.xsd Executable file
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<?xml version="1.0" encoding="UTF-8"?>
<!--
@date: 29.07.2011
@note Copyright (C) 2011 ARM Limited. All rights reserved.
@par
ARM Limited (ARM) is supplying this software for use with Cortex-M
processor based microcontroller, but can be equally used for other
suitable processor architectures. This file can be freely distributed.
Modifications to this file shall be clearly marked.
@par
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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<html>
<head>
<title>CMSIS Debug Support</title>
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<body>
<h1>CMSIS Debug Support</h1>
<p align="center">This file describes the CMSIS Debug support available with CMSIS (starting V1.30).</p>
<p align="center">Version: 1.02 - 25. July 2011</p>
<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
Copyright <20> ARM Ltd.<br>All rights reserved.
</p>
<hr>
<p><span style="FONT-WEIGHT: bold">Revision History</span></p>
<ul>
<li>Version 1.00: Initial Release. </li>
<li>Version 1.01: Internal Review. </li>
<li>Version 1.02: Removed product specific information. </li>
</ul>
<hr>
<h2>Contents</h2>
<ol>
<li class="LI2"><a href="#About">About</a></li>
<li class="LI2"><a href="#ITM_DbgAcc">Cortex-M3 / Cortex-M4 ITM Debug Access</a></li>
<li class="LI2"><a href="#DbgIn_DbgOut">Debug IN / OUT functions</a></li>
<li class="LI2"><a href="#ITM_DbgSup">ITM Debug Support in Debugger</a></li>
</ol>
<p>&nbsp;</p>
<h2><a name="About"></a>About</h2>
<p>
CMSIS provides for Cortex-M3 / Cortex-M4 processor based microcontrollers debug support via the Instrumented Trace Macrocell (ITM).
This document describes the available CMSIS Debug functions and the used methods.
</p>
<p>&nbsp;</p>
<h2><a name="ITM_DbgAcc"></a>Cortex-M3 / Cortex-M4 ITM Debug Access</h2>
<p>
The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with
the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has
32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM
communication channels are used by CMSIS to output the following information:
</p>
<ul>
<li>ITM Channel 0: used for printf-style output via the debug interface.</li>
<li>ITM Channel 31: is reserved for RTOS kernel awareness debugging.</li>
</ul>
<p>&nbsp;</p>
<h2><a name="DbgIn_DbgOut"></a>Debug IN / OUT functions</h2>
<p>CMSIS provides following debug functions:</p>
<ul>
<li>ITM_SendChar (uses ITM channel 0)</li>
<li>ITM_ReceiveChar (uses global variable)</li>
<li>ITM_CheckChar (uses global variable)</li>
</ul>
<h3>ITM_SendChar</h3>
<p>
<strong>ITM_SendChar</strong> is used to transmit a character over ITM channel 0 from
the microcontroller system to the debug system. <br>
Only a 8 bit value is transmitted.
</p>
<pre>
static __INLINE uint32_t ITM_SendChar (uint32_t ch)
{
/* check if debugger connected and ITM channel enabled for tracing */
if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &amp;&amp;
(ITM-&gt;TCR & ITM_TCR_ITMENA) &amp;&amp;
(ITM-&gt;TER & (1UL &lt;&lt; 0)) )
{
while (ITM-&gt;PORT[0].u32 == 0);
ITM-&gt;PORT[0].u8 = (uint8_t)ch;
}
return (ch);
}</pre>
<h3>ITM_ReceiveChar</h3>
<p>
ITM communication channel is only capable for OUT direction. For IN direction
a global variable is used. A simple mechanism detects if a character is received.
The project to test need to be build with debug information.
</p>
<p>
The global variable <strong>ITM_RxBuffer</strong> is used to transmit a 8 bit value from debug system
to microcontroller system. <strong>ITM_RxBuffer</strong> is 32 bit wide to
ensure a proper handshake.
</p>
<pre>
extern volatile int32_t ITM_RxBuffer; /* variable to receive characters */
</pre>
<p>
A dedicated bit pattern is used to determine if <strong>ITM_RxBuffer</strong> is empty
or contains a valid value.
</p>
<pre>
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
</pre>
<p>
<strong>ITM_ReceiveChar</strong> is used to receive a 8 bit value from the debug system. The function is nonblocking.
It returns the received character or '-1' if no character was available.
</p>
<pre>
static __INLINE int32_t ITM_ReceiveChar (void) {
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
</pre>
<h3>ITM_CheckChar</h3>
<p>
<strong>ITM_CheckChar</strong> is used to check if a character is received.
</p>
<pre>
static __INLINE int32_t ITM_CheckChar (void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
} else {
return (1); /* character available */
}
}</pre>
<p>&nbsp;</p>
<h2><a name="ITM_DbgSup"></a>ITM Debug Support in a Debugger</h2>
<p>
The Debugger shall offer a dedicated console window for printf style debug input and output using the CMSIS defined ITM methods described above.
</p>
<p>Direction: Microcontroller -&gt; Debugger:</p>
<ul>
<li>
at the beginning of a debug session the debugger shall enable ITM trace on channel 0 and continuously snoop for channel 0 data on the ITM trace
stream it receives from the Microcontroller's CoreSight ITM unit
</li>
<li>
data received via the ITM communication channel 0 is interpreted as charater and gets redirected into the dedicated <strong>Console Window</strong>
</li>
</ul>
<p>Direction: Debugger -&gt; Microcontroller:</p>
<ul>
<li>
at the beginning of a debug session the debugger shall seek for the presence of the global variable named <strong>ITM_RxBuffer</strong> in the debug
information of the application being loaded
</li>
<li>
strings entered into the <strong>Console Window</strong> are written by the debugger as a stream of char values via the variable <strong>ITM_RxBuffer</strong>.
</li>
<li>
the debugger writes the next character into the <strong>ITM_RxBuffer</strong> only once the value has been read and the <strong>ITM_RXBUFFER_EMPTY</strong> value being set.
(refer to: ITM_ReceiveChar()).
</ul>
</body>
</html>

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<body>
<h1>CMSIS Version History</h1>
<p align="center">This document describes the changes between the different CMSIS versions.</p>
<p align="center">Version: 2.10 - July 2011</p>
<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
Copyright <20> ARM Ltd.<br>All rights reserved.
</p>
<hr>
<h2>Contents</h2>
<ol>
<li class="LI2"><a href="#Toolchain">Used Toolchains</a></li>
<li class="LI2"><a href="#6">Changes to version V2.00</a></li>
<li class="LI2"><a href="#5">Changes to version V1.30</a></li>
<li class="LI2"><a href="#4">Changes to version V1.20</a></li>
<li class="LI2"><a href="#2">Open Points</a></li>
<li class="LI2"><a href="#1">Limitations</a></li>
</ol>
<h2><a name="Toolchain"></a>Used Toolchains</h2>
<p>
Following toolchains have been used for test / verification:</i>.
</p>
<ul>
<li>ARM: MDK-ARM Version 4.21</li>
<li>GNU: Sourcery G++ Lite Edition for ARM 2010.09-51</li>
<li>IAR: IAR Embedded Workbench Kickstart Edition V6.10</li>
</ul>
<h2><a name="6"></a>Changes to version V2.00</h2>
<h3>Added CMSIS DSP Software Library support for Cortex-M0 based MCUs</h3>
<p>
The <strong>CMSIS DSP Software Library</strong> provides now also libraries and examples for Cortex-M0.
</p>
<p>
For more information refer to <i>CMSIS DSP Library documentation</i>.
</p>
<h3>Added big endian support for DSP library</h3>
<p>
The <strong>CMSIS DSP Software Library</strong> provides now also pre-build libraries
and projects for big endian devices.
</p>
<p>
For more information refer to <i>CMSIS DSP Library documentation</i>.
</p>
<h3>Simplified folder structure for CMSIS include files</h3>
<p>
All CMSIS core include files as well as the DSP-Library header files are located in
a single folder <strong>./CMSIS/Include</strong>.
</p>
<h3>Changed folder structure for Device Support packages</h3>
<p>
Device Support packages are expected to be in folder <strong>./Device</strong> located at the
same level as <strong>./CMSIS</strong>.
</p>
<p>The new Device folder contains the following subfolders:</p>
<ul>
<li><b>Device</b></li>
<ul>
<li>&lt;<b>Vendor</b>&gt;
<ul>
<li>&lt;<b>Device</b>&gt; | &lt;<b>Device Series</b>&gt;
<ul>
<li><b>Include</b><br>
&lt;device&gt;.h<br>
system_&lt;device&gt;.h<br>
</li>
<li><b>Source</b>
<ul>
<li><b>Templates</b><br>
system_&lt;device&gt;.c<br>
<ul>
<li>&lt;<b>Toolchain</b>&gt;<br>
startup_&lt;device&gt;.s<br>
</li>
<li>&lt;<b>Toolchain</b>&gt;</li>
<li>...</li>
</ul>
</li>
</ul>
</li>
</ul>
<li>&lt;<b>Device</b>&gt; | &lt;<b>Device Series</b>&gt;</li>
<li>...</li>
</ul>
</li>
<li>&lt;<b>Vendor</b>&gt;</li>
<li>...</li>
</ul>
</li>
</ul>
<p>Template files are application specific files and are required to be copied to the project prior to use!</p>
<h3>Removed CMSIS core source files</h3>
<p>
The CMSIS core source files <strong>core_cm0.c, core_cm3.c, core_cm4.c</strong>
containing helper functions for older ARM compiler versions got removed.
</p>
<p>
For the <b>ARM Compiler Toolchain </b>version <b>V4.0.677</b> or later is
required!</p>
<h2><a name="5"></a>Changes to version V1.30</h2>
<h3>Added CMSIS DSP Software Library</h3>
<p>
The <strong>CMSIS DSP Software Library</strong> is a suite of common signal processing functions targeted
to Cortex-M processor based microcontrollers. Even though the code has been specifically
optimized towards using the extended DSP instruction set of the Cortex-M4 processor,
the library can be compiled for any Cortex-M processor.
</p>
<p>
For more information see <i>CMSIS DSP Library documentation</i>.
</p>
<h3>Added CMSIS System View Description</h3>
<p>
The <strong>CMSIS System View Description</strong> answers the challenges of accurate, detailed and
timely device aware peripheral debugging support for Cortex Microcontroller based
devices by the software development tools vendor community.
</p>
<p>
Silicon vendors shall create and maintain a formalized description of the debug view
for all the peripherals contained in their Cortex Microcontroller based devices.
Tool vendors use such descriptions to establish device specific debug support in
their debugging tools.
</p>
<p>
A standardized System View Description shall provide a common approach to
capturing peripheral debug related information in a machine readable files.
</p>
<p>
For more information see <i>CMSIS System View Description</i>.
</p>
<h3>Added Cortex-M4 Core Support</h3>
<p>
Additional folder <strong>CM4</strong>, containing the Cortex-M4 core support files, has been added.
</p>
<ul>
<li>CM0</li>
<li>CM3</li>
<li>CM4
<ul>
<li>CoreSupport</li>
<li>DeviceSupport</li>
</ul>
</li>
</ul>
<h3>New naming for Core Support Files</h3>
<p>
The new Core Support Files are:
</p>
<ul>
<li>core_cm#.h (# = 0, 3, 4)</li>
<li>core_cmFunc.h (Cortex-M Core Register access functions)</li>
<li>core_cmInstr.h (Cortex-M Core instructions)</li>
<li>core_cm4_simd.h (Cortex-M4 SIMD instructions)</li>
</ul>
<h2><a name="4"></a>Changes to version V1.20</h2>
<h3>Removed CMSIS Middelware packages</h3>
<p>
CMSIS Middleware is removed and no longer focus of CMSIS.
</p>
<h3>SystemFrequency renamed to SystemCoreClock</h3>
<p>
The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>
because the variable holds the clock value at which the core is running.
</p>
<h3>Changed startup concept</h3>
<p>
The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
from main) has the weakness that it does not work for controllers which need a already
configuerd clock system to configure the external memory controller.
</p>
<h5>Changed startup concept</h5>
<ul>
<li>
SystemInit() is called from startup file before <strong>premain</strong>.
</li>
<li>
<strong>SystemInit()</strong> configures the clock system and also configures
an existing external memory controller.
</li>
<li>
<strong>SystemInit()</strong> must not use global variables.
</li>
<li>
<strong>SystemCoreClock</strong> is initialized with a correct predefined value.
</li>
<li>
Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>
<strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>
and must be called whenever the core clock is changed.<br>
<strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates
the current core clock.
</li>
</ul>
<h3>Advanced Debug Functions</h3>
<p>
ITM communication channel is only capable for OUT direction. To allow also communication for
IN direction a simple concept is provided.
</p>
<ul>
<li>
Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.
</li>
<li>
Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.
</li>
<li>
Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.
</li>
</ul>
<p>
For detailed explanation see file <strong>CMSIS debug support.htm</strong>.
</p>
<h3>Core Register Bit Definitions</h3>
<p>
Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
defines correspond with the Cortex-M Technical Reference Manual.
</p>
<p>
e.g. SysTick structure with bit definitions
</p>
<pre>
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */</pre>
<h3>DoxyGen Tags</h3>
<p>
DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
using DoxyGen.
</p>
<h3>Folder Structure</h3>
<p>
The folder structure is changed to differentiate the single support packages.
</p>
<ul>
<li>CM0</li>
<li>CM3
<ul>
<li>CoreSupport</li>
<li>DeviceSupport</li>
<ul>
<li>Vendor
<ul>
<li>Device
<ul>
<li>Startup
<ul>
<li>Toolchain</li>
<li>Toolchain</li>
<li>...</li>
</ul>
</li>
</ul>
</li>
<li>Device</li>
<li>...</li>
</ul>
</li>
<li>Vendor</li>
<li>...</li>
</ul>
</li>
<li>Example <i>(optional)</i>
<ul>
<li>Toolchain
<ul>
<li>Device</li>
<li>Device</li>
<li>...</li>
</ul>
</li>
<li>Toolchain</li>
<li>...</li>
</ul>
</li>
</ul>
</li>
<li>Documentation</li>
</ul>
<h2><a name="2"></a>Open Points</h2>
<p>
Following points need to be clarified and solved:
</p>
<ul>
<li>
<p>
Equivalent C and Assembler startup files.
</p>
<p>
Is there a need for having C startup files although assembler startup files are
very efficient and do not need to be changed?
<p/>
</li>
<li>
<p>
Placing of HEAP in external RAM.
</p>
<p>
It must be possible to place HEAP in external RAM if the device supports an
external memory controller.
</p>
</li>
<li>
<p>
Placing of STACK /HEAP.
</p>
<p>
STACK should always be placed at the end of internal RAM.
</p>
<p>
If HEAP is placed in internal RAM than it should be placed after RW ZI section.
</p>
</li>
</ul>
<h2><a name="1"></a>Limitations</h2>
<p>
The following limitations are not covered with the current CMSIS version:
</p>
<ul>
<li>
No <strong>C startup files</strong> are available.
</li>
</ul>

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<h1>Data Structures</h1> </div>
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Here are the data structures with brief descriptions:<table>
<tr><td class="indexkey"><a class="el" href="structarm__bilinear__interp__instance__f32.html">arm_bilinear_interp_instance_f32</a></td><td class="indexvalue">Instance structure for the floating-point bilinear interpolation function </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__bilinear__interp__instance__q15.html">arm_bilinear_interp_instance_q15</a></td><td class="indexvalue">Instance structure for the Q15 bilinear interpolation function </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__bilinear__interp__instance__q31.html">arm_bilinear_interp_instance_q31</a></td><td class="indexvalue">Instance structure for the Q31 bilinear interpolation function </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__bilinear__interp__instance__q7.html">arm_bilinear_interp_instance_q7</a></td><td class="indexvalue">Instance structure for the Q15 bilinear interpolation function </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__biquad__cas__df1__32x64__ins__q31.html">arm_biquad_cas_df1_32x64_ins_q31</a></td><td class="indexvalue">Instance structure for the high precision Q31 Biquad cascade filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__biquad__cascade__df2_t__instance__f32.html">arm_biquad_cascade_df2T_instance_f32</a></td><td class="indexvalue">Instance structure for the floating-point transposed direct form II Biquad cascade filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__biquad__casd__df1__inst__f32.html">arm_biquad_casd_df1_inst_f32</a></td><td class="indexvalue">Instance structure for the floating-point Biquad cascade filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__biquad__casd__df1__inst__q15.html">arm_biquad_casd_df1_inst_q15</a></td><td class="indexvalue">Instance structure for the Q15 Biquad cascade filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__biquad__casd__df1__inst__q31.html">arm_biquad_casd_df1_inst_q31</a></td><td class="indexvalue">Instance structure for the Q31 Biquad cascade filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__cfft__radix4__instance__f32.html">arm_cfft_radix4_instance_f32</a></td><td class="indexvalue">Instance structure for the floating-point CFFT/CIFFT function </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__cfft__radix4__instance__q15.html">arm_cfft_radix4_instance_q15</a></td><td class="indexvalue">Instance structure for the Q15 CFFT/CIFFT function </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__cfft__radix4__instance__q31.html">arm_cfft_radix4_instance_q31</a></td><td class="indexvalue">Instance structure for the Q31 CFFT/CIFFT function </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__dct4__instance__f32.html">arm_dct4_instance_f32</a></td><td class="indexvalue">Instance structure for the floating-point DCT4/IDCT4 function </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__dct4__instance__q15.html">arm_dct4_instance_q15</a></td><td class="indexvalue">Instance structure for the Q15 DCT4/IDCT4 function </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__dct4__instance__q31.html">arm_dct4_instance_q31</a></td><td class="indexvalue">Instance structure for the Q31 DCT4/IDCT4 function </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__fir__decimate__instance__f32.html">arm_fir_decimate_instance_f32</a></td><td class="indexvalue">Instance structure for the floating-point FIR decimator </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__fir__decimate__instance__q15.html">arm_fir_decimate_instance_q15</a></td><td class="indexvalue">Instance structure for the Q15 FIR decimator </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__fir__decimate__instance__q31.html">arm_fir_decimate_instance_q31</a></td><td class="indexvalue">Instance structure for the Q31 FIR decimator </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__fir__instance__f32.html">arm_fir_instance_f32</a></td><td class="indexvalue">Instance structure for the floating-point FIR filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__fir__instance__q15.html">arm_fir_instance_q15</a></td><td class="indexvalue">Instance structure for the Q15 FIR filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__fir__instance__q31.html">arm_fir_instance_q31</a></td><td class="indexvalue">Instance structure for the Q31 FIR filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__fir__instance__q7.html">arm_fir_instance_q7</a></td><td class="indexvalue">Instance structure for the Q7 FIR filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__fir__interpolate__instance__f32.html">arm_fir_interpolate_instance_f32</a></td><td class="indexvalue">Instance structure for the floating-point FIR interpolator </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__fir__interpolate__instance__q15.html">arm_fir_interpolate_instance_q15</a></td><td class="indexvalue">Instance structure for the Q15 FIR interpolator </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__fir__interpolate__instance__q31.html">arm_fir_interpolate_instance_q31</a></td><td class="indexvalue">Instance structure for the Q31 FIR interpolator </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__fir__lattice__instance__f32.html">arm_fir_lattice_instance_f32</a></td><td class="indexvalue">Instance structure for the floating-point FIR lattice filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__fir__lattice__instance__q15.html">arm_fir_lattice_instance_q15</a></td><td class="indexvalue">Instance structure for the Q15 FIR lattice filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__fir__lattice__instance__q31.html">arm_fir_lattice_instance_q31</a></td><td class="indexvalue">Instance structure for the Q31 FIR lattice filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__fir__sparse__instance__f32.html">arm_fir_sparse_instance_f32</a></td><td class="indexvalue">Instance structure for the floating-point sparse FIR filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__fir__sparse__instance__q15.html">arm_fir_sparse_instance_q15</a></td><td class="indexvalue">Instance structure for the Q15 sparse FIR filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__fir__sparse__instance__q31.html">arm_fir_sparse_instance_q31</a></td><td class="indexvalue">Instance structure for the Q31 sparse FIR filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__fir__sparse__instance__q7.html">arm_fir_sparse_instance_q7</a></td><td class="indexvalue">Instance structure for the Q7 sparse FIR filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__iir__lattice__instance__f32.html">arm_iir_lattice_instance_f32</a></td><td class="indexvalue">Instance structure for the floating-point IIR lattice filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__iir__lattice__instance__q15.html">arm_iir_lattice_instance_q15</a></td><td class="indexvalue">Instance structure for the Q15 IIR lattice filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__iir__lattice__instance__q31.html">arm_iir_lattice_instance_q31</a></td><td class="indexvalue">Instance structure for the Q31 IIR lattice filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__linear__interp__instance__f32.html">arm_linear_interp_instance_f32</a></td><td class="indexvalue">Instance structure for the floating-point Linear Interpolate function </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__lms__instance__f32.html">arm_lms_instance_f32</a></td><td class="indexvalue">Instance structure for the floating-point LMS filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__lms__instance__q15.html">arm_lms_instance_q15</a></td><td class="indexvalue">Instance structure for the Q15 LMS filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__lms__instance__q31.html">arm_lms_instance_q31</a></td><td class="indexvalue">Instance structure for the Q31 LMS filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__lms__norm__instance__f32.html">arm_lms_norm_instance_f32</a></td><td class="indexvalue">Instance structure for the floating-point normalized LMS filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__lms__norm__instance__q15.html">arm_lms_norm_instance_q15</a></td><td class="indexvalue">Instance structure for the Q15 normalized LMS filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__lms__norm__instance__q31.html">arm_lms_norm_instance_q31</a></td><td class="indexvalue">Instance structure for the Q31 normalized LMS filter </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__matrix__instance__f32.html">arm_matrix_instance_f32</a></td><td class="indexvalue">Instance structure for the floating-point matrix structure </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__matrix__instance__q15.html">arm_matrix_instance_q15</a></td><td class="indexvalue">Instance structure for the Q15 matrix structure </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__matrix__instance__q31.html">arm_matrix_instance_q31</a></td><td class="indexvalue">Instance structure for the Q31 matrix structure </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__pid__instance__f32.html">arm_pid_instance_f32</a></td><td class="indexvalue">Instance structure for the floating-point PID Control </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__pid__instance__q15.html">arm_pid_instance_q15</a></td><td class="indexvalue">Instance structure for the Q15 PID Control </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__pid__instance__q31.html">arm_pid_instance_q31</a></td><td class="indexvalue">Instance structure for the Q31 PID Control </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__rfft__instance__f32.html">arm_rfft_instance_f32</a></td><td class="indexvalue">Instance structure for the floating-point RFFT/RIFFT function </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__rfft__instance__q15.html">arm_rfft_instance_q15</a></td><td class="indexvalue">Instance structure for the Q15 RFFT/RIFFT function </td></tr>
<tr><td class="indexkey"><a class="el" href="structarm__rfft__instance__q31.html">arm_rfft_instance_q31</a></td><td class="indexvalue">Instance structure for the Q31 RFFT/RIFFT function </td></tr>
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
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Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___basic_abs.html#ga421b6275f9d35f50286c0ff3beceff02">arm_abs_f32</a> (<a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> *pSrc, <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> *pDst, uint32_t <a class="el" href="arm__variance__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)</td></tr>
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<h1>arm_abs_f32.c</h1> </div>
</div>
<div class="contents">
<a href="arm__abs__f32_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ---------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_abs_f32.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: Vector absolute value. </span>
<a name="l00011"></a>00011 <span class="comment">* </span>
<a name="l00012"></a>00012 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0</span>
<a name="l00013"></a>00013 <span class="comment">* </span>
<a name="l00014"></a>00014 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00015"></a>00015 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00016"></a>00016 <span class="comment">* </span>
<a name="l00017"></a>00017 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00018"></a>00018 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00019"></a>00019 <span class="comment">* </span>
<a name="l00020"></a>00020 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00021"></a>00021 <span class="comment">* Documentation updated. </span>
<a name="l00022"></a>00022 <span class="comment">* </span>
<a name="l00023"></a>00023 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00024"></a>00024 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00025"></a>00025 <span class="comment">* </span>
<a name="l00026"></a>00026 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00027"></a>00027 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00028"></a>00028 <span class="comment">* </span>
<a name="l00029"></a>00029 <span class="comment">* Version 0.0.7 2010/06/10 </span>
<a name="l00030"></a>00030 <span class="comment">* Misra-C changes done </span>
<a name="l00031"></a>00031 <span class="comment">* ---------------------------------------------------------------------------- */</span>
<a name="l00032"></a>00032
<a name="l00033"></a>00033 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00034"></a>00034 <span class="preprocessor">#include &lt;math.h&gt;</span>
<a name="l00035"></a>00035
<a name="l00066"></a><a class="code" href="group___basic_abs.html#ga421b6275f9d35f50286c0ff3beceff02">00066</a> <span class="keywordtype">void</span> <a class="code" href="group___basic_abs.html#ga421b6275f9d35f50286c0ff3beceff02" title="Floating-point vector absolute value.">arm_abs_f32</a>(
<a name="l00067"></a>00067 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> * pSrc,
<a name="l00068"></a>00068 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> * pDst,
<a name="l00069"></a>00069 uint32_t <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)
<a name="l00070"></a>00070 {
<a name="l00071"></a>00071 uint32_t blkCnt; <span class="comment">/* loop counter */</span>
<a name="l00072"></a>00072
<a name="l00073"></a>00073 <span class="preprocessor">#ifndef ARM_MATH_CM0</span>
<a name="l00074"></a>00074 <span class="preprocessor"></span>
<a name="l00075"></a>00075 <span class="comment">/* Run the below code for Cortex-M4 and Cortex-M3 */</span>
<a name="l00076"></a>00076
<a name="l00077"></a>00077 <span class="comment">/*loop Unrolling */</span>
<a name="l00078"></a>00078 blkCnt = blockSize &gt;&gt; 2u;
<a name="l00079"></a>00079
<a name="l00080"></a>00080 <span class="comment">/* First part of the processing with loop unrolling. Compute 4 outputs at a time. </span>
<a name="l00081"></a>00081 <span class="comment"> ** a second loop below computes the remaining 1 to 3 samples. */</span>
<a name="l00082"></a>00082 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00083"></a>00083 {
<a name="l00084"></a>00084 <span class="comment">/* C = |A| */</span>
<a name="l00085"></a>00085 <span class="comment">/* Calculate absolute and then store the results in the destination buffer. */</span>
<a name="l00086"></a>00086 *pDst++ = fabsf(*pSrc++);
<a name="l00087"></a>00087 *pDst++ = fabsf(*pSrc++);
<a name="l00088"></a>00088 *pDst++ = fabsf(*pSrc++);
<a name="l00089"></a>00089 *pDst++ = fabsf(*pSrc++);
<a name="l00090"></a>00090
<a name="l00091"></a>00091 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00092"></a>00092 blkCnt--;
<a name="l00093"></a>00093 }
<a name="l00094"></a>00094
<a name="l00095"></a>00095 <span class="comment">/* If the blockSize is not a multiple of 4, compute any remaining output samples here. </span>
<a name="l00096"></a>00096 <span class="comment"> ** No loop unrolling is used. */</span>
<a name="l00097"></a>00097 blkCnt = blockSize % 0x4u;
<a name="l00098"></a>00098
<a name="l00099"></a>00099 <span class="preprocessor">#else</span>
<a name="l00100"></a>00100 <span class="preprocessor"></span>
<a name="l00101"></a>00101 <span class="comment">/* Run the below code for Cortex-M0 */</span>
<a name="l00102"></a>00102
<a name="l00103"></a>00103 <span class="comment">/* Initialize blkCnt with number of samples */</span>
<a name="l00104"></a>00104 blkCnt = <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>;
<a name="l00105"></a>00105
<a name="l00106"></a>00106 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_CM0 */</span>
<a name="l00107"></a>00107
<a name="l00108"></a>00108 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00109"></a>00109 {
<a name="l00110"></a>00110 <span class="comment">/* C = |A| */</span>
<a name="l00111"></a>00111 <span class="comment">/* Calculate absolute and then store the results in the destination buffer. */</span>
<a name="l00112"></a>00112 *pDst++ = fabsf(*pSrc++);
<a name="l00113"></a>00113
<a name="l00114"></a>00114 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00115"></a>00115 blkCnt--;
<a name="l00116"></a>00116 }
<a name="l00117"></a>00117
<a name="l00118"></a>00118 }
<a name="l00119"></a>00119
</pre></div></div>
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<h1>arm_abs_q15.c File Reference</h1> </div>
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
<p><a href="arm__abs__q15_8c_source.html">Go to the source code of this file.</a></p>
<table class="memberdecls">
<tr><td colspan="2"><h2><a name="func-members"></a>
Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___basic_abs.html#ga39f92964c9b649ba252e26ebe7b95594">arm_abs_q15</a> (<a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> *pSrc, <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> *pDst, uint32_t <a class="el" href="arm__variance__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)</td></tr>
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<h1>arm_abs_q15.c</h1> </div>
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<div class="contents">
<a href="arm__abs__q15_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ---------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_abs_q15.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: Q15 vector absolute value. </span>
<a name="l00011"></a>00011 <span class="comment">* </span>
<a name="l00012"></a>00012 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0</span>
<a name="l00013"></a>00013 <span class="comment">* </span>
<a name="l00014"></a>00014 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00015"></a>00015 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00016"></a>00016 <span class="comment">* </span>
<a name="l00017"></a>00017 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00018"></a>00018 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00019"></a>00019 <span class="comment">* </span>
<a name="l00020"></a>00020 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00021"></a>00021 <span class="comment">* Documentation updated. </span>
<a name="l00022"></a>00022 <span class="comment">* </span>
<a name="l00023"></a>00023 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00024"></a>00024 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00025"></a>00025 <span class="comment">* </span>
<a name="l00026"></a>00026 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00027"></a>00027 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00028"></a>00028 <span class="comment">* </span>
<a name="l00029"></a>00029 <span class="comment">* Version 0.0.7 2010/06/10 </span>
<a name="l00030"></a>00030 <span class="comment">* Misra-C changes done </span>
<a name="l00031"></a>00031 <span class="comment">* -------------------------------------------------------------------- */</span>
<a name="l00032"></a>00032
<a name="l00033"></a>00033 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00034"></a>00034
<a name="l00057"></a><a class="code" href="group___basic_abs.html#ga39f92964c9b649ba252e26ebe7b95594">00057</a> <span class="keywordtype">void</span> <a class="code" href="group___basic_abs.html#ga39f92964c9b649ba252e26ebe7b95594" title="Q15 vector absolute value.">arm_abs_q15</a>(
<a name="l00058"></a>00058 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> * pSrc,
<a name="l00059"></a>00059 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> * pDst,
<a name="l00060"></a>00060 uint32_t <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)
<a name="l00061"></a>00061 {
<a name="l00062"></a>00062 uint32_t blkCnt; <span class="comment">/* loop counter */</span>
<a name="l00063"></a>00063
<a name="l00064"></a>00064 <span class="preprocessor">#ifndef ARM_MATH_CM0</span>
<a name="l00065"></a>00065 <span class="preprocessor"></span>
<a name="l00066"></a>00066 <span class="comment">/* Run the below code for Cortex-M4 and Cortex-M3 */</span>
<a name="l00067"></a>00067
<a name="l00068"></a>00068 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> in1; <span class="comment">/* Input value1 */</span>
<a name="l00069"></a>00069 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> in2; <span class="comment">/* Input value2 */</span>
<a name="l00070"></a>00070
<a name="l00071"></a>00071
<a name="l00072"></a>00072 <span class="comment">/*loop Unrolling */</span>
<a name="l00073"></a>00073 blkCnt = blockSize &gt;&gt; 2u;
<a name="l00074"></a>00074
<a name="l00075"></a>00075 <span class="comment">/* First part of the processing with loop unrolling. Compute 4 outputs at a time. </span>
<a name="l00076"></a>00076 <span class="comment"> ** a second loop below computes the remaining 1 to 3 samples. */</span>
<a name="l00077"></a>00077 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00078"></a>00078 {
<a name="l00079"></a>00079 <span class="comment">/* C = |A| */</span>
<a name="l00080"></a>00080 <span class="comment">/* Read two inputs */</span>
<a name="l00081"></a>00081 in1 = *pSrc++;
<a name="l00082"></a>00082 in2 = *pSrc++;
<a name="l00083"></a>00083
<a name="l00084"></a>00084
<a name="l00085"></a>00085 <span class="comment">/* Store the Absolute result in the destination buffer by packing the two values, in a single cycle */</span>
<a name="l00086"></a>00086
<a name="l00087"></a>00087 <span class="preprocessor">#ifndef ARM_MATH_BIG_ENDIAN</span>
<a name="l00088"></a>00088 <span class="preprocessor"></span>
<a name="l00089"></a>00089 *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pDst)++ =
<a name="l00090"></a>00090 __PKHBT(((in1 &gt; 0) ? in1 : __SSAT(-in1, 16)),
<a name="l00091"></a>00091 ((in2 &gt; 0) ? in2 : __SSAT(-in2, 16)), 16);
<a name="l00092"></a>00092
<a name="l00093"></a>00093 <span class="preprocessor">#else</span>
<a name="l00094"></a>00094 <span class="preprocessor"></span>
<a name="l00095"></a>00095
<a name="l00096"></a>00096 *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pDst)++ =
<a name="l00097"></a>00097 __PKHBT(((in2 &gt; 0) ? in2 : __SSAT(-in2, 16)),
<a name="l00098"></a>00098 ((in1 &gt; 0) ? in1 : __SSAT(-in1, 16)), 16);
<a name="l00099"></a>00099
<a name="l00100"></a>00100 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_BIG_ENDIAN */</span>
<a name="l00101"></a>00101
<a name="l00102"></a>00102 in1 = *pSrc++;
<a name="l00103"></a>00103 in2 = *pSrc++;
<a name="l00104"></a>00104
<a name="l00105"></a>00105
<a name="l00106"></a>00106 <span class="preprocessor">#ifndef ARM_MATH_BIG_ENDIAN</span>
<a name="l00107"></a>00107 <span class="preprocessor"></span>
<a name="l00108"></a>00108 *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pDst)++ =
<a name="l00109"></a>00109 __PKHBT(((in1 &gt; 0) ? in1 : __SSAT(-in1, 16)),
<a name="l00110"></a>00110 ((in2 &gt; 0) ? in2 : __SSAT(-in2, 16)), 16);
<a name="l00111"></a>00111
<a name="l00112"></a>00112
<a name="l00113"></a>00113 <span class="preprocessor">#else</span>
<a name="l00114"></a>00114 <span class="preprocessor"></span>
<a name="l00115"></a>00115 *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pDst)++ =
<a name="l00116"></a>00116 __PKHBT(((in2 &gt; 0) ? in2 : __SSAT(-in2, 16)),
<a name="l00117"></a>00117 ((in1 &gt; 0) ? in1 : __SSAT(-in1, 16)), 16);
<a name="l00118"></a>00118
<a name="l00119"></a>00119 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_BIG_ENDIAN */</span>
<a name="l00120"></a>00120
<a name="l00121"></a>00121 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00122"></a>00122 blkCnt--;
<a name="l00123"></a>00123 }
<a name="l00124"></a>00124
<a name="l00125"></a>00125 <span class="comment">/* If the blockSize is not a multiple of 4, compute any remaining output samples here. </span>
<a name="l00126"></a>00126 <span class="comment"> ** No loop unrolling is used. */</span>
<a name="l00127"></a>00127 blkCnt = blockSize % 0x4u;
<a name="l00128"></a>00128
<a name="l00129"></a>00129 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00130"></a>00130 {
<a name="l00131"></a>00131 <span class="comment">/* C = |A| */</span>
<a name="l00132"></a>00132 <span class="comment">/* Read the input */</span>
<a name="l00133"></a>00133 in1 = *pSrc++;
<a name="l00134"></a>00134
<a name="l00135"></a>00135 <span class="comment">/* Calculate absolute value of input and then store the result in the destination buffer. */</span>
<a name="l00136"></a>00136 *pDst++ = (in1 &gt; 0) ? in1 : __SSAT(-in1, 16);
<a name="l00137"></a>00137
<a name="l00138"></a>00138 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00139"></a>00139 blkCnt--;
<a name="l00140"></a>00140 }
<a name="l00141"></a>00141
<a name="l00142"></a>00142 <span class="preprocessor">#else</span>
<a name="l00143"></a>00143 <span class="preprocessor"></span>
<a name="l00144"></a>00144 <span class="comment">/* Run the below code for Cortex-M0 */</span>
<a name="l00145"></a>00145
<a name="l00146"></a>00146 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> in; <span class="comment">/* Temporary input variable */</span>
<a name="l00147"></a>00147
<a name="l00148"></a>00148 <span class="comment">/* Initialize blkCnt with number of samples */</span>
<a name="l00149"></a>00149 blkCnt = <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>;
<a name="l00150"></a>00150
<a name="l00151"></a>00151 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00152"></a>00152 {
<a name="l00153"></a>00153 <span class="comment">/* C = |A| */</span>
<a name="l00154"></a>00154 <span class="comment">/* Read the input */</span>
<a name="l00155"></a>00155 in = *pSrc++;
<a name="l00156"></a>00156
<a name="l00157"></a>00157 <span class="comment">/* Calculate absolute value of input and then store the result in the destination buffer. */</span>
<a name="l00158"></a>00158 *pDst++ = (in &gt; 0) ? in : __SSAT(-in, 16);
<a name="l00159"></a>00159
<a name="l00160"></a>00160 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00161"></a>00161 blkCnt--;
<a name="l00162"></a>00162 }
<a name="l00163"></a>00163
<a name="l00164"></a>00164 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_CM0 */</span>
<a name="l00165"></a>00165
<a name="l00166"></a>00166 }
<a name="l00167"></a>00167
</pre></div></div>
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<h1>arm_abs_q31.c File Reference</h1> </div>
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
<p><a href="arm__abs__q31_8c_source.html">Go to the source code of this file.</a></p>
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<tr><td colspan="2"><h2><a name="func-members"></a>
Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___basic_abs.html#ga59eafcdcdb52da60d37f20aec6ff4577">arm_abs_q31</a> (<a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> *pSrc, <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> *pDst, uint32_t <a class="el" href="arm__variance__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)</td></tr>
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<h1>arm_abs_q31.c</h1> </div>
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<a href="arm__abs__q31_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ---------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_abs_q31.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: Q31 vector absolute value. </span>
<a name="l00011"></a>00011 <span class="comment">* </span>
<a name="l00012"></a>00012 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0</span>
<a name="l00013"></a>00013 <span class="comment">* </span>
<a name="l00014"></a>00014 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00015"></a>00015 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00016"></a>00016 <span class="comment">* </span>
<a name="l00017"></a>00017 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00018"></a>00018 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00019"></a>00019 <span class="comment">* </span>
<a name="l00020"></a>00020 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00021"></a>00021 <span class="comment">* Documentation updated. </span>
<a name="l00022"></a>00022 <span class="comment">* </span>
<a name="l00023"></a>00023 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00024"></a>00024 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00025"></a>00025 <span class="comment">* </span>
<a name="l00026"></a>00026 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00027"></a>00027 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00028"></a>00028 <span class="comment">* </span>
<a name="l00029"></a>00029 <span class="comment">* Version 0.0.7 2010/06/10 </span>
<a name="l00030"></a>00030 <span class="comment">* Misra-C changes done </span>
<a name="l00031"></a>00031 <span class="comment">* -------------------------------------------------------------------- */</span>
<a name="l00032"></a>00032
<a name="l00033"></a>00033 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00034"></a>00034
<a name="l00058"></a><a class="code" href="group___basic_abs.html#ga59eafcdcdb52da60d37f20aec6ff4577">00058</a> <span class="keywordtype">void</span> <a class="code" href="group___basic_abs.html#ga59eafcdcdb52da60d37f20aec6ff4577" title="Q31 vector absolute value.">arm_abs_q31</a>(
<a name="l00059"></a>00059 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> * pSrc,
<a name="l00060"></a>00060 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> * pDst,
<a name="l00061"></a>00061 uint32_t <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)
<a name="l00062"></a>00062 {
<a name="l00063"></a>00063 uint32_t blkCnt; <span class="comment">/* loop counter */</span>
<a name="l00064"></a>00064 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> in; <span class="comment">/* Input value */</span>
<a name="l00065"></a>00065
<a name="l00066"></a>00066 <span class="preprocessor">#ifndef ARM_MATH_CM0</span>
<a name="l00067"></a>00067 <span class="preprocessor"></span>
<a name="l00068"></a>00068 <span class="comment">/* Run the below code for Cortex-M4 and Cortex-M3 */</span>
<a name="l00069"></a>00069
<a name="l00070"></a>00070 <span class="comment">/*loop Unrolling */</span>
<a name="l00071"></a>00071 blkCnt = blockSize &gt;&gt; 2u;
<a name="l00072"></a>00072
<a name="l00073"></a>00073 <span class="comment">/* First part of the processing with loop unrolling. Compute 4 outputs at a time. </span>
<a name="l00074"></a>00074 <span class="comment"> ** a second loop below computes the remaining 1 to 3 samples. */</span>
<a name="l00075"></a>00075 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00076"></a>00076 {
<a name="l00077"></a>00077 <span class="comment">/* C = |A| */</span>
<a name="l00078"></a>00078 <span class="comment">/* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */</span>
<a name="l00079"></a>00079 in = *pSrc++;
<a name="l00080"></a>00080 *pDst++ = (in &gt; 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in);
<a name="l00081"></a>00081 in = *pSrc++;
<a name="l00082"></a>00082 *pDst++ = (in &gt; 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in);
<a name="l00083"></a>00083 in = *pSrc++;
<a name="l00084"></a>00084 *pDst++ = (in &gt; 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in);
<a name="l00085"></a>00085 in = *pSrc++;
<a name="l00086"></a>00086 *pDst++ = (in &gt; 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in);
<a name="l00087"></a>00087
<a name="l00088"></a>00088 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00089"></a>00089 blkCnt--;
<a name="l00090"></a>00090 }
<a name="l00091"></a>00091
<a name="l00092"></a>00092 <span class="comment">/* If the blockSize is not a multiple of 4, compute any remaining output samples here. </span>
<a name="l00093"></a>00093 <span class="comment"> ** No loop unrolling is used. */</span>
<a name="l00094"></a>00094 blkCnt = blockSize % 0x4u;
<a name="l00095"></a>00095
<a name="l00096"></a>00096 <span class="preprocessor">#else</span>
<a name="l00097"></a>00097 <span class="preprocessor"></span>
<a name="l00098"></a>00098 <span class="comment">/* Run the below code for Cortex-M0 */</span>
<a name="l00099"></a>00099
<a name="l00100"></a>00100 <span class="comment">/* Initialize blkCnt with number of samples */</span>
<a name="l00101"></a>00101 blkCnt = <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>;
<a name="l00102"></a>00102
<a name="l00103"></a>00103 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_CM0 */</span>
<a name="l00104"></a>00104
<a name="l00105"></a>00105 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00106"></a>00106 {
<a name="l00107"></a>00107 <span class="comment">/* C = |A| */</span>
<a name="l00108"></a>00108 <span class="comment">/* Calculate absolute value of the input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */</span>
<a name="l00109"></a>00109 in = *pSrc++;
<a name="l00110"></a>00110 *pDst++ = (in &gt; 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in);
<a name="l00111"></a>00111
<a name="l00112"></a>00112 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00113"></a>00113 blkCnt--;
<a name="l00114"></a>00114 }
<a name="l00115"></a>00115
<a name="l00116"></a>00116 }
<a name="l00117"></a>00117
</pre></div></div>
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<h1>arm_abs_q7.c File Reference</h1> </div>
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
<p><a href="arm__abs__q7_8c_source.html">Go to the source code of this file.</a></p>
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Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___basic_abs.html#gadc30985e33fbf96802a5a7954dece3b1">arm_abs_q7</a> (<a class="el" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263">q7_t</a> *pSrc, <a class="el" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263">q7_t</a> *pDst, uint32_t <a class="el" href="arm__variance__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)</td></tr>
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<h1>arm_abs_q7.c</h1> </div>
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<a href="arm__abs__q7_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ---------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_abs_q7.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: Q7 vector absolute value. </span>
<a name="l00011"></a>00011 <span class="comment">* </span>
<a name="l00012"></a>00012 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0</span>
<a name="l00013"></a>00013 <span class="comment">* </span>
<a name="l00014"></a>00014 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00015"></a>00015 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00016"></a>00016 <span class="comment">* </span>
<a name="l00017"></a>00017 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00018"></a>00018 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00019"></a>00019 <span class="comment">* </span>
<a name="l00020"></a>00020 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00021"></a>00021 <span class="comment">* Documentation updated. </span>
<a name="l00022"></a>00022 <span class="comment">* </span>
<a name="l00023"></a>00023 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00024"></a>00024 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00025"></a>00025 <span class="comment">* </span>
<a name="l00026"></a>00026 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00027"></a>00027 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00028"></a>00028 <span class="comment">* </span>
<a name="l00029"></a>00029 <span class="comment">* Version 0.0.7 2010/06/10 </span>
<a name="l00030"></a>00030 <span class="comment">* Misra-C changes done </span>
<a name="l00031"></a>00031 <span class="comment">* -------------------------------------------------------------------- */</span>
<a name="l00032"></a>00032
<a name="l00033"></a>00033 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00034"></a>00034
<a name="l00057"></a><a class="code" href="group___basic_abs.html#gadc30985e33fbf96802a5a7954dece3b1">00057</a> <span class="keywordtype">void</span> <a class="code" href="group___basic_abs.html#gadc30985e33fbf96802a5a7954dece3b1" title="Q7 vector absolute value.">arm_abs_q7</a>(
<a name="l00058"></a>00058 <a class="code" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263" title="8-bit fractional data type in 1.7 format.">q7_t</a> * pSrc,
<a name="l00059"></a>00059 <a class="code" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263" title="8-bit fractional data type in 1.7 format.">q7_t</a> * pDst,
<a name="l00060"></a>00060 uint32_t <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)
<a name="l00061"></a>00061 {
<a name="l00062"></a>00062 uint32_t blkCnt; <span class="comment">/* loop counter */</span>
<a name="l00063"></a>00063
<a name="l00064"></a>00064 <span class="preprocessor">#ifndef ARM_MATH_CM0</span>
<a name="l00065"></a>00065 <span class="preprocessor"></span>
<a name="l00066"></a>00066 <span class="comment">/* Run the below code for Cortex-M4 and Cortex-M3 */</span>
<a name="l00067"></a>00067 <a class="code" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263" title="8-bit fractional data type in 1.7 format.">q7_t</a> in1; <span class="comment">/* Input value1 */</span>
<a name="l00068"></a>00068 <a class="code" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263" title="8-bit fractional data type in 1.7 format.">q7_t</a> in2; <span class="comment">/* Input value2 */</span>
<a name="l00069"></a>00069 <a class="code" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263" title="8-bit fractional data type in 1.7 format.">q7_t</a> in3; <span class="comment">/* Input value3 */</span>
<a name="l00070"></a>00070 <a class="code" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263" title="8-bit fractional data type in 1.7 format.">q7_t</a> in4; <span class="comment">/* Input value4 */</span>
<a name="l00071"></a>00071
<a name="l00072"></a>00072
<a name="l00073"></a>00073 <span class="comment">/*loop Unrolling */</span>
<a name="l00074"></a>00074 blkCnt = blockSize &gt;&gt; 2u;
<a name="l00075"></a>00075
<a name="l00076"></a>00076 <span class="comment">/* First part of the processing with loop unrolling. Compute 4 outputs at a time. </span>
<a name="l00077"></a>00077 <span class="comment"> ** a second loop below computes the remaining 1 to 3 samples. */</span>
<a name="l00078"></a>00078 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00079"></a>00079 {
<a name="l00080"></a>00080 <span class="comment">/* C = |A| */</span>
<a name="l00081"></a>00081 <span class="comment">/* Read 4 inputs */</span>
<a name="l00082"></a>00082 in1 = *pSrc++;
<a name="l00083"></a>00083 in2 = *pSrc++;
<a name="l00084"></a>00084 in3 = *pSrc++;
<a name="l00085"></a>00085 in4 = *pSrc++;
<a name="l00086"></a>00086
<a name="l00087"></a>00087 <span class="comment">/* Store the Absolute result in the destination buffer by packing the 4 values in single cycle */</span>
<a name="l00088"></a>00088 *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pDst)++ =
<a name="l00089"></a>00089 <a class="code" href="arm__math_8h.html#a3ebff224ad44c217fde9f530342e2960" title="definition to pack four 8 bit values.">__PACKq7</a>(((in1 &gt; 0) ? in1 : __SSAT(-in1, 8)),
<a name="l00090"></a>00090 ((in2 &gt; 0) ? in2 : __SSAT(-in2, 8)),
<a name="l00091"></a>00091 ((in3 &gt; 0) ? in3 : __SSAT(-in3, 8)),
<a name="l00092"></a>00092 ((in4 &gt; 0) ? in4 : __SSAT(-in4, 8)));
<a name="l00093"></a>00093
<a name="l00094"></a>00094 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00095"></a>00095 blkCnt--;
<a name="l00096"></a>00096 }
<a name="l00097"></a>00097
<a name="l00098"></a>00098 <span class="comment">/* If the blockSize is not a multiple of 4, compute any remaining output samples here. </span>
<a name="l00099"></a>00099 <span class="comment"> ** No loop unrolling is used. */</span>
<a name="l00100"></a>00100 blkCnt = blockSize % 0x4u;
<a name="l00101"></a>00101
<a name="l00102"></a>00102 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00103"></a>00103 {
<a name="l00104"></a>00104 <span class="comment">/* C = |A| */</span>
<a name="l00105"></a>00105 <span class="comment">/* Read the input */</span>
<a name="l00106"></a>00106 in1 = *pSrc++;
<a name="l00107"></a>00107
<a name="l00108"></a>00108 <span class="comment">/* Store the Absolute result in the destination buffer */</span>
<a name="l00109"></a>00109 *pDst++ = (in1 &gt; 0) ? in1 : __SSAT(-in1, 8);
<a name="l00110"></a>00110
<a name="l00111"></a>00111 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00112"></a>00112 blkCnt--;
<a name="l00113"></a>00113 }
<a name="l00114"></a>00114
<a name="l00115"></a>00115 <span class="preprocessor">#else</span>
<a name="l00116"></a>00116 <span class="preprocessor"></span>
<a name="l00117"></a>00117 <span class="comment">/* Run the below code for Cortex-M0 */</span>
<a name="l00118"></a>00118
<a name="l00119"></a>00119 <a class="code" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263" title="8-bit fractional data type in 1.7 format.">q7_t</a> in; <span class="comment">/* Temporary input varible */</span>
<a name="l00120"></a>00120
<a name="l00121"></a>00121 <span class="comment">/* Initialize blkCnt with number of samples */</span>
<a name="l00122"></a>00122 blkCnt = <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>;
<a name="l00123"></a>00123
<a name="l00124"></a>00124 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00125"></a>00125 {
<a name="l00126"></a>00126 <span class="comment">/* C = |A| */</span>
<a name="l00127"></a>00127 <span class="comment">/* Read the input */</span>
<a name="l00128"></a>00128 in = *pSrc++;
<a name="l00129"></a>00129
<a name="l00130"></a>00130 <span class="comment">/* Store the Absolute result in the destination buffer */</span>
<a name="l00131"></a>00131 *pDst++ = (in &gt; 0) ? in : __SSAT(-in, 8);
<a name="l00132"></a>00132
<a name="l00133"></a>00133 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00134"></a>00134 blkCnt--;
<a name="l00135"></a>00135 }
<a name="l00136"></a>00136
<a name="l00137"></a>00137 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_CM0 */</span>
<a name="l00138"></a>00138
<a name="l00139"></a>00139 }
<a name="l00140"></a>00140
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<h1>arm_add_f32.c File Reference</h1> </div>
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
<p><a href="arm__add__f32_8c_source.html">Go to the source code of this file.</a></p>
<table class="memberdecls">
<tr><td colspan="2"><h2><a name="func-members"></a>
Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___basic_add.html#ga6a904a547413b10565dd1d251c6bafbd">arm_add_f32</a> (<a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> *pSrcA, <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> *pSrcB, <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> *pDst, uint32_t <a class="el" href="arm__variance__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)</td></tr>
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<a href="arm__add__f32_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ---------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_add_f32.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: Floating-point vector addition. </span>
<a name="l00011"></a>00011 <span class="comment">* </span>
<a name="l00012"></a>00012 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0</span>
<a name="l00013"></a>00013 <span class="comment">* </span>
<a name="l00014"></a>00014 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00015"></a>00015 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00016"></a>00016 <span class="comment">* </span>
<a name="l00017"></a>00017 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00018"></a>00018 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00019"></a>00019 <span class="comment">* </span>
<a name="l00020"></a>00020 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00021"></a>00021 <span class="comment">* Documentation updated. </span>
<a name="l00022"></a>00022 <span class="comment">* </span>
<a name="l00023"></a>00023 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00024"></a>00024 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00025"></a>00025 <span class="comment">* </span>
<a name="l00026"></a>00026 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00027"></a>00027 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00028"></a>00028 <span class="comment">* </span>
<a name="l00029"></a>00029 <span class="comment">* Version 0.0.7 2010/06/10 </span>
<a name="l00030"></a>00030 <span class="comment">* Misra-C changes done </span>
<a name="l00031"></a>00031 <span class="comment">* ---------------------------------------------------------------------------- */</span>
<a name="l00032"></a>00032
<a name="l00033"></a>00033 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00034"></a>00034
<a name="l00065"></a><a class="code" href="group___basic_add.html#ga6a904a547413b10565dd1d251c6bafbd">00065</a> <span class="keywordtype">void</span> <a class="code" href="group___basic_add.html#ga6a904a547413b10565dd1d251c6bafbd" title="Floating-point vector addition.">arm_add_f32</a>(
<a name="l00066"></a>00066 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> * pSrcA,
<a name="l00067"></a>00067 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> * pSrcB,
<a name="l00068"></a>00068 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> * pDst,
<a name="l00069"></a>00069 uint32_t <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)
<a name="l00070"></a>00070 {
<a name="l00071"></a>00071 uint32_t blkCnt; <span class="comment">/* loop counter */</span>
<a name="l00072"></a>00072
<a name="l00073"></a>00073 <span class="preprocessor">#ifndef ARM_MATH_CM0</span>
<a name="l00074"></a>00074 <span class="preprocessor"></span>
<a name="l00075"></a>00075 <span class="comment">/* Run the below code for Cortex-M4 and Cortex-M3 */</span>
<a name="l00076"></a>00076
<a name="l00077"></a>00077 <span class="comment">/*loop Unrolling */</span>
<a name="l00078"></a>00078 blkCnt = blockSize &gt;&gt; 2u;
<a name="l00079"></a>00079
<a name="l00080"></a>00080 <span class="comment">/* First part of the processing with loop unrolling. Compute 4 outputs at a time. </span>
<a name="l00081"></a>00081 <span class="comment"> ** a second loop below computes the remaining 1 to 3 samples. */</span>
<a name="l00082"></a>00082 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00083"></a>00083 {
<a name="l00084"></a>00084 <span class="comment">/* C = A + B */</span>
<a name="l00085"></a>00085 <span class="comment">/* Add and then store the results in the destination buffer. */</span>
<a name="l00086"></a>00086 *pDst++ = (*pSrcA++) + (*pSrcB++);
<a name="l00087"></a>00087 *pDst++ = (*pSrcA++) + (*pSrcB++);
<a name="l00088"></a>00088 *pDst++ = (*pSrcA++) + (*pSrcB++);
<a name="l00089"></a>00089 *pDst++ = (*pSrcA++) + (*pSrcB++);
<a name="l00090"></a>00090
<a name="l00091"></a>00091 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00092"></a>00092 blkCnt--;
<a name="l00093"></a>00093 }
<a name="l00094"></a>00094
<a name="l00095"></a>00095 <span class="comment">/* If the blockSize is not a multiple of 4, compute any remaining output samples here. </span>
<a name="l00096"></a>00096 <span class="comment"> ** No loop unrolling is used. */</span>
<a name="l00097"></a>00097 blkCnt = blockSize % 0x4u;
<a name="l00098"></a>00098
<a name="l00099"></a>00099 <span class="preprocessor">#else</span>
<a name="l00100"></a>00100 <span class="preprocessor"></span>
<a name="l00101"></a>00101 <span class="comment">/* Run the below code for Cortex-M0 */</span>
<a name="l00102"></a>00102
<a name="l00103"></a>00103 <span class="comment">/* Initialize blkCnt with number of samples */</span>
<a name="l00104"></a>00104 blkCnt = <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>;
<a name="l00105"></a>00105
<a name="l00106"></a>00106 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_CM0 */</span>
<a name="l00107"></a>00107
<a name="l00108"></a>00108 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00109"></a>00109 {
<a name="l00110"></a>00110 <span class="comment">/* C = A + B */</span>
<a name="l00111"></a>00111 <span class="comment">/* Add and then store the results in the destination buffer. */</span>
<a name="l00112"></a>00112 *pDst++ = (*pSrcA++) + (*pSrcB++);
<a name="l00113"></a>00113
<a name="l00114"></a>00114 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00115"></a>00115 blkCnt--;
<a name="l00116"></a>00116 }
<a name="l00117"></a>00117 }
<a name="l00118"></a>00118
</pre></div></div>
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
<p><a href="arm__add__q15_8c_source.html">Go to the source code of this file.</a></p>
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Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___basic_add.html#gabb51285a41f511670bbff62fc0e1bf62">arm_add_q15</a> (<a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> *pSrcA, <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> *pSrcB, <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> *pDst, uint32_t <a class="el" href="arm__variance__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)</td></tr>
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<h1>arm_add_q15.c</h1> </div>
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<a href="arm__add__q15_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ---------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_add_q15.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: Q15 vector addition </span>
<a name="l00011"></a>00011 <span class="comment">* </span>
<a name="l00012"></a>00012 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0</span>
<a name="l00013"></a>00013 <span class="comment">* </span>
<a name="l00014"></a>00014 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00015"></a>00015 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00016"></a>00016 <span class="comment">* </span>
<a name="l00017"></a>00017 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00018"></a>00018 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00019"></a>00019 <span class="comment">* </span>
<a name="l00020"></a>00020 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00021"></a>00021 <span class="comment">* Documentation updated. </span>
<a name="l00022"></a>00022 <span class="comment">* </span>
<a name="l00023"></a>00023 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00024"></a>00024 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00025"></a>00025 <span class="comment">* </span>
<a name="l00026"></a>00026 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00027"></a>00027 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00028"></a>00028 <span class="comment">* </span>
<a name="l00029"></a>00029 <span class="comment">* Version 0.0.7 2010/06/10 </span>
<a name="l00030"></a>00030 <span class="comment">* Misra-C changes done </span>
<a name="l00031"></a>00031 <span class="comment">* -------------------------------------------------------------------- */</span>
<a name="l00032"></a>00032
<a name="l00033"></a>00033 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00034"></a>00034
<a name="l00058"></a><a class="code" href="group___basic_add.html#gabb51285a41f511670bbff62fc0e1bf62">00058</a> <span class="keywordtype">void</span> <a class="code" href="group___basic_add.html#gabb51285a41f511670bbff62fc0e1bf62" title="Q15 vector addition.">arm_add_q15</a>(
<a name="l00059"></a>00059 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> * pSrcA,
<a name="l00060"></a>00060 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> * pSrcB,
<a name="l00061"></a>00061 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> * pDst,
<a name="l00062"></a>00062 uint32_t <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)
<a name="l00063"></a>00063 {
<a name="l00064"></a>00064 uint32_t blkCnt; <span class="comment">/* loop counter */</span>
<a name="l00065"></a>00065
<a name="l00066"></a>00066 <span class="preprocessor">#ifndef ARM_MATH_CM0</span>
<a name="l00067"></a>00067 <span class="preprocessor"></span>
<a name="l00068"></a>00068 <span class="comment">/* Run the below code for Cortex-M4 and Cortex-M3 */</span>
<a name="l00069"></a>00069
<a name="l00070"></a>00070
<a name="l00071"></a>00071 <span class="comment">/*loop Unrolling */</span>
<a name="l00072"></a>00072 blkCnt = blockSize &gt;&gt; 2u;
<a name="l00073"></a>00073
<a name="l00074"></a>00074 <span class="comment">/* First part of the processing with loop unrolling. Compute 4 outputs at a time. </span>
<a name="l00075"></a>00075 <span class="comment"> ** a second loop below computes the remaining 1 to 3 samples. */</span>
<a name="l00076"></a>00076 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00077"></a>00077 {
<a name="l00078"></a>00078 <span class="comment">/* C = A + B */</span>
<a name="l00079"></a>00079 <span class="comment">/* Add and then store the results in the destination buffer. */</span>
<a name="l00080"></a>00080 *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pDst)++ = __QADD16(*<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pSrcA)++, *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pSrcB)++);
<a name="l00081"></a>00081 *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pDst)++ = __QADD16(*<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pSrcA)++, *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pSrcB)++);
<a name="l00082"></a>00082
<a name="l00083"></a>00083 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00084"></a>00084 blkCnt--;
<a name="l00085"></a>00085 }
<a name="l00086"></a>00086
<a name="l00087"></a>00087 <span class="comment">/* If the blockSize is not a multiple of 4, compute any remaining output samples here. </span>
<a name="l00088"></a>00088 <span class="comment"> ** No loop unrolling is used. */</span>
<a name="l00089"></a>00089 blkCnt = blockSize % 0x4u;
<a name="l00090"></a>00090
<a name="l00091"></a>00091 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00092"></a>00092 {
<a name="l00093"></a>00093 <span class="comment">/* C = A + B */</span>
<a name="l00094"></a>00094 <span class="comment">/* Add and then store the results in the destination buffer. */</span>
<a name="l00095"></a>00095 *pDst++ = (<a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a>) __QADD16(*pSrcA++, *pSrcB++);
<a name="l00096"></a>00096
<a name="l00097"></a>00097 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00098"></a>00098 blkCnt--;
<a name="l00099"></a>00099 }
<a name="l00100"></a>00100
<a name="l00101"></a>00101 <span class="preprocessor">#else</span>
<a name="l00102"></a>00102 <span class="preprocessor"></span>
<a name="l00103"></a>00103 <span class="comment">/* Run the below code for Cortex-M0 */</span>
<a name="l00104"></a>00104
<a name="l00105"></a>00105
<a name="l00106"></a>00106
<a name="l00107"></a>00107 <span class="comment">/* Initialize blkCnt with number of samples */</span>
<a name="l00108"></a>00108 blkCnt = <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>;
<a name="l00109"></a>00109
<a name="l00110"></a>00110 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00111"></a>00111 {
<a name="l00112"></a>00112 <span class="comment">/* C = A + B */</span>
<a name="l00113"></a>00113 <span class="comment">/* Add and then store the results in the destination buffer. */</span>
<a name="l00114"></a>00114 *pDst++ = (<a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a>) __SSAT(((<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) * pSrcA++ + *pSrcB++), 16);
<a name="l00115"></a>00115
<a name="l00116"></a>00116 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00117"></a>00117 blkCnt--;
<a name="l00118"></a>00118 }
<a name="l00119"></a>00119
<a name="l00120"></a>00120 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_CM0 */</span>
<a name="l00121"></a>00121
<a name="l00122"></a>00122
<a name="l00123"></a>00123 }
<a name="l00124"></a>00124
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
<p><a href="arm__add__q31_8c_source.html">Go to the source code of this file.</a></p>
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Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___basic_add.html#ga24d6c3f7f8b9fae4847c0c3f26a39a3b">arm_add_q31</a> (<a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> *pSrcA, <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> *pSrcB, <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> *pDst, uint32_t <a class="el" href="arm__variance__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)</td></tr>
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<h1>arm_add_q31.c</h1> </div>
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<a href="arm__add__q31_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ---------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_add_q31.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: Q31 vector addition. </span>
<a name="l00011"></a>00011 <span class="comment">* </span>
<a name="l00012"></a>00012 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0</span>
<a name="l00013"></a>00013 <span class="comment">* </span>
<a name="l00014"></a>00014 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00015"></a>00015 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00016"></a>00016 <span class="comment">* </span>
<a name="l00017"></a>00017 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00018"></a>00018 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00019"></a>00019 <span class="comment">* </span>
<a name="l00020"></a>00020 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00021"></a>00021 <span class="comment">* Documentation updated. </span>
<a name="l00022"></a>00022 <span class="comment">* </span>
<a name="l00023"></a>00023 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00024"></a>00024 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00025"></a>00025 <span class="comment">* </span>
<a name="l00026"></a>00026 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00027"></a>00027 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00028"></a>00028 <span class="comment">* </span>
<a name="l00029"></a>00029 <span class="comment">* Version 0.0.7 2010/06/10 </span>
<a name="l00030"></a>00030 <span class="comment">* Misra-C changes done </span>
<a name="l00031"></a>00031 <span class="comment">* -------------------------------------------------------------------- */</span>
<a name="l00032"></a>00032
<a name="l00033"></a>00033 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00034"></a>00034
<a name="l00059"></a><a class="code" href="group___basic_add.html#ga24d6c3f7f8b9fae4847c0c3f26a39a3b">00059</a> <span class="keywordtype">void</span> <a class="code" href="group___basic_add.html#ga24d6c3f7f8b9fae4847c0c3f26a39a3b" title="Q31 vector addition.">arm_add_q31</a>(
<a name="l00060"></a>00060 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> * pSrcA,
<a name="l00061"></a>00061 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> * pSrcB,
<a name="l00062"></a>00062 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> * pDst,
<a name="l00063"></a>00063 uint32_t <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)
<a name="l00064"></a>00064 {
<a name="l00065"></a>00065 uint32_t blkCnt; <span class="comment">/* loop counter */</span>
<a name="l00066"></a>00066
<a name="l00067"></a>00067 <span class="preprocessor">#ifndef ARM_MATH_CM0</span>
<a name="l00068"></a>00068 <span class="preprocessor"></span>
<a name="l00069"></a>00069 <span class="comment">/* Run the below code for Cortex-M4 and Cortex-M3 */</span>
<a name="l00070"></a>00070
<a name="l00071"></a>00071
<a name="l00072"></a>00072 <span class="comment">/*loop Unrolling */</span>
<a name="l00073"></a>00073 blkCnt = blockSize &gt;&gt; 2u;
<a name="l00074"></a>00074
<a name="l00075"></a>00075 <span class="comment">/* First part of the processing with loop unrolling. Compute 4 outputs at a time. </span>
<a name="l00076"></a>00076 <span class="comment"> ** a second loop below computes the remaining 1 to 3 samples. */</span>
<a name="l00077"></a>00077 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00078"></a>00078 {
<a name="l00079"></a>00079 <span class="comment">/* C = A + B */</span>
<a name="l00080"></a>00080 <span class="comment">/* Add and then store the results in the destination buffer. */</span>
<a name="l00081"></a>00081 *pDst++ = __QADD(*pSrcA++, *pSrcB++);
<a name="l00082"></a>00082 *pDst++ = __QADD(*pSrcA++, *pSrcB++);
<a name="l00083"></a>00083 *pDst++ = __QADD(*pSrcA++, *pSrcB++);
<a name="l00084"></a>00084 *pDst++ = __QADD(*pSrcA++, *pSrcB++);
<a name="l00085"></a>00085
<a name="l00086"></a>00086 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00087"></a>00087 blkCnt--;
<a name="l00088"></a>00088 }
<a name="l00089"></a>00089
<a name="l00090"></a>00090 <span class="comment">/* If the blockSize is not a multiple of 4, compute any remaining output samples here. </span>
<a name="l00091"></a>00091 <span class="comment"> ** No loop unrolling is used. */</span>
<a name="l00092"></a>00092 blkCnt = blockSize % 0x4u;
<a name="l00093"></a>00093
<a name="l00094"></a>00094 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00095"></a>00095 {
<a name="l00096"></a>00096 <span class="comment">/* C = A + B */</span>
<a name="l00097"></a>00097 <span class="comment">/* Add and then store the results in the destination buffer. */</span>
<a name="l00098"></a>00098 *pDst++ = __QADD(*pSrcA++, *pSrcB++);
<a name="l00099"></a>00099
<a name="l00100"></a>00100 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00101"></a>00101 blkCnt--;
<a name="l00102"></a>00102 }
<a name="l00103"></a>00103
<a name="l00104"></a>00104 <span class="preprocessor">#else</span>
<a name="l00105"></a>00105 <span class="preprocessor"></span>
<a name="l00106"></a>00106 <span class="comment">/* Run the below code for Cortex-M0 */</span>
<a name="l00107"></a>00107
<a name="l00108"></a>00108
<a name="l00109"></a>00109
<a name="l00110"></a>00110 <span class="comment">/* Initialize blkCnt with number of samples */</span>
<a name="l00111"></a>00111 blkCnt = <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>;
<a name="l00112"></a>00112
<a name="l00113"></a>00113 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00114"></a>00114 {
<a name="l00115"></a>00115 <span class="comment">/* C = A + B */</span>
<a name="l00116"></a>00116 <span class="comment">/* Add and then store the results in the destination buffer. */</span>
<a name="l00117"></a>00117 *pDst++ = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) <a class="code" href="arm__math_8h.html#ad7373e53d3c2e1adfeafc8c2e9720b5c" title="Clips Q63 to Q31 values.">clip_q63_to_q31</a>((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) * pSrcA++ + *pSrcB++);
<a name="l00118"></a>00118
<a name="l00119"></a>00119 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00120"></a>00120 blkCnt--;
<a name="l00121"></a>00121 }
<a name="l00122"></a>00122
<a name="l00123"></a>00123 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_CM0 */</span>
<a name="l00124"></a>00124
<a name="l00125"></a>00125 }
<a name="l00126"></a>00126
</pre></div></div>
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
<p><a href="arm__add__q7_8c_source.html">Go to the source code of this file.</a></p>
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Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___basic_add.html#gaed633f415a7840a66861debca2dfb96b">arm_add_q7</a> (<a class="el" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263">q7_t</a> *pSrcA, <a class="el" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263">q7_t</a> *pSrcB, <a class="el" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263">q7_t</a> *pDst, uint32_t <a class="el" href="arm__variance__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)</td></tr>
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<a href="arm__add__q7_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ---------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_add_q7.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: Q7 vector addition. </span>
<a name="l00011"></a>00011 <span class="comment">* </span>
<a name="l00012"></a>00012 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0</span>
<a name="l00013"></a>00013 <span class="comment">* </span>
<a name="l00014"></a>00014 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00015"></a>00015 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00016"></a>00016 <span class="comment">* </span>
<a name="l00017"></a>00017 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00018"></a>00018 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00019"></a>00019 <span class="comment">* </span>
<a name="l00020"></a>00020 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00021"></a>00021 <span class="comment">* Documentation updated. </span>
<a name="l00022"></a>00022 <span class="comment">* </span>
<a name="l00023"></a>00023 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00024"></a>00024 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00025"></a>00025 <span class="comment">* </span>
<a name="l00026"></a>00026 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00027"></a>00027 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00028"></a>00028 <span class="comment">* </span>
<a name="l00029"></a>00029 <span class="comment">* Version 0.0.7 2010/06/10 </span>
<a name="l00030"></a>00030 <span class="comment">* Misra-C changes done </span>
<a name="l00031"></a>00031 <span class="comment">* -------------------------------------------------------------------- */</span>
<a name="l00032"></a>00032
<a name="l00033"></a>00033 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00034"></a>00034
<a name="l00058"></a><a class="code" href="group___basic_add.html#gaed633f415a7840a66861debca2dfb96b">00058</a> <span class="keywordtype">void</span> <a class="code" href="group___basic_add.html#gaed633f415a7840a66861debca2dfb96b" title="Q7 vector addition.">arm_add_q7</a>(
<a name="l00059"></a>00059 <a class="code" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263" title="8-bit fractional data type in 1.7 format.">q7_t</a> * pSrcA,
<a name="l00060"></a>00060 <a class="code" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263" title="8-bit fractional data type in 1.7 format.">q7_t</a> * pSrcB,
<a name="l00061"></a>00061 <a class="code" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263" title="8-bit fractional data type in 1.7 format.">q7_t</a> * pDst,
<a name="l00062"></a>00062 uint32_t <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)
<a name="l00063"></a>00063 {
<a name="l00064"></a>00064 uint32_t blkCnt; <span class="comment">/* loop counter */</span>
<a name="l00065"></a>00065
<a name="l00066"></a>00066 <span class="preprocessor">#ifndef ARM_MATH_CM0</span>
<a name="l00067"></a>00067 <span class="preprocessor"></span>
<a name="l00068"></a>00068 <span class="comment">/* Run the below code for Cortex-M4 and Cortex-M3 */</span>
<a name="l00069"></a>00069
<a name="l00070"></a>00070
<a name="l00071"></a>00071 <span class="comment">/*loop Unrolling */</span>
<a name="l00072"></a>00072 blkCnt = blockSize &gt;&gt; 2u;
<a name="l00073"></a>00073
<a name="l00074"></a>00074 <span class="comment">/* First part of the processing with loop unrolling. Compute 4 outputs at a time. </span>
<a name="l00075"></a>00075 <span class="comment"> ** a second loop below computes the remaining 1 to 3 samples. */</span>
<a name="l00076"></a>00076 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00077"></a>00077 {
<a name="l00078"></a>00078 <span class="comment">/* C = A + B */</span>
<a name="l00079"></a>00079 <span class="comment">/* Add and then store the results in the destination buffer. */</span>
<a name="l00080"></a>00080 *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pDst)++ = __QADD8(*<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pSrcA)++, *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pSrcB)++);
<a name="l00081"></a>00081
<a name="l00082"></a>00082 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00083"></a>00083 blkCnt--;
<a name="l00084"></a>00084 }
<a name="l00085"></a>00085
<a name="l00086"></a>00086 <span class="comment">/* If the blockSize is not a multiple of 4, compute any remaining output samples here. </span>
<a name="l00087"></a>00087 <span class="comment"> ** No loop unrolling is used. */</span>
<a name="l00088"></a>00088 blkCnt = blockSize % 0x4u;
<a name="l00089"></a>00089
<a name="l00090"></a>00090 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00091"></a>00091 {
<a name="l00092"></a>00092 <span class="comment">/* C = A + B */</span>
<a name="l00093"></a>00093 <span class="comment">/* Add and then store the results in the destination buffer. */</span>
<a name="l00094"></a>00094 *pDst++ = (<a class="code" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263" title="8-bit fractional data type in 1.7 format.">q7_t</a>) __SSAT(*pSrcA++ + *pSrcB++, 8);
<a name="l00095"></a>00095
<a name="l00096"></a>00096 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00097"></a>00097 blkCnt--;
<a name="l00098"></a>00098 }
<a name="l00099"></a>00099
<a name="l00100"></a>00100 <span class="preprocessor">#else</span>
<a name="l00101"></a>00101 <span class="preprocessor"></span>
<a name="l00102"></a>00102 <span class="comment">/* Run the below code for Cortex-M0 */</span>
<a name="l00103"></a>00103
<a name="l00104"></a>00104
<a name="l00105"></a>00105
<a name="l00106"></a>00106 <span class="comment">/* Initialize blkCnt with number of samples */</span>
<a name="l00107"></a>00107 blkCnt = <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>;
<a name="l00108"></a>00108
<a name="l00109"></a>00109 <span class="keywordflow">while</span>(blkCnt &gt; 0u)
<a name="l00110"></a>00110 {
<a name="l00111"></a>00111 <span class="comment">/* C = A + B */</span>
<a name="l00112"></a>00112 <span class="comment">/* Add and then store the results in the destination buffer. */</span>
<a name="l00113"></a>00113 *pDst++ = (<a class="code" href="arm__math_8h.html#ae541b6f232c305361e9b416fc9eed263" title="8-bit fractional data type in 1.7 format.">q7_t</a>) __SSAT((<a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a>) * pSrcA++ + *pSrcB++, 8);
<a name="l00114"></a>00114
<a name="l00115"></a>00115 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00116"></a>00116 blkCnt--;
<a name="l00117"></a>00117 }
<a name="l00118"></a>00118
<a name="l00119"></a>00119 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_CM0 */</span>
<a name="l00120"></a>00120
<a name="l00121"></a>00121
<a name="l00122"></a>00122 }
<a name="l00123"></a>00123
</pre></div></div>
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<h1>arm_biquad_cascade_df1_32x64_init_q31.c File Reference</h1> </div>
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
<p><a href="arm__biquad__cascade__df1__32x64__init__q31_8c_source.html">Go to the source code of this file.</a></p>
<table class="memberdecls">
<tr><td colspan="2"><h2><a name="func-members"></a>
Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___biquad_cascade_d_f1__32x64.html#ga44900cecb8083afcaabf905ffcd656bb">arm_biquad_cas_df1_32x64_init_q31</a> (<a class="el" href="structarm__biquad__cas__df1__32x64__ins__q31.html">arm_biquad_cas_df1_32x64_ins_q31</a> *S, uint8_t numStages, <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> *pCoeffs, <a class="el" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6">q63_t</a> *pState, uint8_t postShift)</td></tr>
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<a href="arm__biquad__cascade__df1__32x64__init__q31_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ---------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_biquad_cascade_df1_32x64_init_q31.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: High precision Q31 Biquad cascade filter initialization function. </span>
<a name="l00011"></a>00011 <span class="comment">* </span>
<a name="l00012"></a>00012 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0</span>
<a name="l00013"></a>00013 <span class="comment">* </span>
<a name="l00014"></a>00014 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00015"></a>00015 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00016"></a>00016 <span class="comment">* </span>
<a name="l00017"></a>00017 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00018"></a>00018 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00019"></a>00019 <span class="comment">* </span>
<a name="l00020"></a>00020 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00021"></a>00021 <span class="comment">* Documentation updated. </span>
<a name="l00022"></a>00022 <span class="comment">* </span>
<a name="l00023"></a>00023 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00024"></a>00024 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00025"></a>00025 <span class="comment">* </span>
<a name="l00026"></a>00026 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00027"></a>00027 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00028"></a>00028 <span class="comment">* </span>
<a name="l00029"></a>00029 <span class="comment">* Version 0.0.7 2010/06/10 </span>
<a name="l00030"></a>00030 <span class="comment">* Misra-C changes done </span>
<a name="l00031"></a>00031 <span class="comment">* -------------------------------------------------------------------- */</span>
<a name="l00032"></a>00032
<a name="l00033"></a>00033 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00034"></a>00034
<a name="l00077"></a><a class="code" href="group___biquad_cascade_d_f1__32x64.html#ga44900cecb8083afcaabf905ffcd656bb">00077</a> <span class="keywordtype">void</span> <a class="code" href="group___biquad_cascade_d_f1__32x64.html#ga44900cecb8083afcaabf905ffcd656bb">arm_biquad_cas_df1_32x64_init_q31</a>(
<a name="l00078"></a>00078 <a class="code" href="structarm__biquad__cas__df1__32x64__ins__q31.html" title="Instance structure for the high precision Q31 Biquad cascade filter.">arm_biquad_cas_df1_32x64_ins_q31</a> * S,
<a name="l00079"></a>00079 uint8_t numStages,
<a name="l00080"></a>00080 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> * pCoeffs,
<a name="l00081"></a>00081 <a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a> * pState,
<a name="l00082"></a>00082 uint8_t postShift)
<a name="l00083"></a>00083 {
<a name="l00084"></a>00084 <span class="comment">/* Assign filter stages */</span>
<a name="l00085"></a>00085 S-&gt;<a class="code" href="structarm__biquad__cas__df1__32x64__ins__q31.html#ad7cb9a9f5df8f4fcfc7a0b633672e574">numStages</a> = numStages;
<a name="l00086"></a>00086
<a name="l00087"></a>00087 <span class="comment">/* Assign postShift to be applied to the output */</span>
<a name="l00088"></a>00088 S-&gt;<a class="code" href="structarm__biquad__cas__df1__32x64__ins__q31.html#a8e9d58e8dba5aa3b2fc4f36d2ed07996">postShift</a> = postShift;
<a name="l00089"></a>00089
<a name="l00090"></a>00090 <span class="comment">/* Assign coefficient pointer */</span>
<a name="l00091"></a>00091 S-&gt;<a class="code" href="structarm__biquad__cas__df1__32x64__ins__q31.html#a490462d6ebe0fecfb6acbf51bed22ecf">pCoeffs</a> = pCoeffs;
<a name="l00092"></a>00092
<a name="l00093"></a>00093 <span class="comment">/* Clear state buffer and size is always 4 * numStages */</span>
<a name="l00094"></a>00094 memset(pState, 0, (4u * (uint32_t) numStages) * <span class="keyword">sizeof</span>(<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>));
<a name="l00095"></a>00095
<a name="l00096"></a>00096 <span class="comment">/* Assign state pointer */</span>
<a name="l00097"></a>00097 S-&gt;<a class="code" href="structarm__biquad__cas__df1__32x64__ins__q31.html#a4c899cdfaf2bb955323e93637bd662e0">pState</a> = pState;
<a name="l00098"></a>00098 }
<a name="l00099"></a>00099
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
<p><a href="arm__biquad__cascade__df1__32x64__q31_8c_source.html">Go to the source code of this file.</a></p>
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Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___biquad_cascade_d_f1__32x64.html#ga953a83e69685de6575cff37feb358a93">arm_biquad_cas_df1_32x64_q31</a> (const <a class="el" href="structarm__biquad__cas__df1__32x64__ins__q31.html">arm_biquad_cas_df1_32x64_ins_q31</a> *S, <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> *pSrc, <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> *pDst, uint32_t <a class="el" href="arm__variance__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)</td></tr>
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<a href="arm__biquad__cascade__df1__32x64__q31_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ---------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_biquad_cascade_df1_32x64_q31.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: High precision Q31 Biquad cascade filter processing function </span>
<a name="l00011"></a>00011 <span class="comment">* </span>
<a name="l00012"></a>00012 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0</span>
<a name="l00013"></a>00013 <span class="comment">* </span>
<a name="l00014"></a>00014 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00015"></a>00015 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00016"></a>00016 <span class="comment">* </span>
<a name="l00017"></a>00017 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00018"></a>00018 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00019"></a>00019 <span class="comment">* </span>
<a name="l00020"></a>00020 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00021"></a>00021 <span class="comment">* Documentation updated. </span>
<a name="l00022"></a>00022 <span class="comment">* </span>
<a name="l00023"></a>00023 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00024"></a>00024 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00025"></a>00025 <span class="comment">* </span>
<a name="l00026"></a>00026 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00027"></a>00027 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00028"></a>00028 <span class="comment">* </span>
<a name="l00029"></a>00029 <span class="comment">* Version 0.0.7 2010/06/10 </span>
<a name="l00030"></a>00030 <span class="comment">* Misra-C changes done </span>
<a name="l00031"></a>00031 <span class="comment">* -------------------------------------------------------------------- */</span>
<a name="l00032"></a>00032
<a name="l00033"></a>00033 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00034"></a>00034
<a name="l00176"></a><a class="code" href="group___biquad_cascade_d_f1__32x64.html#ga953a83e69685de6575cff37feb358a93">00176</a> <span class="keywordtype">void</span> <a class="code" href="group___biquad_cascade_d_f1__32x64.html#ga953a83e69685de6575cff37feb358a93">arm_biquad_cas_df1_32x64_q31</a>(
<a name="l00177"></a>00177 <span class="keyword">const</span> <a class="code" href="structarm__biquad__cas__df1__32x64__ins__q31.html" title="Instance structure for the high precision Q31 Biquad cascade filter.">arm_biquad_cas_df1_32x64_ins_q31</a> * S,
<a name="l00178"></a>00178 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> * pSrc,
<a name="l00179"></a>00179 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> * pDst,
<a name="l00180"></a>00180 uint32_t <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)
<a name="l00181"></a>00181 {
<a name="l00182"></a>00182 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> *pIn = pSrc; <span class="comment">/* input pointer initialization */</span>
<a name="l00183"></a>00183 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> *pOut = pDst; <span class="comment">/* output pointer initialization */</span>
<a name="l00184"></a>00184 <a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a> *pState = S-&gt;<a class="code" href="structarm__biquad__cas__df1__32x64__ins__q31.html#a4c899cdfaf2bb955323e93637bd662e0">pState</a>; <span class="comment">/* state pointer initialization */</span>
<a name="l00185"></a>00185 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> *pCoeffs = S-&gt;<a class="code" href="structarm__biquad__cas__df1__32x64__ins__q31.html#a490462d6ebe0fecfb6acbf51bed22ecf">pCoeffs</a>; <span class="comment">/* coeff pointer initialization */</span>
<a name="l00186"></a>00186 <a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a> acc; <span class="comment">/* accumulator */</span>
<a name="l00187"></a>00187 <a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a> Xn1, Xn2, Yn1, Yn2; <span class="comment">/* Filter state variables */</span>
<a name="l00188"></a>00188 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> b0, b1, b2, a1, a2; <span class="comment">/* Filter coefficients */</span>
<a name="l00189"></a>00189 <a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a> Xn; <span class="comment">/* temporary input */</span>
<a name="l00190"></a>00190 int32_t shift = (int32_t) S-&gt;<a class="code" href="structarm__biquad__cas__df1__32x64__ins__q31.html#a8e9d58e8dba5aa3b2fc4f36d2ed07996">postShift</a> + 1; <span class="comment">/* Shift to be applied to the output */</span>
<a name="l00191"></a>00191 uint32_t sample, stage = S-&gt;<a class="code" href="structarm__biquad__cas__df1__32x64__ins__q31.html#ad7cb9a9f5df8f4fcfc7a0b633672e574">numStages</a>; <span class="comment">/* loop counters */</span>
<a name="l00192"></a>00192
<a name="l00193"></a>00193
<a name="l00194"></a>00194 #ifndef ARM_MATH_CM0
<a name="l00195"></a>00195
<a name="l00196"></a>00196 <span class="comment">/* Run the below code for Cortex-M4 and Cortex-M3 */</span>
<a name="l00197"></a>00197
<a name="l00198"></a>00198 <span class="keywordflow">do</span>
<a name="l00199"></a>00199 {
<a name="l00200"></a>00200 <span class="comment">/* Reading the coefficients */</span>
<a name="l00201"></a>00201 b0 = *pCoeffs++;
<a name="l00202"></a>00202 b1 = *pCoeffs++;
<a name="l00203"></a>00203 b2 = *pCoeffs++;
<a name="l00204"></a>00204 a1 = *pCoeffs++;
<a name="l00205"></a>00205 a2 = *pCoeffs++;
<a name="l00206"></a>00206
<a name="l00207"></a>00207 <span class="comment">/* Reading the state values */</span>
<a name="l00208"></a>00208 Xn1 = pState[0];
<a name="l00209"></a>00209 Xn2 = pState[1];
<a name="l00210"></a>00210 Yn1 = pState[2];
<a name="l00211"></a>00211 Yn2 = pState[3];
<a name="l00212"></a>00212
<a name="l00213"></a>00213 <span class="comment">/* Apply loop unrolling and compute 4 output values simultaneously. */</span>
<a name="l00214"></a>00214 <span class="comment">/* The variable acc hold output value that is being computed and </span>
<a name="l00215"></a>00215 <span class="comment"> * stored in the destination buffer </span>
<a name="l00216"></a>00216 <span class="comment"> * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] </span>
<a name="l00217"></a>00217 <span class="comment"> */</span>
<a name="l00218"></a>00218
<a name="l00219"></a>00219 sample = blockSize &gt;&gt; 2u;
<a name="l00220"></a>00220
<a name="l00221"></a>00221 <span class="comment">/* First part of the processing with loop unrolling. Compute 4 outputs at a time. </span>
<a name="l00222"></a>00222 <span class="comment"> ** a second loop below computes the remaining 1 to 3 samples. */</span>
<a name="l00223"></a>00223 <span class="keywordflow">while</span>(sample &gt; 0u)
<a name="l00224"></a>00224 {
<a name="l00225"></a>00225 <span class="comment">/* Read the input */</span>
<a name="l00226"></a>00226 Xn = *pIn++;
<a name="l00227"></a>00227
<a name="l00228"></a>00228 <span class="comment">/* The value is shifted to the MSB to perform 32x64 multiplication */</span>
<a name="l00229"></a>00229 Xn = Xn &lt;&lt; 32;
<a name="l00230"></a>00230
<a name="l00231"></a>00231 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00232"></a>00232
<a name="l00233"></a>00233 <span class="comment">/* acc = b0 * x[n] */</span>
<a name="l00234"></a>00234 acc = <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Xn, b0);
<a name="l00235"></a>00235 <span class="comment">/* acc += b1 * x[n-1] */</span>
<a name="l00236"></a>00236 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Xn1, b1);
<a name="l00237"></a>00237 <span class="comment">/* acc += b[2] * x[n-2] */</span>
<a name="l00238"></a>00238 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Xn2, b2);
<a name="l00239"></a>00239 <span class="comment">/* acc += a1 * y[n-1] */</span>
<a name="l00240"></a>00240 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Yn1, a1);
<a name="l00241"></a>00241 <span class="comment">/* acc += a2 * y[n-2] */</span>
<a name="l00242"></a>00242 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Yn2, a2);
<a name="l00243"></a>00243
<a name="l00244"></a>00244 <span class="comment">/* The result is converted to 1.63 , Yn2 variable is reused */</span>
<a name="l00245"></a>00245 Yn2 = acc &lt;&lt; shift;
<a name="l00246"></a>00246
<a name="l00247"></a>00247 <span class="comment">/* Store the output in the destination buffer in 1.31 format. */</span>
<a name="l00248"></a>00248 *pOut++ = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) (acc &gt;&gt; (32 - shift));
<a name="l00249"></a>00249
<a name="l00250"></a>00250 <span class="comment">/* Read the second input into Xn2, to reuse the value */</span>
<a name="l00251"></a>00251 Xn2 = *pIn++;
<a name="l00252"></a>00252
<a name="l00253"></a>00253 <span class="comment">/* The value is shifted to the MSB to perform 32x64 multiplication */</span>
<a name="l00254"></a>00254 Xn2 = Xn2 &lt;&lt; 32;
<a name="l00255"></a>00255
<a name="l00256"></a>00256 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00257"></a>00257
<a name="l00258"></a>00258 <span class="comment">/* acc = b0 * x[n] */</span>
<a name="l00259"></a>00259 acc = <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Xn2, b0);
<a name="l00260"></a>00260 <span class="comment">/* acc += b1 * x[n-1] */</span>
<a name="l00261"></a>00261 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Xn, b1);
<a name="l00262"></a>00262 <span class="comment">/* acc += b[2] * x[n-2] */</span>
<a name="l00263"></a>00263 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Xn1, b2);
<a name="l00264"></a>00264 <span class="comment">/* acc += a1 * y[n-1] */</span>
<a name="l00265"></a>00265 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Yn2, a1);
<a name="l00266"></a>00266 <span class="comment">/* acc += a2 * y[n-2] */</span>
<a name="l00267"></a>00267 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Yn1, a2);
<a name="l00268"></a>00268
<a name="l00269"></a>00269 <span class="comment">/* The result is converted to 1.63, Yn1 variable is reused */</span>
<a name="l00270"></a>00270 Yn1 = acc &lt;&lt; shift;
<a name="l00271"></a>00271
<a name="l00272"></a>00272 <span class="comment">/* The result is converted to 1.31 */</span>
<a name="l00273"></a>00273 <span class="comment">/* Store the output in the destination buffer. */</span>
<a name="l00274"></a>00274 *pOut++ = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) (acc &gt;&gt; (32 - shift));
<a name="l00275"></a>00275
<a name="l00276"></a>00276 <span class="comment">/* Read the third input into Xn1, to reuse the value */</span>
<a name="l00277"></a>00277 Xn1 = *pIn++;
<a name="l00278"></a>00278
<a name="l00279"></a>00279 <span class="comment">/* The value is shifted to the MSB to perform 32x64 multiplication */</span>
<a name="l00280"></a>00280 Xn1 = Xn1 &lt;&lt; 32;
<a name="l00281"></a>00281
<a name="l00282"></a>00282 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00283"></a>00283 <span class="comment">/* acc = b0 * x[n] */</span>
<a name="l00284"></a>00284 acc = <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Xn1, b0);
<a name="l00285"></a>00285 <span class="comment">/* acc += b1 * x[n-1] */</span>
<a name="l00286"></a>00286 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Xn2, b1);
<a name="l00287"></a>00287 <span class="comment">/* acc += b[2] * x[n-2] */</span>
<a name="l00288"></a>00288 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Xn, b2);
<a name="l00289"></a>00289 <span class="comment">/* acc += a1 * y[n-1] */</span>
<a name="l00290"></a>00290 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Yn1, a1);
<a name="l00291"></a>00291 <span class="comment">/* acc += a2 * y[n-2] */</span>
<a name="l00292"></a>00292 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Yn2, a2);
<a name="l00293"></a>00293
<a name="l00294"></a>00294 <span class="comment">/* The result is converted to 1.63, Yn2 variable is reused */</span>
<a name="l00295"></a>00295 Yn2 = acc &lt;&lt; shift;
<a name="l00296"></a>00296
<a name="l00297"></a>00297 <span class="comment">/* Store the output in the destination buffer in 1.31 format. */</span>
<a name="l00298"></a>00298 *pOut++ = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) (acc &gt;&gt; (32 - shift));
<a name="l00299"></a>00299
<a name="l00300"></a>00300 <span class="comment">/* Read the fourth input into Xn, to reuse the value */</span>
<a name="l00301"></a>00301 Xn = *pIn++;
<a name="l00302"></a>00302
<a name="l00303"></a>00303 <span class="comment">/* The value is shifted to the MSB to perform 32x64 multiplication */</span>
<a name="l00304"></a>00304 Xn = Xn &lt;&lt; 32;
<a name="l00305"></a>00305
<a name="l00306"></a>00306 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00307"></a>00307 <span class="comment">/* acc = b0 * x[n] */</span>
<a name="l00308"></a>00308 acc = <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Xn, b0);
<a name="l00309"></a>00309 <span class="comment">/* acc += b1 * x[n-1] */</span>
<a name="l00310"></a>00310 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Xn1, b1);
<a name="l00311"></a>00311 <span class="comment">/* acc += b[2] * x[n-2] */</span>
<a name="l00312"></a>00312 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Xn2, b2);
<a name="l00313"></a>00313 <span class="comment">/* acc += a1 * y[n-1] */</span>
<a name="l00314"></a>00314 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Yn2, a1);
<a name="l00315"></a>00315 <span class="comment">/* acc += a2 * y[n-2] */</span>
<a name="l00316"></a>00316 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Yn1, a2);
<a name="l00317"></a>00317
<a name="l00318"></a>00318 <span class="comment">/* The result is converted to 1.63, Yn1 variable is reused */</span>
<a name="l00319"></a>00319 Yn1 = acc &lt;&lt; shift;
<a name="l00320"></a>00320
<a name="l00321"></a>00321 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00322"></a>00322 <span class="comment">/* The states should be updated as: */</span>
<a name="l00323"></a>00323 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00324"></a>00324 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00325"></a>00325 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00326"></a>00326 <span class="comment">/* Yn1 = acc */</span>
<a name="l00327"></a>00327 Xn2 = Xn1;
<a name="l00328"></a>00328 Xn1 = Xn;
<a name="l00329"></a>00329
<a name="l00330"></a>00330 <span class="comment">/* Store the output in the destination buffer in 1.31 format. */</span>
<a name="l00331"></a>00331 *pOut++ = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) (acc &gt;&gt; (32 - shift));
<a name="l00332"></a>00332
<a name="l00333"></a>00333 <span class="comment">/* decrement the loop counter */</span>
<a name="l00334"></a>00334 sample--;
<a name="l00335"></a>00335 }
<a name="l00336"></a>00336
<a name="l00337"></a>00337 <span class="comment">/* If the blockSize is not a multiple of 4, compute any remaining output samples here. </span>
<a name="l00338"></a>00338 <span class="comment"> ** No loop unrolling is used. */</span>
<a name="l00339"></a>00339 sample = (blockSize &amp; 0x3u);
<a name="l00340"></a>00340
<a name="l00341"></a>00341 <span class="keywordflow">while</span>(sample &gt; 0u)
<a name="l00342"></a>00342 {
<a name="l00343"></a>00343 <span class="comment">/* Read the input */</span>
<a name="l00344"></a>00344 Xn = *pIn++;
<a name="l00345"></a>00345
<a name="l00346"></a>00346 <span class="comment">/* The value is shifted to the MSB to perform 32x64 multiplication */</span>
<a name="l00347"></a>00347 Xn = Xn &lt;&lt; 32;
<a name="l00348"></a>00348
<a name="l00349"></a>00349 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00350"></a>00350 <span class="comment">/* acc = b0 * x[n] */</span>
<a name="l00351"></a>00351 acc = <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Xn, b0);
<a name="l00352"></a>00352 <span class="comment">/* acc += b1 * x[n-1] */</span>
<a name="l00353"></a>00353 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Xn1, b1);
<a name="l00354"></a>00354 <span class="comment">/* acc += b[2] * x[n-2] */</span>
<a name="l00355"></a>00355 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Xn2, b2);
<a name="l00356"></a>00356 <span class="comment">/* acc += a1 * y[n-1] */</span>
<a name="l00357"></a>00357 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Yn1, a1);
<a name="l00358"></a>00358 <span class="comment">/* acc += a2 * y[n-2] */</span>
<a name="l00359"></a>00359 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Yn2, a2);
<a name="l00360"></a>00360
<a name="l00361"></a>00361 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00362"></a>00362 <span class="comment">/* The states should be updated as: */</span>
<a name="l00363"></a>00363 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00364"></a>00364 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00365"></a>00365 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00366"></a>00366 <span class="comment">/* Yn1 = acc */</span>
<a name="l00367"></a>00367 Xn2 = Xn1;
<a name="l00368"></a>00368 Xn1 = Xn;
<a name="l00369"></a>00369 Yn2 = Yn1;
<a name="l00370"></a>00370 Yn1 = acc &lt;&lt; shift;
<a name="l00371"></a>00371
<a name="l00372"></a>00372 <span class="comment">/* Store the output in the destination buffer in 1.31 format. */</span>
<a name="l00373"></a>00373 *pOut++ = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) (acc &gt;&gt; (32 - shift));
<a name="l00374"></a>00374
<a name="l00375"></a>00375 <span class="comment">/* decrement the loop counter */</span>
<a name="l00376"></a>00376 sample--;
<a name="l00377"></a>00377 }
<a name="l00378"></a>00378
<a name="l00379"></a>00379 <span class="comment">/* The first stage output is given as input to the second stage. */</span>
<a name="l00380"></a>00380 pIn = pDst;
<a name="l00381"></a>00381
<a name="l00382"></a>00382 <span class="comment">/* Reset to destination buffer working pointer */</span>
<a name="l00383"></a>00383 pOut = pDst;
<a name="l00384"></a>00384
<a name="l00385"></a>00385 <span class="comment">/* Store the updated state variables back into the pState array */</span>
<a name="l00386"></a>00386 *pState++ = Xn1;
<a name="l00387"></a>00387 *pState++ = Xn2;
<a name="l00388"></a>00388 *pState++ = Yn1;
<a name="l00389"></a>00389 *pState++ = Yn2;
<a name="l00390"></a>00390
<a name="l00391"></a>00391 } <span class="keywordflow">while</span>(--stage);
<a name="l00392"></a>00392
<a name="l00393"></a>00393 <span class="preprocessor">#else</span>
<a name="l00394"></a>00394 <span class="preprocessor"></span>
<a name="l00395"></a>00395 <span class="comment">/* Run the below code for Cortex-M0 */</span>
<a name="l00396"></a>00396
<a name="l00397"></a>00397 <span class="keywordflow">do</span>
<a name="l00398"></a>00398 {
<a name="l00399"></a>00399 <span class="comment">/* Reading the coefficients */</span>
<a name="l00400"></a>00400 b0 = *pCoeffs++;
<a name="l00401"></a>00401 b1 = *pCoeffs++;
<a name="l00402"></a>00402 b2 = *pCoeffs++;
<a name="l00403"></a>00403 a1 = *pCoeffs++;
<a name="l00404"></a>00404 a2 = *pCoeffs++;
<a name="l00405"></a>00405
<a name="l00406"></a>00406 <span class="comment">/* Reading the state values */</span>
<a name="l00407"></a>00407 Xn1 = pState[0];
<a name="l00408"></a>00408 Xn2 = pState[1];
<a name="l00409"></a>00409 Yn1 = pState[2];
<a name="l00410"></a>00410 Yn2 = pState[3];
<a name="l00411"></a>00411
<a name="l00412"></a>00412 <span class="comment">/* The variable acc hold output value that is being computed and </span>
<a name="l00413"></a>00413 <span class="comment"> * stored in the destination buffer </span>
<a name="l00414"></a>00414 <span class="comment"> * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] </span>
<a name="l00415"></a>00415 <span class="comment"> */</span>
<a name="l00416"></a>00416
<a name="l00417"></a>00417 sample = <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>;
<a name="l00418"></a>00418
<a name="l00419"></a>00419 <span class="keywordflow">while</span>(sample &gt; 0u)
<a name="l00420"></a>00420 {
<a name="l00421"></a>00421 <span class="comment">/* Read the input */</span>
<a name="l00422"></a>00422 Xn = *pIn++;
<a name="l00423"></a>00423
<a name="l00424"></a>00424 <span class="comment">/* The value is shifted to the MSB to perform 32x64 multiplication */</span>
<a name="l00425"></a>00425 Xn = Xn &lt;&lt; 32;
<a name="l00426"></a>00426
<a name="l00427"></a>00427 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00428"></a>00428 <span class="comment">/* acc = b0 * x[n] */</span>
<a name="l00429"></a>00429 acc = <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Xn, b0);
<a name="l00430"></a>00430 <span class="comment">/* acc += b1 * x[n-1] */</span>
<a name="l00431"></a>00431 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Xn1, b1);
<a name="l00432"></a>00432 <span class="comment">/* acc += b[2] * x[n-2] */</span>
<a name="l00433"></a>00433 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Xn2, b2);
<a name="l00434"></a>00434 <span class="comment">/* acc += a1 * y[n-1] */</span>
<a name="l00435"></a>00435 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Yn1, a1);
<a name="l00436"></a>00436 <span class="comment">/* acc += a2 * y[n-2] */</span>
<a name="l00437"></a>00437 acc += <a class="code" href="arm__math_8h.html#a642a29d71f7951a7f6c0b797c300b711" title="Multiplies 32 X 64 and returns 32 bit result in 2.30 format.">mult32x64</a>(Yn2, a2);
<a name="l00438"></a>00438
<a name="l00439"></a>00439 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00440"></a>00440 <span class="comment">/* The states should be updated as: */</span>
<a name="l00441"></a>00441 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00442"></a>00442 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00443"></a>00443 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00444"></a>00444 <span class="comment">/* Yn1 = acc */</span>
<a name="l00445"></a>00445 Xn2 = Xn1;
<a name="l00446"></a>00446 Xn1 = Xn;
<a name="l00447"></a>00447 Yn2 = Yn1;
<a name="l00448"></a>00448 Yn1 = acc &lt;&lt; shift;
<a name="l00449"></a>00449
<a name="l00450"></a>00450 <span class="comment">/* Store the output in the destination buffer in 1.31 format. */</span>
<a name="l00451"></a>00451 *pOut++ = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) (acc &gt;&gt; (32 - shift));
<a name="l00452"></a>00452
<a name="l00453"></a>00453 <span class="comment">/* decrement the loop counter */</span>
<a name="l00454"></a>00454 sample--;
<a name="l00455"></a>00455 }
<a name="l00456"></a>00456
<a name="l00457"></a>00457 <span class="comment">/* The first stage output is given as input to the second stage. */</span>
<a name="l00458"></a>00458 pIn = pDst;
<a name="l00459"></a>00459
<a name="l00460"></a>00460 <span class="comment">/* Reset to destination buffer working pointer */</span>
<a name="l00461"></a>00461 pOut = pDst;
<a name="l00462"></a>00462
<a name="l00463"></a>00463 <span class="comment">/* Store the updated state variables back into the pState array */</span>
<a name="l00464"></a>00464 *pState++ = Xn1;
<a name="l00465"></a>00465 *pState++ = Xn2;
<a name="l00466"></a>00466 *pState++ = Yn1;
<a name="l00467"></a>00467 *pState++ = Yn2;
<a name="l00468"></a>00468
<a name="l00469"></a>00469 } <span class="keywordflow">while</span>(--stage);
<a name="l00470"></a>00470
<a name="l00471"></a>00471 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_CM0 */</span>
<a name="l00472"></a>00472 }
<a name="l00473"></a>00473
</pre></div></div>
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
<p><a href="arm__biquad__cascade__df1__f32_8c_source.html">Go to the source code of this file.</a></p>
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Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___biquad_cascade_d_f1.html#gaa0dbe330d763e3c1d8030b3ef12d5bdc">arm_biquad_cascade_df1_f32</a> (const <a class="el" href="structarm__biquad__casd__df1__inst__f32.html">arm_biquad_casd_df1_inst_f32</a> *S, <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> *pSrc, <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> *pDst, uint32_t <a class="el" href="arm__variance__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)</td></tr>
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<a href="arm__biquad__cascade__df1__f32_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ---------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_biquad_cascade_df1_f32.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: Processing function for the </span>
<a name="l00011"></a>00011 <span class="comment">* floating-point Biquad cascade DirectFormI(DF1) filter. </span>
<a name="l00012"></a>00012 <span class="comment">* </span>
<a name="l00013"></a>00013 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0</span>
<a name="l00014"></a>00014 <span class="comment">* </span>
<a name="l00015"></a>00015 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00016"></a>00016 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00017"></a>00017 <span class="comment">* </span>
<a name="l00018"></a>00018 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00019"></a>00019 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00020"></a>00020 <span class="comment">* </span>
<a name="l00021"></a>00021 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00022"></a>00022 <span class="comment">* Documentation updated. </span>
<a name="l00023"></a>00023 <span class="comment">* </span>
<a name="l00024"></a>00024 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00025"></a>00025 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00026"></a>00026 <span class="comment">* </span>
<a name="l00027"></a>00027 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00028"></a>00028 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00029"></a>00029 <span class="comment">* </span>
<a name="l00030"></a>00030 <span class="comment">* Version 0.0.5 2010/04/26 </span>
<a name="l00031"></a>00031 <span class="comment">* incorporated review comments and updated with latest CMSIS layer </span>
<a name="l00032"></a>00032 <span class="comment">* </span>
<a name="l00033"></a>00033 <span class="comment">* Version 0.0.3 2010/03/10 </span>
<a name="l00034"></a>00034 <span class="comment">* Initial version </span>
<a name="l00035"></a>00035 <span class="comment">* -------------------------------------------------------------------- */</span>
<a name="l00036"></a>00036
<a name="l00037"></a>00037 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00038"></a>00038
<a name="l00171"></a><a class="code" href="group___biquad_cascade_d_f1.html#gaa0dbe330d763e3c1d8030b3ef12d5bdc">00171</a> <span class="keywordtype">void</span> <a class="code" href="group___biquad_cascade_d_f1.html#gaa0dbe330d763e3c1d8030b3ef12d5bdc" title="Processing function for the floating-point Biquad cascade filter.">arm_biquad_cascade_df1_f32</a>(
<a name="l00172"></a>00172 <span class="keyword">const</span> <a class="code" href="structarm__biquad__casd__df1__inst__f32.html" title="Instance structure for the floating-point Biquad cascade filter.">arm_biquad_casd_df1_inst_f32</a> * S,
<a name="l00173"></a>00173 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> * pSrc,
<a name="l00174"></a>00174 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> * pDst,
<a name="l00175"></a>00175 uint32_t <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)
<a name="l00176"></a>00176 {
<a name="l00177"></a>00177 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> *pIn = pSrc; <span class="comment">/* source pointer */</span>
<a name="l00178"></a>00178 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> *pOut = pDst; <span class="comment">/* destination pointer */</span>
<a name="l00179"></a>00179 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> *pState = S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__f32.html#a8c245d79e0d8cfabc82409d4b54fb682">pState</a>; <span class="comment">/* pState pointer */</span>
<a name="l00180"></a>00180 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> *pCoeffs = S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__f32.html#af9df3820576fb921809d1462c9c6d16c">pCoeffs</a>; <span class="comment">/* coefficient pointer */</span>
<a name="l00181"></a>00181 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> acc; <span class="comment">/* Simulates the accumulator */</span>
<a name="l00182"></a>00182 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> b0, b1, b2, a1, a2; <span class="comment">/* Filter coefficients */</span>
<a name="l00183"></a>00183 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> Xn1, Xn2, Yn1, Yn2; <span class="comment">/* Filter pState variables */</span>
<a name="l00184"></a>00184 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> Xn; <span class="comment">/* temporary input */</span>
<a name="l00185"></a>00185 uint32_t sample, stage = S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__f32.html#af69820c37a87252c46453e4cfe120585">numStages</a>; <span class="comment">/* loop counters */</span>
<a name="l00186"></a>00186
<a name="l00187"></a>00187
<a name="l00188"></a>00188 <span class="preprocessor">#ifndef ARM_MATH_CM0</span>
<a name="l00189"></a>00189 <span class="preprocessor"></span>
<a name="l00190"></a>00190 <span class="comment">/* Run the below code for Cortex-M4 and Cortex-M3 */</span>
<a name="l00191"></a>00191
<a name="l00192"></a>00192 <span class="keywordflow">do</span>
<a name="l00193"></a>00193 {
<a name="l00194"></a>00194 <span class="comment">/* Reading the coefficients */</span>
<a name="l00195"></a>00195 b0 = *pCoeffs++;
<a name="l00196"></a>00196 b1 = *pCoeffs++;
<a name="l00197"></a>00197 b2 = *pCoeffs++;
<a name="l00198"></a>00198 a1 = *pCoeffs++;
<a name="l00199"></a>00199 a2 = *pCoeffs++;
<a name="l00200"></a>00200
<a name="l00201"></a>00201 <span class="comment">/* Reading the pState values */</span>
<a name="l00202"></a>00202 Xn1 = pState[0];
<a name="l00203"></a>00203 Xn2 = pState[1];
<a name="l00204"></a>00204 Yn1 = pState[2];
<a name="l00205"></a>00205 Yn2 = pState[3];
<a name="l00206"></a>00206
<a name="l00207"></a>00207 <span class="comment">/* Apply loop unrolling and compute 4 output values simultaneously. */</span>
<a name="l00208"></a>00208 <span class="comment">/* The variable acc hold output values that are being computed: </span>
<a name="l00209"></a>00209 <span class="comment"> * </span>
<a name="l00210"></a>00210 <span class="comment"> * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] </span>
<a name="l00211"></a>00211 <span class="comment"> * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] </span>
<a name="l00212"></a>00212 <span class="comment"> * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] </span>
<a name="l00213"></a>00213 <span class="comment"> * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] </span>
<a name="l00214"></a>00214 <span class="comment"> */</span>
<a name="l00215"></a>00215
<a name="l00216"></a>00216 sample = blockSize &gt;&gt; 2u;
<a name="l00217"></a>00217
<a name="l00218"></a>00218 <span class="comment">/* First part of the processing with loop unrolling. Compute 4 outputs at a time. </span>
<a name="l00219"></a>00219 <span class="comment"> ** a second loop below computes the remaining 1 to 3 samples. */</span>
<a name="l00220"></a>00220 <span class="keywordflow">while</span>(sample &gt; 0u)
<a name="l00221"></a>00221 {
<a name="l00222"></a>00222 <span class="comment">/* Read the first input */</span>
<a name="l00223"></a>00223 Xn = *pIn++;
<a name="l00224"></a>00224
<a name="l00225"></a>00225 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00226"></a>00226 Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
<a name="l00227"></a>00227
<a name="l00228"></a>00228 <span class="comment">/* Store the result in the accumulator in the destination buffer. */</span>
<a name="l00229"></a>00229 *pOut++ = Yn2;
<a name="l00230"></a>00230
<a name="l00231"></a>00231 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00232"></a>00232 <span class="comment">/* The states should be updated as: */</span>
<a name="l00233"></a>00233 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00234"></a>00234 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00235"></a>00235 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00236"></a>00236 <span class="comment">/* Yn1 = acc */</span>
<a name="l00237"></a>00237
<a name="l00238"></a>00238 <span class="comment">/* Read the second input */</span>
<a name="l00239"></a>00239 Xn2 = *pIn++;
<a name="l00240"></a>00240
<a name="l00241"></a>00241 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00242"></a>00242 Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1);
<a name="l00243"></a>00243
<a name="l00244"></a>00244 <span class="comment">/* Store the result in the accumulator in the destination buffer. */</span>
<a name="l00245"></a>00245 *pOut++ = Yn1;
<a name="l00246"></a>00246
<a name="l00247"></a>00247 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00248"></a>00248 <span class="comment">/* The states should be updated as: */</span>
<a name="l00249"></a>00249 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00250"></a>00250 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00251"></a>00251 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00252"></a>00252 <span class="comment">/* Yn1 = acc */</span>
<a name="l00253"></a>00253
<a name="l00254"></a>00254 <span class="comment">/* Read the third input */</span>
<a name="l00255"></a>00255 Xn1 = *pIn++;
<a name="l00256"></a>00256
<a name="l00257"></a>00257 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00258"></a>00258 Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2);
<a name="l00259"></a>00259
<a name="l00260"></a>00260 <span class="comment">/* Store the result in the accumulator in the destination buffer. */</span>
<a name="l00261"></a>00261 *pOut++ = Yn2;
<a name="l00262"></a>00262
<a name="l00263"></a>00263 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00264"></a>00264 <span class="comment">/* The states should be updated as: */</span>
<a name="l00265"></a>00265 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00266"></a>00266 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00267"></a>00267 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00268"></a>00268 <span class="comment">/* Yn1 = acc */</span>
<a name="l00269"></a>00269
<a name="l00270"></a>00270 <span class="comment">/* Read the forth input */</span>
<a name="l00271"></a>00271 Xn = *pIn++;
<a name="l00272"></a>00272
<a name="l00273"></a>00273 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00274"></a>00274 Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1);
<a name="l00275"></a>00275
<a name="l00276"></a>00276 <span class="comment">/* Store the result in the accumulator in the destination buffer. */</span>
<a name="l00277"></a>00277 *pOut++ = Yn1;
<a name="l00278"></a>00278
<a name="l00279"></a>00279 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00280"></a>00280 <span class="comment">/* The states should be updated as: */</span>
<a name="l00281"></a>00281 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00282"></a>00282 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00283"></a>00283 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00284"></a>00284 <span class="comment">/* Yn1 = acc */</span>
<a name="l00285"></a>00285 Xn2 = Xn1;
<a name="l00286"></a>00286 Xn1 = Xn;
<a name="l00287"></a>00287
<a name="l00288"></a>00288 <span class="comment">/* decrement the loop counter */</span>
<a name="l00289"></a>00289 sample--;
<a name="l00290"></a>00290
<a name="l00291"></a>00291 }
<a name="l00292"></a>00292
<a name="l00293"></a>00293 <span class="comment">/* If the blockSize is not a multiple of 4, compute any remaining output samples here. </span>
<a name="l00294"></a>00294 <span class="comment"> ** No loop unrolling is used. */</span>
<a name="l00295"></a>00295 sample = blockSize &amp; 0x3u;
<a name="l00296"></a>00296
<a name="l00297"></a>00297 <span class="keywordflow">while</span>(sample &gt; 0u)
<a name="l00298"></a>00298 {
<a name="l00299"></a>00299 <span class="comment">/* Read the input */</span>
<a name="l00300"></a>00300 Xn = *pIn++;
<a name="l00301"></a>00301
<a name="l00302"></a>00302 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00303"></a>00303 acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
<a name="l00304"></a>00304
<a name="l00305"></a>00305 <span class="comment">/* Store the result in the accumulator in the destination buffer. */</span>
<a name="l00306"></a>00306 *pOut++ = acc;
<a name="l00307"></a>00307
<a name="l00308"></a>00308 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00309"></a>00309 <span class="comment">/* The states should be updated as: */</span>
<a name="l00310"></a>00310 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00311"></a>00311 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00312"></a>00312 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00313"></a>00313 <span class="comment">/* Yn1 = acc */</span>
<a name="l00314"></a>00314 Xn2 = Xn1;
<a name="l00315"></a>00315 Xn1 = Xn;
<a name="l00316"></a>00316 Yn2 = Yn1;
<a name="l00317"></a>00317 Yn1 = acc;
<a name="l00318"></a>00318
<a name="l00319"></a>00319 <span class="comment">/* decrement the loop counter */</span>
<a name="l00320"></a>00320 sample--;
<a name="l00321"></a>00321
<a name="l00322"></a>00322 }
<a name="l00323"></a>00323
<a name="l00324"></a>00324 <span class="comment">/* Store the updated state variables back into the pState array */</span>
<a name="l00325"></a>00325 *pState++ = Xn1;
<a name="l00326"></a>00326 *pState++ = Xn2;
<a name="l00327"></a>00327 *pState++ = Yn1;
<a name="l00328"></a>00328 *pState++ = Yn2;
<a name="l00329"></a>00329
<a name="l00330"></a>00330 <span class="comment">/* The first stage goes from the input buffer to the output buffer. */</span>
<a name="l00331"></a>00331 <span class="comment">/* Subsequent numStages occur in-place in the output buffer */</span>
<a name="l00332"></a>00332 pIn = pDst;
<a name="l00333"></a>00333
<a name="l00334"></a>00334 <span class="comment">/* Reset the output pointer */</span>
<a name="l00335"></a>00335 pOut = pDst;
<a name="l00336"></a>00336
<a name="l00337"></a>00337 <span class="comment">/* decrement the loop counter */</span>
<a name="l00338"></a>00338 stage--;
<a name="l00339"></a>00339
<a name="l00340"></a>00340 } <span class="keywordflow">while</span>(stage &gt; 0u);
<a name="l00341"></a>00341
<a name="l00342"></a>00342 <span class="preprocessor">#else</span>
<a name="l00343"></a>00343 <span class="preprocessor"></span>
<a name="l00344"></a>00344 <span class="comment">/* Run the below code for Cortex-M0 */</span>
<a name="l00345"></a>00345
<a name="l00346"></a>00346 <span class="keywordflow">do</span>
<a name="l00347"></a>00347 {
<a name="l00348"></a>00348 <span class="comment">/* Reading the coefficients */</span>
<a name="l00349"></a>00349 b0 = *pCoeffs++;
<a name="l00350"></a>00350 b1 = *pCoeffs++;
<a name="l00351"></a>00351 b2 = *pCoeffs++;
<a name="l00352"></a>00352 a1 = *pCoeffs++;
<a name="l00353"></a>00353 a2 = *pCoeffs++;
<a name="l00354"></a>00354
<a name="l00355"></a>00355 <span class="comment">/* Reading the pState values */</span>
<a name="l00356"></a>00356 Xn1 = pState[0];
<a name="l00357"></a>00357 Xn2 = pState[1];
<a name="l00358"></a>00358 Yn1 = pState[2];
<a name="l00359"></a>00359 Yn2 = pState[3];
<a name="l00360"></a>00360
<a name="l00361"></a>00361 <span class="comment">/* The variables acc holds the output value that is computed: </span>
<a name="l00362"></a>00362 <span class="comment"> * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] </span>
<a name="l00363"></a>00363 <span class="comment"> */</span>
<a name="l00364"></a>00364
<a name="l00365"></a>00365 sample = <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>;
<a name="l00366"></a>00366
<a name="l00367"></a>00367 <span class="keywordflow">while</span>(sample &gt; 0u)
<a name="l00368"></a>00368 {
<a name="l00369"></a>00369 <span class="comment">/* Read the input */</span>
<a name="l00370"></a>00370 Xn = *pIn++;
<a name="l00371"></a>00371
<a name="l00372"></a>00372 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00373"></a>00373 acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
<a name="l00374"></a>00374
<a name="l00375"></a>00375 <span class="comment">/* Store the result in the accumulator in the destination buffer. */</span>
<a name="l00376"></a>00376 *pOut++ = acc;
<a name="l00377"></a>00377
<a name="l00378"></a>00378 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00379"></a>00379 <span class="comment">/* The states should be updated as: */</span>
<a name="l00380"></a>00380 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00381"></a>00381 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00382"></a>00382 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00383"></a>00383 <span class="comment">/* Yn1 = acc */</span>
<a name="l00384"></a>00384 Xn2 = Xn1;
<a name="l00385"></a>00385 Xn1 = Xn;
<a name="l00386"></a>00386 Yn2 = Yn1;
<a name="l00387"></a>00387 Yn1 = acc;
<a name="l00388"></a>00388
<a name="l00389"></a>00389 <span class="comment">/* decrement the loop counter */</span>
<a name="l00390"></a>00390 sample--;
<a name="l00391"></a>00391 }
<a name="l00392"></a>00392
<a name="l00393"></a>00393 <span class="comment">/* Store the updated state variables back into the pState array */</span>
<a name="l00394"></a>00394 *pState++ = Xn1;
<a name="l00395"></a>00395 *pState++ = Xn2;
<a name="l00396"></a>00396 *pState++ = Yn1;
<a name="l00397"></a>00397 *pState++ = Yn2;
<a name="l00398"></a>00398
<a name="l00399"></a>00399 <span class="comment">/* The first stage goes from the input buffer to the output buffer. */</span>
<a name="l00400"></a>00400 <span class="comment">/* Subsequent numStages occur in-place in the output buffer */</span>
<a name="l00401"></a>00401 pIn = pDst;
<a name="l00402"></a>00402
<a name="l00403"></a>00403 <span class="comment">/* Reset the output pointer */</span>
<a name="l00404"></a>00404 pOut = pDst;
<a name="l00405"></a>00405
<a name="l00406"></a>00406 <span class="comment">/* decrement the loop counter */</span>
<a name="l00407"></a>00407 stage--;
<a name="l00408"></a>00408
<a name="l00409"></a>00409 } <span class="keywordflow">while</span>(stage &gt; 0u);
<a name="l00410"></a>00410
<a name="l00411"></a>00411 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_CM0 */</span>
<a name="l00412"></a>00412
<a name="l00413"></a>00413 }
<a name="l00414"></a>00414
<a name="l00415"></a>00415
</pre></div></div>
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<h1>arm_biquad_cascade_df1_fast_q15.c File Reference</h1> </div>
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
<p><a href="arm__biquad__cascade__df1__fast__q15_8c_source.html">Go to the source code of this file.</a></p>
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Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___biquad_cascade_d_f1.html#gaffb9792c0220882efd4c58f3c6a05fd7">arm_biquad_cascade_df1_fast_q15</a> (const <a class="el" href="structarm__biquad__casd__df1__inst__q15.html">arm_biquad_casd_df1_inst_q15</a> *S, <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> *pSrc, <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> *pDst, uint32_t <a class="el" href="arm__variance__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)</td></tr>
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<h1>arm_biquad_cascade_df1_fast_q15.c</h1> </div>
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<a href="arm__biquad__cascade__df1__fast__q15_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ---------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_biquad_cascade_df1_fast_q15.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: Fast processing function for the </span>
<a name="l00011"></a>00011 <span class="comment">* Q15 Biquad cascade filter. </span>
<a name="l00012"></a>00012 <span class="comment">* </span>
<a name="l00013"></a>00013 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3</span>
<a name="l00014"></a>00014 <span class="comment">* </span>
<a name="l00015"></a>00015 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00016"></a>00016 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00017"></a>00017 <span class="comment">* </span>
<a name="l00018"></a>00018 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00019"></a>00019 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00020"></a>00020 <span class="comment">* </span>
<a name="l00021"></a>00021 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00022"></a>00022 <span class="comment">* Documentation updated. </span>
<a name="l00023"></a>00023 <span class="comment">* </span>
<a name="l00024"></a>00024 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00025"></a>00025 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00026"></a>00026 <span class="comment">* </span>
<a name="l00027"></a>00027 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00028"></a>00028 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00029"></a>00029 <span class="comment">* </span>
<a name="l00030"></a>00030 <span class="comment">* Version 0.0.9 2010/08/16 </span>
<a name="l00031"></a>00031 <span class="comment">* Initial version </span>
<a name="l00032"></a>00032 <span class="comment">* </span>
<a name="l00033"></a>00033 <span class="comment">* </span>
<a name="l00034"></a>00034 <span class="comment">* -------------------------------------------------------------------- */</span>
<a name="l00035"></a>00035
<a name="l00036"></a>00036 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00037"></a>00037
<a name="l00069"></a><a class="code" href="group___biquad_cascade_d_f1.html#gaffb9792c0220882efd4c58f3c6a05fd7">00069</a> <span class="keywordtype">void</span> <a class="code" href="group___biquad_cascade_d_f1.html#gaffb9792c0220882efd4c58f3c6a05fd7" title="Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-...">arm_biquad_cascade_df1_fast_q15</a>(
<a name="l00070"></a>00070 <span class="keyword">const</span> <a class="code" href="structarm__biquad__casd__df1__inst__q15.html" title="Instance structure for the Q15 Biquad cascade filter.">arm_biquad_casd_df1_inst_q15</a> * S,
<a name="l00071"></a>00071 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> * pSrc,
<a name="l00072"></a>00072 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> * pDst,
<a name="l00073"></a>00073 uint32_t <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)
<a name="l00074"></a>00074 {
<a name="l00075"></a>00075 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> *pIn = pSrc; <span class="comment">/* Source pointer */</span>
<a name="l00076"></a>00076 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> *pOut = pDst; <span class="comment">/* Destination pointer */</span>
<a name="l00077"></a>00077 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> in; <span class="comment">/* Temporary variable to hold input value */</span>
<a name="l00078"></a>00078 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> out; <span class="comment">/* Temporary variable to hold output value */</span>
<a name="l00079"></a>00079 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> b0; <span class="comment">/* Temporary variable to hold bo value */</span>
<a name="l00080"></a>00080 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> b1, a1; <span class="comment">/* Filter coefficients */</span>
<a name="l00081"></a>00081 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> state_in, state_out; <span class="comment">/* Filter state variables */</span>
<a name="l00082"></a>00082 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> acc0; <span class="comment">/* Accumulator */</span>
<a name="l00083"></a>00083 int32_t shift = (int32_t) (15 - S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q15.html#ada7e9d6269e6ed4eacf8f68729e9832d">postShift</a>); <span class="comment">/* Post shift */</span>
<a name="l00084"></a>00084 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> *pState = S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q15.html#a5481104ef2f8f81360b80b47d69ae932">pState</a>; <span class="comment">/* State pointer */</span>
<a name="l00085"></a>00085 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> *pCoeffs = S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q15.html#a1edaacdebb5b09d7635bf20c779855fc">pCoeffs</a>; <span class="comment">/* Coefficient pointer */</span>
<a name="l00086"></a>00086 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> *pState_q31; <span class="comment">/* 32-bit state pointer for SIMD implementation */</span>
<a name="l00087"></a>00087 uint32_t sample, stage = S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q15.html#ad6d95e70abcf4ff1300181415ad92153">numStages</a>; <span class="comment">/* Stage loop counter */</span>
<a name="l00088"></a>00088
<a name="l00089"></a>00089
<a name="l00090"></a>00090
<a name="l00091"></a>00091 <span class="keywordflow">do</span>
<a name="l00092"></a>00092 {
<a name="l00093"></a>00093 <span class="comment">/* Initialize state pointer of type q31 */</span>
<a name="l00094"></a>00094 pState_q31 = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> *) (pState);
<a name="l00095"></a>00095
<a name="l00096"></a>00096 <span class="comment">/* Read the b0 and 0 coefficients using SIMD */</span>
<a name="l00097"></a>00097 b0 = *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pCoeffs)++;
<a name="l00098"></a>00098
<a name="l00099"></a>00099 <span class="comment">/* Read the b1 and b2 coefficients using SIMD */</span>
<a name="l00100"></a>00100 b1 = *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pCoeffs)++;
<a name="l00101"></a>00101
<a name="l00102"></a>00102 <span class="comment">/* Read the a1 and a2 coefficients using SIMD */</span>
<a name="l00103"></a>00103 a1 = *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pCoeffs)++;
<a name="l00104"></a>00104
<a name="l00105"></a>00105 <span class="comment">/* Read the input state values from the state buffer: x[n-1], x[n-2] */</span>
<a name="l00106"></a>00106 state_in = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) (*pState_q31++);
<a name="l00107"></a>00107
<a name="l00108"></a>00108 <span class="comment">/* Read the output state values from the state buffer: y[n-1], y[n-2] */</span>
<a name="l00109"></a>00109 state_out = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) (*pState_q31);
<a name="l00110"></a>00110
<a name="l00111"></a>00111 <span class="comment">/* Apply loop unrolling and compute 2 output values simultaneously. */</span>
<a name="l00112"></a>00112 <span class="comment">/* The variables acc0 ... acc3 hold output values that are being computed: </span>
<a name="l00113"></a>00113 <span class="comment"> * </span>
<a name="l00114"></a>00114 <span class="comment"> * acc0 = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] </span>
<a name="l00115"></a>00115 <span class="comment"> * acc0 = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] </span>
<a name="l00116"></a>00116 <span class="comment"> */</span>
<a name="l00117"></a>00117 sample = blockSize &gt;&gt; 1u;
<a name="l00118"></a>00118
<a name="l00119"></a>00119 <span class="comment">/* First part of the processing with loop unrolling. Compute 2 outputs at a time. </span>
<a name="l00120"></a>00120 <span class="comment"> ** a second loop below computes the remaining 1 sample. */</span>
<a name="l00121"></a>00121 <span class="keywordflow">while</span>(sample &gt; 0u)
<a name="l00122"></a>00122 {
<a name="l00123"></a>00123
<a name="l00124"></a>00124 <span class="comment">/* Read the input */</span>
<a name="l00125"></a>00125 in = *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pIn)++;
<a name="l00126"></a>00126
<a name="l00127"></a>00127 <span class="comment">/* out = b0 * x[n] + 0 * 0 */</span>
<a name="l00128"></a>00128 out = __SMUAD(b0, in);
<a name="l00129"></a>00129 <span class="comment">/* acc0 = b1 * x[n-1] + acc0 += b2 * x[n-2] + out */</span>
<a name="l00130"></a>00130 acc0 = __SMLAD(b1, state_in, out);
<a name="l00131"></a>00131 <span class="comment">/* acc0 += a1 * y[n-1] + acc0 += a2 * y[n-2] */</span>
<a name="l00132"></a>00132 acc0 = __SMLAD(a1, state_out, acc0);
<a name="l00133"></a>00133
<a name="l00134"></a>00134 <span class="comment">/* The result is converted from 3.29 to 1.31 and then saturation is applied */</span>
<a name="l00135"></a>00135 out = __SSAT((acc0 &gt;&gt; shift), 16);
<a name="l00136"></a>00136
<a name="l00137"></a>00137 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00138"></a>00138 <span class="comment">/* The states should be updated as: */</span>
<a name="l00139"></a>00139 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00140"></a>00140 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00141"></a>00141 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00142"></a>00142 <span class="comment">/* Yn1 = acc0 */</span>
<a name="l00143"></a>00143 <span class="comment">/* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */</span>
<a name="l00144"></a>00144 <span class="comment">/* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */</span>
<a name="l00145"></a>00145
<a name="l00146"></a>00146 <span class="preprocessor">#ifndef ARM_MATH_BIG_ENDIAN</span>
<a name="l00147"></a>00147 <span class="preprocessor"></span>
<a name="l00148"></a>00148 state_in = __PKHBT(in, state_in, 16);
<a name="l00149"></a>00149 state_out = __PKHBT(out, state_out, 16);
<a name="l00150"></a>00150
<a name="l00151"></a>00151 <span class="preprocessor">#else</span>
<a name="l00152"></a>00152 <span class="preprocessor"></span>
<a name="l00153"></a>00153 state_in = __PKHBT(state_in &gt;&gt; 16, (in &gt;&gt; 16), 16);
<a name="l00154"></a>00154 state_out = __PKHBT(state_out &gt;&gt; 16, (out), 16);
<a name="l00155"></a>00155
<a name="l00156"></a>00156 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_BIG_ENDIAN */</span>
<a name="l00157"></a>00157
<a name="l00158"></a>00158 <span class="comment">/* out = b0 * x[n] + 0 * 0 */</span>
<a name="l00159"></a>00159 out = __SMUADX(b0, in);
<a name="l00160"></a>00160 <span class="comment">/* acc0 = b1 * x[n-1] + acc0 += b2 * x[n-2] + out */</span>
<a name="l00161"></a>00161 acc0 = __SMLAD(b1, state_in, out);
<a name="l00162"></a>00162 <span class="comment">/* acc0 += a1 * y[n-1] + acc0 += a2 * y[n-2] */</span>
<a name="l00163"></a>00163 acc0 = __SMLAD(a1, state_out, acc0);
<a name="l00164"></a>00164
<a name="l00165"></a>00165 <span class="comment">/* The result is converted from 3.29 to 1.31 and then saturation is applied */</span>
<a name="l00166"></a>00166 out = __SSAT((acc0 &gt;&gt; shift), 16);
<a name="l00167"></a>00167
<a name="l00168"></a>00168
<a name="l00169"></a>00169 <span class="comment">/* Store the output in the destination buffer. */</span>
<a name="l00170"></a>00170
<a name="l00171"></a>00171 <span class="preprocessor">#ifndef ARM_MATH_BIG_ENDIAN</span>
<a name="l00172"></a>00172 <span class="preprocessor"></span>
<a name="l00173"></a>00173 *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pOut)++ = __PKHBT(state_out, out, 16);
<a name="l00174"></a>00174
<a name="l00175"></a>00175 <span class="preprocessor">#else</span>
<a name="l00176"></a>00176 <span class="preprocessor"></span>
<a name="l00177"></a>00177 *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pOut)++ = __PKHBT(out, state_out &gt;&gt; 16, 16);
<a name="l00178"></a>00178
<a name="l00179"></a>00179 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_BIG_ENDIAN */</span>
<a name="l00180"></a>00180
<a name="l00181"></a>00181 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00182"></a>00182 <span class="comment">/* The states should be updated as: */</span>
<a name="l00183"></a>00183 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00184"></a>00184 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00185"></a>00185 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00186"></a>00186 <span class="comment">/* Yn1 = acc0 */</span>
<a name="l00187"></a>00187 <span class="comment">/* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */</span>
<a name="l00188"></a>00188 <span class="comment">/* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */</span>
<a name="l00189"></a>00189
<a name="l00190"></a>00190 <span class="preprocessor">#ifndef ARM_MATH_BIG_ENDIAN</span>
<a name="l00191"></a>00191 <span class="preprocessor"></span>
<a name="l00192"></a>00192 state_in = __PKHBT(in &gt;&gt; 16, state_in, 16);
<a name="l00193"></a>00193 state_out = __PKHBT(out, state_out, 16);
<a name="l00194"></a>00194
<a name="l00195"></a>00195 <span class="preprocessor">#else</span>
<a name="l00196"></a>00196 <span class="preprocessor"></span>
<a name="l00197"></a>00197 state_in = __PKHBT(state_in &gt;&gt; 16, in, 16);
<a name="l00198"></a>00198 state_out = __PKHBT(state_out &gt;&gt; 16, out, 16);
<a name="l00199"></a>00199
<a name="l00200"></a>00200 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_BIG_ENDIAN */</span>
<a name="l00201"></a>00201
<a name="l00202"></a>00202
<a name="l00203"></a>00203 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00204"></a>00204 sample--;
<a name="l00205"></a>00205
<a name="l00206"></a>00206 }
<a name="l00207"></a>00207
<a name="l00208"></a>00208 <span class="comment">/* If the blockSize is not a multiple of 2, compute any remaining output samples here. </span>
<a name="l00209"></a>00209 <span class="comment"> ** No loop unrolling is used. */</span>
<a name="l00210"></a>00210
<a name="l00211"></a>00211 <span class="keywordflow">if</span>((blockSize &amp; 0x1u) != 0u)
<a name="l00212"></a>00212 {
<a name="l00213"></a>00213 <span class="comment">/* Read the input */</span>
<a name="l00214"></a>00214 in = *pIn++;
<a name="l00215"></a>00215
<a name="l00216"></a>00216 <span class="comment">/* out = b0 * x[n] + 0 * 0 */</span>
<a name="l00217"></a>00217
<a name="l00218"></a>00218 <span class="preprocessor">#ifndef ARM_MATH_BIG_ENDIAN</span>
<a name="l00219"></a>00219 <span class="preprocessor"></span>
<a name="l00220"></a>00220 out = __SMUAD(b0, in);
<a name="l00221"></a>00221
<a name="l00222"></a>00222 <span class="preprocessor">#else</span>
<a name="l00223"></a>00223 <span class="preprocessor"></span>
<a name="l00224"></a>00224 out = __SMUADX(b0, in);
<a name="l00225"></a>00225
<a name="l00226"></a>00226 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_BIG_ENDIAN */</span>
<a name="l00227"></a>00227
<a name="l00228"></a>00228 <span class="comment">/* acc0 = b1 * x[n-1] + acc0 += b2 * x[n-2] + out */</span>
<a name="l00229"></a>00229 acc0 = __SMLAD(b1, state_in, out);
<a name="l00230"></a>00230 <span class="comment">/* acc0 += a1 * y[n-1] + acc0 += a2 * y[n-2] */</span>
<a name="l00231"></a>00231 acc0 = __SMLAD(a1, state_out, acc0);
<a name="l00232"></a>00232
<a name="l00233"></a>00233 <span class="comment">/* The result is converted from 3.29 to 1.31 and then saturation is applied */</span>
<a name="l00234"></a>00234 out = __SSAT((acc0 &gt;&gt; shift), 16);
<a name="l00235"></a>00235
<a name="l00236"></a>00236 <span class="comment">/* Store the output in the destination buffer. */</span>
<a name="l00237"></a>00237 *pOut++ = (<a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a>) out;
<a name="l00238"></a>00238
<a name="l00239"></a>00239 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00240"></a>00240 <span class="comment">/* The states should be updated as: */</span>
<a name="l00241"></a>00241 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00242"></a>00242 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00243"></a>00243 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00244"></a>00244 <span class="comment">/* Yn1 = acc0 */</span>
<a name="l00245"></a>00245 <span class="comment">/* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */</span>
<a name="l00246"></a>00246 <span class="comment">/* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */</span>
<a name="l00247"></a>00247
<a name="l00248"></a>00248 <span class="preprocessor">#ifndef ARM_MATH_BIG_ENDIAN</span>
<a name="l00249"></a>00249 <span class="preprocessor"></span>
<a name="l00250"></a>00250 state_in = __PKHBT(in, state_in, 16);
<a name="l00251"></a>00251 state_out = __PKHBT(out, state_out, 16);
<a name="l00252"></a>00252
<a name="l00253"></a>00253 <span class="preprocessor">#else</span>
<a name="l00254"></a>00254 <span class="preprocessor"></span>
<a name="l00255"></a>00255 state_in = __PKHBT(state_in &gt;&gt; 16, in, 16);
<a name="l00256"></a>00256 state_out = __PKHBT(state_out &gt;&gt; 16, out, 16);
<a name="l00257"></a>00257
<a name="l00258"></a>00258 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_BIG_ENDIAN */</span>
<a name="l00259"></a>00259
<a name="l00260"></a>00260 }
<a name="l00261"></a>00261
<a name="l00262"></a>00262 <span class="comment">/* The first stage goes from the input buffer to the output buffer. */</span>
<a name="l00263"></a>00263 <span class="comment">/* Subsequent (numStages - 1) occur in-place in the output buffer */</span>
<a name="l00264"></a>00264 pIn = pDst;
<a name="l00265"></a>00265
<a name="l00266"></a>00266 <span class="comment">/* Reset the output pointer */</span>
<a name="l00267"></a>00267 pOut = pDst;
<a name="l00268"></a>00268
<a name="l00269"></a>00269 <span class="comment">/* Store the updated state variables back into the state array */</span>
<a name="l00270"></a>00270 *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pState)++ = state_in;
<a name="l00271"></a>00271 *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pState)++ = state_out;
<a name="l00272"></a>00272
<a name="l00273"></a>00273
<a name="l00274"></a>00274 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00275"></a>00275 stage--;
<a name="l00276"></a>00276
<a name="l00277"></a>00277 } <span class="keywordflow">while</span>(stage &gt; 0u);
<a name="l00278"></a>00278 }
<a name="l00279"></a>00279
<a name="l00280"></a>00280
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
<p><a href="arm__biquad__cascade__df1__fast__q31_8c_source.html">Go to the source code of this file.</a></p>
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Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___biquad_cascade_d_f1.html#ga456390f5e448afad3a38bed7d6e380e3">arm_biquad_cascade_df1_fast_q31</a> (const <a class="el" href="structarm__biquad__casd__df1__inst__q31.html">arm_biquad_casd_df1_inst_q31</a> *S, <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> *pSrc, <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> *pDst, uint32_t <a class="el" href="arm__variance__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)</td></tr>
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<a href="arm__biquad__cascade__df1__fast__q31_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ---------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_biquad_cascade_df1_fast_q31.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: Processing function for the </span>
<a name="l00011"></a>00011 <span class="comment">* Q31 Fast Biquad cascade DirectFormI(DF1) filter. </span>
<a name="l00012"></a>00012 <span class="comment">* </span>
<a name="l00013"></a>00013 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3</span>
<a name="l00014"></a>00014 <span class="comment">* </span>
<a name="l00015"></a>00015 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00016"></a>00016 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00017"></a>00017 <span class="comment">* </span>
<a name="l00018"></a>00018 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00019"></a>00019 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00020"></a>00020 <span class="comment">* </span>
<a name="l00021"></a>00021 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00022"></a>00022 <span class="comment">* Documentation updated. </span>
<a name="l00023"></a>00023 <span class="comment">* </span>
<a name="l00024"></a>00024 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00025"></a>00025 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00026"></a>00026 <span class="comment">* </span>
<a name="l00027"></a>00027 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00028"></a>00028 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00029"></a>00029 <span class="comment">* </span>
<a name="l00030"></a>00030 <span class="comment">* Version 0.0.9 2010/08/27 </span>
<a name="l00031"></a>00031 <span class="comment">* Initial version </span>
<a name="l00032"></a>00032 <span class="comment">* </span>
<a name="l00033"></a>00033 <span class="comment">* -------------------------------------------------------------------- */</span>
<a name="l00034"></a>00034
<a name="l00035"></a>00035 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00036"></a>00036
<a name="l00070"></a><a class="code" href="group___biquad_cascade_d_f1.html#ga456390f5e448afad3a38bed7d6e380e3">00070</a> <span class="keywordtype">void</span> <a class="code" href="group___biquad_cascade_d_f1.html#ga456390f5e448afad3a38bed7d6e380e3" title="Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-...">arm_biquad_cascade_df1_fast_q31</a>(
<a name="l00071"></a>00071 <span class="keyword">const</span> <a class="code" href="structarm__biquad__casd__df1__inst__q31.html" title="Instance structure for the Q31 Biquad cascade filter.">arm_biquad_casd_df1_inst_q31</a> * S,
<a name="l00072"></a>00072 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> * pSrc,
<a name="l00073"></a>00073 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> * pDst,
<a name="l00074"></a>00074 uint32_t <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)
<a name="l00075"></a>00075 {
<a name="l00076"></a>00076 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> *pIn = pSrc; <span class="comment">/* input pointer initialization */</span>
<a name="l00077"></a>00077 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> *pOut = pDst; <span class="comment">/* output pointer initialization */</span>
<a name="l00078"></a>00078 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> *pState = S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q31.html#a5dcf4727f58eb4e8e8b392508d8657bb">pState</a>; <span class="comment">/* pState pointer initialization */</span>
<a name="l00079"></a>00079 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> *pCoeffs = S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q31.html#aa62366c632f3b5305086f841f079dbd2">pCoeffs</a>; <span class="comment">/* coeff pointer initialization */</span>
<a name="l00080"></a>00080 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> acc; <span class="comment">/* accumulator */</span>
<a name="l00081"></a>00081 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> Xn1, Xn2, Yn1, Yn2; <span class="comment">/* Filter state variables */</span>
<a name="l00082"></a>00082 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> b0, b1, b2, a1, a2; <span class="comment">/* Filter coefficients */</span>
<a name="l00083"></a>00083 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> Xn; <span class="comment">/* temporary input */</span>
<a name="l00084"></a>00084 int32_t shift = (int32_t) S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q31.html#a636c7fbe09ec4bef0bc0a4b4e2151cbe">postShift</a> + 1; <span class="comment">/* Shift to be applied to the output */</span>
<a name="l00085"></a>00085 uint32_t sample, stage = S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q31.html#a2c2b579f1df1d8273a5d9d945c27e1b2">numStages</a>; <span class="comment">/* loop counters */</span>
<a name="l00086"></a>00086
<a name="l00087"></a>00087
<a name="l00088"></a>00088 <span class="keywordflow">do</span>
<a name="l00089"></a>00089 {
<a name="l00090"></a>00090 <span class="comment">/* Reading the coefficients */</span>
<a name="l00091"></a>00091 b0 = *pCoeffs++;
<a name="l00092"></a>00092 b1 = *pCoeffs++;
<a name="l00093"></a>00093 b2 = *pCoeffs++;
<a name="l00094"></a>00094 a1 = *pCoeffs++;
<a name="l00095"></a>00095 a2 = *pCoeffs++;
<a name="l00096"></a>00096
<a name="l00097"></a>00097 <span class="comment">/* Reading the state values */</span>
<a name="l00098"></a>00098 Xn1 = pState[0];
<a name="l00099"></a>00099 Xn2 = pState[1];
<a name="l00100"></a>00100 Yn1 = pState[2];
<a name="l00101"></a>00101 Yn2 = pState[3];
<a name="l00102"></a>00102
<a name="l00103"></a>00103 <span class="comment">/* Apply loop unrolling and compute 4 output values simultaneously. */</span>
<a name="l00104"></a>00104 <span class="comment">/* The variables acc ... acc3 hold output values that are being computed: </span>
<a name="l00105"></a>00105 <span class="comment"> * </span>
<a name="l00106"></a>00106 <span class="comment"> * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] </span>
<a name="l00107"></a>00107 <span class="comment"> */</span>
<a name="l00108"></a>00108
<a name="l00109"></a>00109 sample = blockSize &gt;&gt; 2u;
<a name="l00110"></a>00110
<a name="l00111"></a>00111 <span class="comment">/* First part of the processing with loop unrolling. Compute 4 outputs at a time. </span>
<a name="l00112"></a>00112 <span class="comment"> ** a second loop below computes the remaining 1 to 3 samples. */</span>
<a name="l00113"></a>00113 <span class="keywordflow">while</span>(sample &gt; 0u)
<a name="l00114"></a>00114 {
<a name="l00115"></a>00115 <span class="comment">/* Read the input */</span>
<a name="l00116"></a>00116 Xn = *pIn++;
<a name="l00117"></a>00117
<a name="l00118"></a>00118 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00119"></a>00119 <span class="comment">/* acc = b0 * x[n] */</span>
<a name="l00120"></a>00120 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) (((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b0 * Xn) &gt;&gt; 32);
<a name="l00121"></a>00121 <span class="comment">/* acc += b1 * x[n-1] */</span>
<a name="l00122"></a>00122 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((q63_t) b1 * (Xn1))) &gt;&gt; 32);
<a name="l00123"></a>00123 <span class="comment">/* acc += b[2] * x[n-2] */</span>
<a name="l00124"></a>00124 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b2 * (Xn2))) &gt;&gt; 32);
<a name="l00125"></a>00125 <span class="comment">/* acc += a1 * y[n-1] */</span>
<a name="l00126"></a>00126 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((q63_t) a1 * (Yn1))) &gt;&gt; 32);
<a name="l00127"></a>00127 <span class="comment">/* acc += a2 * y[n-2] */</span>
<a name="l00128"></a>00128 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((q63_t) a2 * (Yn2))) &gt;&gt; 32);
<a name="l00129"></a>00129
<a name="l00130"></a>00130 <span class="comment">/* The result is converted to 1.31 , Yn2 variable is reused */</span>
<a name="l00131"></a>00131 Yn2 = acc &lt;&lt; shift;
<a name="l00132"></a>00132
<a name="l00133"></a>00133 <span class="comment">/* Store the output in the destination buffer. */</span>
<a name="l00134"></a>00134 *pOut++ = Yn2;
<a name="l00135"></a>00135
<a name="l00136"></a>00136 <span class="comment">/* Read the second input */</span>
<a name="l00137"></a>00137 Xn2 = *pIn++;
<a name="l00138"></a>00138
<a name="l00139"></a>00139 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00140"></a>00140 <span class="comment">/* acc = b0 * x[n] */</span>
<a name="l00141"></a>00141 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) (((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b0 * (Xn2)) &gt;&gt; 32);
<a name="l00142"></a>00142 <span class="comment">/* acc += b1 * x[n-1] */</span>
<a name="l00143"></a>00143 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((q63_t) b1 * (Xn))) &gt;&gt; 32);
<a name="l00144"></a>00144 <span class="comment">/* acc += b[2] * x[n-2] */</span>
<a name="l00145"></a>00145 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((q63_t) b2 * (Xn1))) &gt;&gt; 32);
<a name="l00146"></a>00146 <span class="comment">/* acc += a1 * y[n-1] */</span>
<a name="l00147"></a>00147 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((q63_t) a1 * (Yn2))) &gt;&gt; 32);
<a name="l00148"></a>00148 <span class="comment">/* acc += a2 * y[n-2] */</span>
<a name="l00149"></a>00149 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) a2 * (Yn1))) &gt;&gt; 32);
<a name="l00150"></a>00150
<a name="l00151"></a>00151 <span class="comment">/* The result is converted to 1.31, Yn1 variable is reused */</span>
<a name="l00152"></a>00152 Yn1 = acc &lt;&lt; shift;
<a name="l00153"></a>00153
<a name="l00154"></a>00154 <span class="comment">/* Store the output in the destination buffer. */</span>
<a name="l00155"></a>00155 *pOut++ = Yn1;
<a name="l00156"></a>00156
<a name="l00157"></a>00157 <span class="comment">/* Read the third input */</span>
<a name="l00158"></a>00158 Xn1 = *pIn++;
<a name="l00159"></a>00159
<a name="l00160"></a>00160 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00161"></a>00161 <span class="comment">/* acc = b0 * x[n] */</span>
<a name="l00162"></a>00162 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) (((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b0 * (Xn1)) &gt;&gt; 32);
<a name="l00163"></a>00163 <span class="comment">/* acc += b1 * x[n-1] */</span>
<a name="l00164"></a>00164 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((q63_t) b1 * (Xn2))) &gt;&gt; 32);
<a name="l00165"></a>00165 <span class="comment">/* acc += b[2] * x[n-2] */</span>
<a name="l00166"></a>00166 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((q63_t) b2 * (Xn))) &gt;&gt; 32);
<a name="l00167"></a>00167 <span class="comment">/* acc += a1 * y[n-1] */</span>
<a name="l00168"></a>00168 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((q63_t) a1 * (Yn1))) &gt;&gt; 32);
<a name="l00169"></a>00169 <span class="comment">/* acc += a2 * y[n-2] */</span>
<a name="l00170"></a>00170 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((q63_t) a2 * (Yn2))) &gt;&gt; 32);
<a name="l00171"></a>00171
<a name="l00172"></a>00172 <span class="comment">/* The result is converted to 1.31, Yn2 variable is reused */</span>
<a name="l00173"></a>00173 Yn2 = acc &lt;&lt; shift;
<a name="l00174"></a>00174
<a name="l00175"></a>00175 <span class="comment">/* Store the output in the destination buffer. */</span>
<a name="l00176"></a>00176 *pOut++ = Yn2;
<a name="l00177"></a>00177
<a name="l00178"></a>00178 <span class="comment">/* Read the forth input */</span>
<a name="l00179"></a>00179 Xn = *pIn++;
<a name="l00180"></a>00180
<a name="l00181"></a>00181 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00182"></a>00182 <span class="comment">/* acc = b0 * x[n] */</span>
<a name="l00183"></a>00183 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) (((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b0 * (Xn)) &gt;&gt; 32);
<a name="l00184"></a>00184 <span class="comment">/* acc += b1 * x[n-1] */</span>
<a name="l00185"></a>00185 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((q63_t) b1 * (Xn1))) &gt;&gt; 32);
<a name="l00186"></a>00186 <span class="comment">/* acc += b[2] * x[n-2] */</span>
<a name="l00187"></a>00187 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((q63_t) b2 * (Xn2))) &gt;&gt; 32);
<a name="l00188"></a>00188 <span class="comment">/* acc += a1 * y[n-1] */</span>
<a name="l00189"></a>00189 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((q63_t) a1 * (Yn2))) &gt;&gt; 32);
<a name="l00190"></a>00190 <span class="comment">/* acc += a2 * y[n-2] */</span>
<a name="l00191"></a>00191 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) a2 * (Yn1))) &gt;&gt; 32);
<a name="l00192"></a>00192
<a name="l00193"></a>00193 <span class="comment">/* The result is converted to 1.31, Yn1 variable is reused */</span>
<a name="l00194"></a>00194 Yn1 = acc &lt;&lt; shift;
<a name="l00195"></a>00195
<a name="l00196"></a>00196 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00197"></a>00197 <span class="comment">/* The states should be updated as: */</span>
<a name="l00198"></a>00198 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00199"></a>00199 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00200"></a>00200 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00201"></a>00201 <span class="comment">/* Yn1 = acc */</span>
<a name="l00202"></a>00202 Xn2 = Xn1;
<a name="l00203"></a>00203 Xn1 = Xn;
<a name="l00204"></a>00204
<a name="l00205"></a>00205 <span class="comment">/* Store the output in the destination buffer. */</span>
<a name="l00206"></a>00206 *pOut++ = Yn1;
<a name="l00207"></a>00207
<a name="l00208"></a>00208 <span class="comment">/* decrement the loop counter */</span>
<a name="l00209"></a>00209 sample--;
<a name="l00210"></a>00210 }
<a name="l00211"></a>00211
<a name="l00212"></a>00212 <span class="comment">/* If the blockSize is not a multiple of 4, compute any remaining output samples here. </span>
<a name="l00213"></a>00213 <span class="comment"> ** No loop unrolling is used. */</span>
<a name="l00214"></a>00214 sample = (blockSize &amp; 0x3u);
<a name="l00215"></a>00215
<a name="l00216"></a>00216 <span class="keywordflow">while</span>(sample &gt; 0u)
<a name="l00217"></a>00217 {
<a name="l00218"></a>00218 <span class="comment">/* Read the input */</span>
<a name="l00219"></a>00219 Xn = *pIn++;
<a name="l00220"></a>00220
<a name="l00221"></a>00221 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00222"></a>00222 <span class="comment">/* acc = b0 * x[n] */</span>
<a name="l00223"></a>00223 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) (((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b0 * (Xn)) &gt;&gt; 32);
<a name="l00224"></a>00224 <span class="comment">/* acc += b1 * x[n-1] */</span>
<a name="l00225"></a>00225 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((q63_t) b1 * (Xn1))) &gt;&gt; 32);
<a name="l00226"></a>00226 <span class="comment">/* acc += b[2] * x[n-2] */</span>
<a name="l00227"></a>00227 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((q63_t) b2 * (Xn2))) &gt;&gt; 32);
<a name="l00228"></a>00228 <span class="comment">/* acc += a1 * y[n-1] */</span>
<a name="l00229"></a>00229 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((q63_t) a1 * (Yn1))) &gt;&gt; 32);
<a name="l00230"></a>00230 <span class="comment">/* acc += a2 * y[n-2] */</span>
<a name="l00231"></a>00231 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) ((((<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) acc &lt;&lt; 32) + ((q63_t) a2 * (Yn2))) &gt;&gt; 32);
<a name="l00232"></a>00232 <span class="comment">/* The result is converted to 1.31 */</span>
<a name="l00233"></a>00233 acc = acc &lt;&lt; shift;
<a name="l00234"></a>00234
<a name="l00235"></a>00235 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00236"></a>00236 <span class="comment">/* The states should be updated as: */</span>
<a name="l00237"></a>00237 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00238"></a>00238 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00239"></a>00239 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00240"></a>00240 <span class="comment">/* Yn1 = acc */</span>
<a name="l00241"></a>00241 Xn2 = Xn1;
<a name="l00242"></a>00242 Xn1 = Xn;
<a name="l00243"></a>00243 Yn2 = Yn1;
<a name="l00244"></a>00244 Yn1 = acc;
<a name="l00245"></a>00245
<a name="l00246"></a>00246 <span class="comment">/* Store the output in the destination buffer. */</span>
<a name="l00247"></a>00247 *pOut++ = acc;
<a name="l00248"></a>00248
<a name="l00249"></a>00249 <span class="comment">/* decrement the loop counter */</span>
<a name="l00250"></a>00250 sample--;
<a name="l00251"></a>00251 }
<a name="l00252"></a>00252
<a name="l00253"></a>00253 <span class="comment">/* The first stage goes from the input buffer to the output buffer. */</span>
<a name="l00254"></a>00254 <span class="comment">/* Subsequent stages occur in-place in the output buffer */</span>
<a name="l00255"></a>00255 pIn = pDst;
<a name="l00256"></a>00256
<a name="l00257"></a>00257 <span class="comment">/* Reset to destination pointer */</span>
<a name="l00258"></a>00258 pOut = pDst;
<a name="l00259"></a>00259
<a name="l00260"></a>00260 <span class="comment">/* Store the updated state variables back into the pState array */</span>
<a name="l00261"></a>00261 *pState++ = Xn1;
<a name="l00262"></a>00262 *pState++ = Xn2;
<a name="l00263"></a>00263 *pState++ = Yn1;
<a name="l00264"></a>00264 *pState++ = Yn2;
<a name="l00265"></a>00265
<a name="l00266"></a>00266 } <span class="keywordflow">while</span>(--stage);
<a name="l00267"></a>00267 }
<a name="l00268"></a>00268
</pre></div></div>
</div>
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<h1>arm_biquad_cascade_df1_init_f32.c File Reference</h1> </div>
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
<p><a href="arm__biquad__cascade__df1__init__f32_8c_source.html">Go to the source code of this file.</a></p>
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Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___biquad_cascade_d_f1.html#ga8e73b69a788e681a61bccc8959d823c5">arm_biquad_cascade_df1_init_f32</a> (<a class="el" href="structarm__biquad__casd__df1__inst__f32.html">arm_biquad_casd_df1_inst_f32</a> *S, uint8_t numStages, <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> *pCoeffs, <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> *pState)</td></tr>
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<a href="arm__biquad__cascade__df1__init__f32_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/*----------------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_biquad_cascade_df1_init_f32.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: floating-point Biquad cascade DirectFormI(DF1) filter initialization function. </span>
<a name="l00011"></a>00011 <span class="comment">* </span>
<a name="l00012"></a>00012 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0</span>
<a name="l00013"></a>00013 <span class="comment">* </span>
<a name="l00014"></a>00014 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00015"></a>00015 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00016"></a>00016 <span class="comment">* </span>
<a name="l00017"></a>00017 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00018"></a>00018 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00019"></a>00019 <span class="comment">* </span>
<a name="l00020"></a>00020 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00021"></a>00021 <span class="comment">* Documentation updated. </span>
<a name="l00022"></a>00022 <span class="comment">* </span>
<a name="l00023"></a>00023 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00024"></a>00024 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00025"></a>00025 <span class="comment">* </span>
<a name="l00026"></a>00026 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00027"></a>00027 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00028"></a>00028 <span class="comment">* </span>
<a name="l00029"></a>00029 <span class="comment">* Version 0.0.5 2010/04/26 </span>
<a name="l00030"></a>00030 <span class="comment">* incorporated review comments and updated with latest CMSIS layer </span>
<a name="l00031"></a>00031 <span class="comment">* </span>
<a name="l00032"></a>00032 <span class="comment">* Version 0.0.3 2010/03/10 </span>
<a name="l00033"></a>00033 <span class="comment">* Initial version </span>
<a name="l00034"></a>00034 <span class="comment">* ---------------------------------------------------------------------------*/</span>
<a name="l00035"></a>00035
<a name="l00036"></a>00036 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00037"></a>00037
<a name="l00083"></a><a class="code" href="group___biquad_cascade_d_f1.html#ga8e73b69a788e681a61bccc8959d823c5">00083</a> <span class="keywordtype">void</span> <a class="code" href="group___biquad_cascade_d_f1.html#ga8e73b69a788e681a61bccc8959d823c5" title="Initialization function for the floating-point Biquad cascade filter.">arm_biquad_cascade_df1_init_f32</a>(
<a name="l00084"></a>00084 <a class="code" href="structarm__biquad__casd__df1__inst__f32.html" title="Instance structure for the floating-point Biquad cascade filter.">arm_biquad_casd_df1_inst_f32</a> * S,
<a name="l00085"></a>00085 uint8_t numStages,
<a name="l00086"></a>00086 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> * pCoeffs,
<a name="l00087"></a>00087 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> * pState)
<a name="l00088"></a>00088 {
<a name="l00089"></a>00089 <span class="comment">/* Assign filter stages */</span>
<a name="l00090"></a>00090 S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__f32.html#af69820c37a87252c46453e4cfe120585">numStages</a> = numStages;
<a name="l00091"></a>00091
<a name="l00092"></a>00092 <span class="comment">/* Assign coefficient pointer */</span>
<a name="l00093"></a>00093 S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__f32.html#af9df3820576fb921809d1462c9c6d16c">pCoeffs</a> = pCoeffs;
<a name="l00094"></a>00094
<a name="l00095"></a>00095 <span class="comment">/* Clear state buffer and size is always 4 * numStages */</span>
<a name="l00096"></a>00096 memset(pState, 0, (4u * (uint32_t) numStages) * <span class="keyword">sizeof</span>(<a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a>));
<a name="l00097"></a>00097
<a name="l00098"></a>00098 <span class="comment">/* Assign state pointer */</span>
<a name="l00099"></a>00099 S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__f32.html#a8c245d79e0d8cfabc82409d4b54fb682">pState</a> = pState;
<a name="l00100"></a>00100 }
<a name="l00101"></a>00101
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
<p><a href="arm__biquad__cascade__df1__init__q15_8c_source.html">Go to the source code of this file.</a></p>
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Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___biquad_cascade_d_f1.html#gad54c724132f6d742a444eb6df0e9c731">arm_biquad_cascade_df1_init_q15</a> (<a class="el" href="structarm__biquad__casd__df1__inst__q15.html">arm_biquad_casd_df1_inst_q15</a> *S, uint8_t numStages, <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> *pCoeffs, <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> *pState, int8_t postShift)</td></tr>
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<h1>arm_biquad_cascade_df1_init_q15.c</h1> </div>
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<a href="arm__biquad__cascade__df1__init__q15_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/*----------------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_biquad_cascade_df1_init_q15.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: Q15 Biquad cascade DirectFormI(DF1) filter initialization function. </span>
<a name="l00011"></a>00011 <span class="comment">* </span>
<a name="l00012"></a>00012 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0</span>
<a name="l00013"></a>00013 <span class="comment">* </span>
<a name="l00014"></a>00014 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00015"></a>00015 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00016"></a>00016 <span class="comment">* </span>
<a name="l00017"></a>00017 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00018"></a>00018 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00019"></a>00019 <span class="comment">* </span>
<a name="l00020"></a>00020 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00021"></a>00021 <span class="comment">* Documentation updated. </span>
<a name="l00022"></a>00022 <span class="comment">* </span>
<a name="l00023"></a>00023 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00024"></a>00024 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00025"></a>00025 <span class="comment">* </span>
<a name="l00026"></a>00026 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00027"></a>00027 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00028"></a>00028 <span class="comment">* </span>
<a name="l00029"></a>00029 <span class="comment">* Version 0.0.5 2010/04/26 </span>
<a name="l00030"></a>00030 <span class="comment">* incorporated review comments and updated with latest CMSIS layer </span>
<a name="l00031"></a>00031 <span class="comment">* </span>
<a name="l00032"></a>00032 <span class="comment">* Version 0.0.3 2010/03/10 </span>
<a name="l00033"></a>00033 <span class="comment">* Initial version </span>
<a name="l00034"></a>00034 <span class="comment">* ---------------------------------------------------------------------------*/</span>
<a name="l00035"></a>00035
<a name="l00036"></a>00036 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00037"></a>00037
<a name="l00081"></a><a class="code" href="group___biquad_cascade_d_f1.html#gad54c724132f6d742a444eb6df0e9c731">00081</a> <span class="keywordtype">void</span> <a class="code" href="group___biquad_cascade_d_f1.html#gad54c724132f6d742a444eb6df0e9c731" title="Initialization function for the Q15 Biquad cascade filter.">arm_biquad_cascade_df1_init_q15</a>(
<a name="l00082"></a>00082 <a class="code" href="structarm__biquad__casd__df1__inst__q15.html" title="Instance structure for the Q15 Biquad cascade filter.">arm_biquad_casd_df1_inst_q15</a> * S,
<a name="l00083"></a>00083 uint8_t numStages,
<a name="l00084"></a>00084 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> * pCoeffs,
<a name="l00085"></a>00085 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> * pState,
<a name="l00086"></a>00086 int8_t postShift)
<a name="l00087"></a>00087 {
<a name="l00088"></a>00088 <span class="comment">/* Assign filter stages */</span>
<a name="l00089"></a>00089 S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q15.html#ad6d95e70abcf4ff1300181415ad92153">numStages</a> = numStages;
<a name="l00090"></a>00090
<a name="l00091"></a>00091 <span class="comment">/* Assign postShift to be applied to the output */</span>
<a name="l00092"></a>00092 S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q15.html#ada7e9d6269e6ed4eacf8f68729e9832d">postShift</a> = postShift;
<a name="l00093"></a>00093
<a name="l00094"></a>00094 <span class="comment">/* Assign coefficient pointer */</span>
<a name="l00095"></a>00095 S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q15.html#a1edaacdebb5b09d7635bf20c779855fc">pCoeffs</a> = pCoeffs;
<a name="l00096"></a>00096
<a name="l00097"></a>00097 <span class="comment">/* Clear state buffer and size is always 4 * numStages */</span>
<a name="l00098"></a>00098 memset(pState, 0, (4u * (uint32_t) numStages) * <span class="keyword">sizeof</span>(<a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a>));
<a name="l00099"></a>00099
<a name="l00100"></a>00100 <span class="comment">/* Assign state pointer */</span>
<a name="l00101"></a>00101 S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q15.html#a5481104ef2f8f81360b80b47d69ae932">pState</a> = pState;
<a name="l00102"></a>00102 }
<a name="l00103"></a>00103
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
<p><a href="arm__biquad__cascade__df1__init__q31_8c_source.html">Go to the source code of this file.</a></p>
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Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___biquad_cascade_d_f1.html#gaf42a44f9b16d61e636418c83eefe577b">arm_biquad_cascade_df1_init_q31</a> (<a class="el" href="structarm__biquad__casd__df1__inst__q31.html">arm_biquad_casd_df1_inst_q31</a> *S, uint8_t numStages, <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> *pCoeffs, <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> *pState, int8_t postShift)</td></tr>
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<a href="arm__biquad__cascade__df1__init__q31_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ---------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_biquad_cascade_df1_init_q31.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: Q31 Biquad cascade DirectFormI(DF1) filter initialization function. </span>
<a name="l00011"></a>00011 <span class="comment">* </span>
<a name="l00012"></a>00012 <span class="comment">* </span>
<a name="l00013"></a>00013 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0</span>
<a name="l00014"></a>00014 <span class="comment">* </span>
<a name="l00015"></a>00015 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00016"></a>00016 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00017"></a>00017 <span class="comment">* </span>
<a name="l00018"></a>00018 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00019"></a>00019 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00020"></a>00020 <span class="comment">* </span>
<a name="l00021"></a>00021 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00022"></a>00022 <span class="comment">* Documentation updated. </span>
<a name="l00023"></a>00023 <span class="comment">* </span>
<a name="l00024"></a>00024 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00025"></a>00025 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00026"></a>00026 <span class="comment">* </span>
<a name="l00027"></a>00027 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00028"></a>00028 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00029"></a>00029 <span class="comment">* </span>
<a name="l00030"></a>00030 <span class="comment">* Version 0.0.5 2010/04/26 </span>
<a name="l00031"></a>00031 <span class="comment">* incorporated review comments and updated with latest CMSIS layer </span>
<a name="l00032"></a>00032 <span class="comment">* </span>
<a name="l00033"></a>00033 <span class="comment">* Version 0.0.3 2010/03/10 </span>
<a name="l00034"></a>00034 <span class="comment">* Initial version </span>
<a name="l00035"></a>00035 <span class="comment">* -------------------------------------------------------------------- */</span>
<a name="l00036"></a>00036
<a name="l00037"></a>00037 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00038"></a>00038
<a name="l00081"></a><a class="code" href="group___biquad_cascade_d_f1.html#gaf42a44f9b16d61e636418c83eefe577b">00081</a> <span class="keywordtype">void</span> <a class="code" href="group___biquad_cascade_d_f1.html#gaf42a44f9b16d61e636418c83eefe577b" title="Initialization function for the Q31 Biquad cascade filter.">arm_biquad_cascade_df1_init_q31</a>(
<a name="l00082"></a>00082 <a class="code" href="structarm__biquad__casd__df1__inst__q31.html" title="Instance structure for the Q31 Biquad cascade filter.">arm_biquad_casd_df1_inst_q31</a> * S,
<a name="l00083"></a>00083 uint8_t numStages,
<a name="l00084"></a>00084 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> * pCoeffs,
<a name="l00085"></a>00085 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> * pState,
<a name="l00086"></a>00086 int8_t postShift)
<a name="l00087"></a>00087 {
<a name="l00088"></a>00088 <span class="comment">/* Assign filter stages */</span>
<a name="l00089"></a>00089 S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q31.html#a2c2b579f1df1d8273a5d9d945c27e1b2">numStages</a> = numStages;
<a name="l00090"></a>00090
<a name="l00091"></a>00091 <span class="comment">/* Assign postShift to be applied to the output */</span>
<a name="l00092"></a>00092 S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q31.html#a636c7fbe09ec4bef0bc0a4b4e2151cbe">postShift</a> = postShift;
<a name="l00093"></a>00093
<a name="l00094"></a>00094 <span class="comment">/* Assign coefficient pointer */</span>
<a name="l00095"></a>00095 S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q31.html#aa62366c632f3b5305086f841f079dbd2">pCoeffs</a> = pCoeffs;
<a name="l00096"></a>00096
<a name="l00097"></a>00097 <span class="comment">/* Clear state buffer and size is always 4 * numStages */</span>
<a name="l00098"></a>00098 memset(pState, 0, (4u * (uint32_t) numStages) * <span class="keyword">sizeof</span>(<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>));
<a name="l00099"></a>00099
<a name="l00100"></a>00100 <span class="comment">/* Assign state pointer */</span>
<a name="l00101"></a>00101 S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q31.html#a5dcf4727f58eb4e8e8b392508d8657bb">pState</a> = pState;
<a name="l00102"></a>00102 }
<a name="l00103"></a>00103
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
<p><a href="arm__biquad__cascade__df1__q15_8c_source.html">Go to the source code of this file.</a></p>
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Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___biquad_cascade_d_f1.html#gadd66a0aefdc645031d607b0a5b37a942">arm_biquad_cascade_df1_q15</a> (const <a class="el" href="structarm__biquad__casd__df1__inst__q15.html">arm_biquad_casd_df1_inst_q15</a> *S, <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> *pSrc, <a class="el" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea">q15_t</a> *pDst, uint32_t <a class="el" href="arm__variance__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)</td></tr>
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<a href="arm__biquad__cascade__df1__q15_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ---------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_biquad_cascade_df1_q15.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: Processing function for the </span>
<a name="l00011"></a>00011 <span class="comment">* Q15 Biquad cascade DirectFormI(DF1) filter. </span>
<a name="l00012"></a>00012 <span class="comment">* </span>
<a name="l00013"></a>00013 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0</span>
<a name="l00014"></a>00014 <span class="comment">* </span>
<a name="l00015"></a>00015 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00016"></a>00016 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00017"></a>00017 <span class="comment">* </span>
<a name="l00018"></a>00018 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00019"></a>00019 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00020"></a>00020 <span class="comment">* </span>
<a name="l00021"></a>00021 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00022"></a>00022 <span class="comment">* Documentation updated. </span>
<a name="l00023"></a>00023 <span class="comment">* </span>
<a name="l00024"></a>00024 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00025"></a>00025 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00026"></a>00026 <span class="comment">* </span>
<a name="l00027"></a>00027 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00028"></a>00028 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00029"></a>00029 <span class="comment">* </span>
<a name="l00030"></a>00030 <span class="comment">* Version 0.0.5 2010/04/26 </span>
<a name="l00031"></a>00031 <span class="comment">* incorporated review comments and updated with latest CMSIS layer </span>
<a name="l00032"></a>00032 <span class="comment">* </span>
<a name="l00033"></a>00033 <span class="comment">* Version 0.0.3 2010/03/10 </span>
<a name="l00034"></a>00034 <span class="comment">* Initial version </span>
<a name="l00035"></a>00035 <span class="comment">* -------------------------------------------------------------------- */</span>
<a name="l00036"></a>00036
<a name="l00037"></a>00037 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00038"></a>00038
<a name="l00070"></a><a class="code" href="group___biquad_cascade_d_f1.html#gadd66a0aefdc645031d607b0a5b37a942">00070</a> <span class="keywordtype">void</span> <a class="code" href="group___biquad_cascade_d_f1.html#gadd66a0aefdc645031d607b0a5b37a942" title="Processing function for the Q15 Biquad cascade filter.">arm_biquad_cascade_df1_q15</a>(
<a name="l00071"></a>00071 <span class="keyword">const</span> <a class="code" href="structarm__biquad__casd__df1__inst__q15.html" title="Instance structure for the Q15 Biquad cascade filter.">arm_biquad_casd_df1_inst_q15</a> * S,
<a name="l00072"></a>00072 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> * pSrc,
<a name="l00073"></a>00073 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> * pDst,
<a name="l00074"></a>00074 uint32_t <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)
<a name="l00075"></a>00075 {
<a name="l00076"></a>00076
<a name="l00077"></a>00077
<a name="l00078"></a>00078 <span class="preprocessor">#ifndef ARM_MATH_CM0</span>
<a name="l00079"></a>00079 <span class="preprocessor"></span>
<a name="l00080"></a>00080 <span class="comment">/* Run the below code for Cortex-M4 and Cortex-M3 */</span>
<a name="l00081"></a>00081
<a name="l00082"></a>00082 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> *pIn = pSrc; <span class="comment">/* Source pointer */</span>
<a name="l00083"></a>00083 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> *pOut = pDst; <span class="comment">/* Destination pointer */</span>
<a name="l00084"></a>00084 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> in; <span class="comment">/* Temporary variable to hold input value */</span>
<a name="l00085"></a>00085 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> out; <span class="comment">/* Temporary variable to hold output value */</span>
<a name="l00086"></a>00086 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> b0; <span class="comment">/* Temporary variable to hold bo value */</span>
<a name="l00087"></a>00087 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> b1, a1; <span class="comment">/* Filter coefficients */</span>
<a name="l00088"></a>00088 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> state_in, state_out; <span class="comment">/* Filter state variables */</span>
<a name="l00089"></a>00089 <a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a> acc; <span class="comment">/* Accumulator */</span>
<a name="l00090"></a>00090 int32_t shift = (15 - (int32_t) S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q15.html#ada7e9d6269e6ed4eacf8f68729e9832d">postShift</a>); <span class="comment">/* Post shift */</span>
<a name="l00091"></a>00091 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> *pState = S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q15.html#a5481104ef2f8f81360b80b47d69ae932">pState</a>; <span class="comment">/* State pointer */</span>
<a name="l00092"></a>00092 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> *pCoeffs = S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q15.html#a1edaacdebb5b09d7635bf20c779855fc">pCoeffs</a>; <span class="comment">/* Coefficient pointer */</span>
<a name="l00093"></a>00093 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> *pState_q31; <span class="comment">/* 32-bit state pointer for SIMD implementation */</span>
<a name="l00094"></a>00094 uint32_t sample, stage = (uint32_t) S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q15.html#ad6d95e70abcf4ff1300181415ad92153">numStages</a>; <span class="comment">/* Stage loop counter */</span>
<a name="l00095"></a>00095
<a name="l00096"></a>00096 <span class="keywordflow">do</span>
<a name="l00097"></a>00097 {
<a name="l00098"></a>00098 <span class="comment">/* Initialize state pointer of type q31 */</span>
<a name="l00099"></a>00099 pState_q31 = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> *) (pState);
<a name="l00100"></a>00100
<a name="l00101"></a>00101 <span class="comment">/* Read the b0 and 0 coefficients using SIMD */</span>
<a name="l00102"></a>00102 b0 = *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pCoeffs)++;
<a name="l00103"></a>00103
<a name="l00104"></a>00104 <span class="comment">/* Read the b1 and b2 coefficients using SIMD */</span>
<a name="l00105"></a>00105 b1 = *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pCoeffs)++;
<a name="l00106"></a>00106
<a name="l00107"></a>00107 <span class="comment">/* Read the a1 and a2 coefficients using SIMD */</span>
<a name="l00108"></a>00108 a1 = *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pCoeffs)++;
<a name="l00109"></a>00109
<a name="l00110"></a>00110 <span class="comment">/* Read the input state values from the state buffer: x[n-1], x[n-2] */</span>
<a name="l00111"></a>00111 state_in = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) (*pState_q31++);
<a name="l00112"></a>00112
<a name="l00113"></a>00113 <span class="comment">/* Read the output state values from the state buffer: y[n-1], y[n-2] */</span>
<a name="l00114"></a>00114 state_out = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) (*pState_q31);
<a name="l00115"></a>00115
<a name="l00116"></a>00116 <span class="comment">/* Apply loop unrolling and compute 2 output values simultaneously. */</span>
<a name="l00117"></a>00117 <span class="comment">/* The variable acc hold output values that are being computed: </span>
<a name="l00118"></a>00118 <span class="comment"> * </span>
<a name="l00119"></a>00119 <span class="comment"> * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] </span>
<a name="l00120"></a>00120 <span class="comment"> * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] </span>
<a name="l00121"></a>00121 <span class="comment"> */</span>
<a name="l00122"></a>00122 sample = blockSize &gt;&gt; 1u;
<a name="l00123"></a>00123
<a name="l00124"></a>00124 <span class="comment">/* First part of the processing with loop unrolling. Compute 2 outputs at a time. </span>
<a name="l00125"></a>00125 <span class="comment"> ** a second loop below computes the remaining 1 sample. */</span>
<a name="l00126"></a>00126 <span class="keywordflow">while</span>(sample &gt; 0u)
<a name="l00127"></a>00127 {
<a name="l00128"></a>00128
<a name="l00129"></a>00129 <span class="comment">/* Read the input */</span>
<a name="l00130"></a>00130 in = *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pIn)++;
<a name="l00131"></a>00131
<a name="l00132"></a>00132 <span class="comment">/* out = b0 * x[n] + 0 * 0 */</span>
<a name="l00133"></a>00133 out = __SMUAD(b0, in);
<a name="l00134"></a>00134
<a name="l00135"></a>00135 <span class="comment">/* acc += b1 * x[n-1] + b2 * x[n-2] + out */</span>
<a name="l00136"></a>00136 acc = __SMLALD(b1, state_in, out);
<a name="l00137"></a>00137 <span class="comment">/* acc += a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00138"></a>00138 acc = __SMLALD(a1, state_out, acc);
<a name="l00139"></a>00139
<a name="l00140"></a>00140 <span class="comment">/* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */</span>
<a name="l00141"></a>00141 out = __SSAT((acc &gt;&gt; shift), 16);
<a name="l00142"></a>00142
<a name="l00143"></a>00143 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00144"></a>00144 <span class="comment">/* The states should be updated as: */</span>
<a name="l00145"></a>00145 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00146"></a>00146 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00147"></a>00147 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00148"></a>00148 <span class="comment">/* Yn1 = acc */</span>
<a name="l00149"></a>00149 <span class="comment">/* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */</span>
<a name="l00150"></a>00150 <span class="comment">/* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */</span>
<a name="l00151"></a>00151
<a name="l00152"></a>00152 <span class="preprocessor">#ifndef ARM_MATH_BIG_ENDIAN</span>
<a name="l00153"></a>00153 <span class="preprocessor"></span>
<a name="l00154"></a>00154 state_in = __PKHBT(in, state_in, 16);
<a name="l00155"></a>00155 state_out = __PKHBT(out, state_out, 16);
<a name="l00156"></a>00156
<a name="l00157"></a>00157 <span class="preprocessor">#else</span>
<a name="l00158"></a>00158 <span class="preprocessor"></span>
<a name="l00159"></a>00159 state_in = __PKHBT(state_in &gt;&gt; 16, (in &gt;&gt; 16), 16);
<a name="l00160"></a>00160 state_out = __PKHBT(state_out &gt;&gt; 16, (out), 16);
<a name="l00161"></a>00161
<a name="l00162"></a>00162 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_BIG_ENDIAN */</span>
<a name="l00163"></a>00163
<a name="l00164"></a>00164 <span class="comment">/* out = b0 * x[n] + 0 * 0 */</span>
<a name="l00165"></a>00165 out = __SMUADX(b0, in);
<a name="l00166"></a>00166 <span class="comment">/* acc += b1 * x[n-1] + b2 * x[n-2] + out */</span>
<a name="l00167"></a>00167 acc = __SMLALD(b1, state_in, out);
<a name="l00168"></a>00168 <span class="comment">/* acc += a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00169"></a>00169 acc = __SMLALD(a1, state_out, acc);
<a name="l00170"></a>00170
<a name="l00171"></a>00171 <span class="comment">/* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */</span>
<a name="l00172"></a>00172 out = __SSAT((acc &gt;&gt; shift), 16);
<a name="l00173"></a>00173
<a name="l00174"></a>00174 <span class="comment">/* Store the output in the destination buffer. */</span>
<a name="l00175"></a>00175
<a name="l00176"></a>00176 <span class="preprocessor">#ifndef ARM_MATH_BIG_ENDIAN</span>
<a name="l00177"></a>00177 <span class="preprocessor"></span>
<a name="l00178"></a>00178 *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pOut)++ = __PKHBT(state_out, out, 16);
<a name="l00179"></a>00179
<a name="l00180"></a>00180 <span class="preprocessor">#else</span>
<a name="l00181"></a>00181 <span class="preprocessor"></span>
<a name="l00182"></a>00182 *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pOut)++ = __PKHBT(out, state_out &gt;&gt; 16, 16);
<a name="l00183"></a>00183
<a name="l00184"></a>00184 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_BIG_ENDIAN */</span>
<a name="l00185"></a>00185
<a name="l00186"></a>00186 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00187"></a>00187 <span class="comment">/* The states should be updated as: */</span>
<a name="l00188"></a>00188 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00189"></a>00189 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00190"></a>00190 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00191"></a>00191 <span class="comment">/* Yn1 = acc */</span>
<a name="l00192"></a>00192 <span class="comment">/* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */</span>
<a name="l00193"></a>00193 <span class="comment">/* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */</span>
<a name="l00194"></a>00194 <span class="preprocessor">#ifndef ARM_MATH_BIG_ENDIAN</span>
<a name="l00195"></a>00195 <span class="preprocessor"></span>
<a name="l00196"></a>00196 state_in = __PKHBT(in &gt;&gt; 16, state_in, 16);
<a name="l00197"></a>00197 state_out = __PKHBT(out, state_out, 16);
<a name="l00198"></a>00198
<a name="l00199"></a>00199 <span class="preprocessor">#else</span>
<a name="l00200"></a>00200 <span class="preprocessor"></span>
<a name="l00201"></a>00201 state_in = __PKHBT(state_in &gt;&gt; 16, in, 16);
<a name="l00202"></a>00202 state_out = __PKHBT(state_out &gt;&gt; 16, out, 16);
<a name="l00203"></a>00203
<a name="l00204"></a>00204 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_BIG_ENDIAN */</span>
<a name="l00205"></a>00205
<a name="l00206"></a>00206
<a name="l00207"></a>00207 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00208"></a>00208 sample--;
<a name="l00209"></a>00209
<a name="l00210"></a>00210 }
<a name="l00211"></a>00211
<a name="l00212"></a>00212 <span class="comment">/* If the blockSize is not a multiple of 2, compute any remaining output samples here. </span>
<a name="l00213"></a>00213 <span class="comment"> ** No loop unrolling is used. */</span>
<a name="l00214"></a>00214
<a name="l00215"></a>00215 <span class="keywordflow">if</span>((blockSize &amp; 0x1u) != 0u)
<a name="l00216"></a>00216 {
<a name="l00217"></a>00217 <span class="comment">/* Read the input */</span>
<a name="l00218"></a>00218 in = *pIn++;
<a name="l00219"></a>00219
<a name="l00220"></a>00220 <span class="comment">/* out = b0 * x[n] + 0 * 0 */</span>
<a name="l00221"></a>00221
<a name="l00222"></a>00222 <span class="preprocessor">#ifndef ARM_MATH_BIG_ENDIAN</span>
<a name="l00223"></a>00223 <span class="preprocessor"></span>
<a name="l00224"></a>00224 out = __SMUAD(b0, in);
<a name="l00225"></a>00225
<a name="l00226"></a>00226 <span class="preprocessor">#else</span>
<a name="l00227"></a>00227 <span class="preprocessor"></span>
<a name="l00228"></a>00228 out = __SMUADX(b0, in);
<a name="l00229"></a>00229
<a name="l00230"></a>00230 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_BIG_ENDIAN */</span>
<a name="l00231"></a>00231
<a name="l00232"></a>00232 <span class="comment">/* acc = b1 * x[n-1] + b2 * x[n-2] + out */</span>
<a name="l00233"></a>00233 acc = __SMLALD(b1, state_in, out);
<a name="l00234"></a>00234 <span class="comment">/* acc += a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00235"></a>00235 acc = __SMLALD(a1, state_out, acc);
<a name="l00236"></a>00236
<a name="l00237"></a>00237 <span class="comment">/* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */</span>
<a name="l00238"></a>00238 out = __SSAT((acc &gt;&gt; shift), 16);
<a name="l00239"></a>00239
<a name="l00240"></a>00240 <span class="comment">/* Store the output in the destination buffer. */</span>
<a name="l00241"></a>00241 *pOut++ = (<a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a>) out;
<a name="l00242"></a>00242
<a name="l00243"></a>00243 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00244"></a>00244 <span class="comment">/* The states should be updated as: */</span>
<a name="l00245"></a>00245 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00246"></a>00246 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00247"></a>00247 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00248"></a>00248 <span class="comment">/* Yn1 = acc */</span>
<a name="l00249"></a>00249 <span class="comment">/* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */</span>
<a name="l00250"></a>00250 <span class="comment">/* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */</span>
<a name="l00251"></a>00251
<a name="l00252"></a>00252 <span class="preprocessor">#ifndef ARM_MATH_BIG_ENDIAN</span>
<a name="l00253"></a>00253 <span class="preprocessor"></span>
<a name="l00254"></a>00254 state_in = __PKHBT(in, state_in, 16);
<a name="l00255"></a>00255 state_out = __PKHBT(out, state_out, 16);
<a name="l00256"></a>00256
<a name="l00257"></a>00257 <span class="preprocessor">#else</span>
<a name="l00258"></a>00258 <span class="preprocessor"></span>
<a name="l00259"></a>00259 state_in = __PKHBT(state_in &gt;&gt; 16, in, 16);
<a name="l00260"></a>00260 state_out = __PKHBT(state_out &gt;&gt; 16, out, 16);
<a name="l00261"></a>00261
<a name="l00262"></a>00262 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_BIG_ENDIAN */</span>
<a name="l00263"></a>00263
<a name="l00264"></a>00264 }
<a name="l00265"></a>00265
<a name="l00266"></a>00266 <span class="comment">/* The first stage goes from the input wire to the output wire. */</span>
<a name="l00267"></a>00267 <span class="comment">/* Subsequent numStages occur in-place in the output wire */</span>
<a name="l00268"></a>00268 pIn = pDst;
<a name="l00269"></a>00269
<a name="l00270"></a>00270 <span class="comment">/* Reset the output pointer */</span>
<a name="l00271"></a>00271 pOut = pDst;
<a name="l00272"></a>00272
<a name="l00273"></a>00273 <span class="comment">/* Store the updated state variables back into the state array */</span>
<a name="l00274"></a>00274 *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pState)++ = state_in;
<a name="l00275"></a>00275 *<a class="code" href="arm__math_8h.html#a9de2e0a5785be82866bcb96012282248" title="definition to read/write two 16 bit values.">__SIMD32</a>(pState)++ = state_out;
<a name="l00276"></a>00276
<a name="l00277"></a>00277
<a name="l00278"></a>00278 <span class="comment">/* Decrement the loop counter */</span>
<a name="l00279"></a>00279 stage--;
<a name="l00280"></a>00280
<a name="l00281"></a>00281 } <span class="keywordflow">while</span>(stage &gt; 0u);
<a name="l00282"></a>00282
<a name="l00283"></a>00283 <span class="preprocessor">#else</span>
<a name="l00284"></a>00284 <span class="preprocessor"></span>
<a name="l00285"></a>00285 <span class="comment">/* Run the below code for Cortex-M0 */</span>
<a name="l00286"></a>00286
<a name="l00287"></a>00287 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> *pIn = pSrc; <span class="comment">/* Source pointer */</span>
<a name="l00288"></a>00288 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> *pOut = pDst; <span class="comment">/* Destination pointer */</span>
<a name="l00289"></a>00289 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> b0, b1, b2, a1, a2; <span class="comment">/* Filter coefficients */</span>
<a name="l00290"></a>00290 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> Xn1, Xn2, Yn1, Yn2; <span class="comment">/* Filter state variables */</span>
<a name="l00291"></a>00291 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> Xn; <span class="comment">/* temporary input */</span>
<a name="l00292"></a>00292 <a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a> acc; <span class="comment">/* Accumulator */</span>
<a name="l00293"></a>00293 int32_t shift = (15 - (int32_t) S-&gt;postShift); <span class="comment">/* Post shift */</span>
<a name="l00294"></a>00294 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> *pState = S-&gt;pState; <span class="comment">/* State pointer */</span>
<a name="l00295"></a>00295 <a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a> *pCoeffs = S-&gt;pCoeffs; <span class="comment">/* Coefficient pointer */</span>
<a name="l00296"></a>00296 uint32_t sample, stage = (uint32_t) S-&gt;numStages; <span class="comment">/* Stage loop counter */</span>
<a name="l00297"></a>00297
<a name="l00298"></a>00298 <span class="keywordflow">do</span>
<a name="l00299"></a>00299 {
<a name="l00300"></a>00300 <span class="comment">/* Reading the coefficients */</span>
<a name="l00301"></a>00301 b0 = *pCoeffs++;
<a name="l00302"></a>00302 b1 = *pCoeffs++;
<a name="l00303"></a>00303 b2 = *pCoeffs++;
<a name="l00304"></a>00304 a1 = *pCoeffs++;
<a name="l00305"></a>00305 a2 = *pCoeffs++;
<a name="l00306"></a>00306
<a name="l00307"></a>00307 <span class="comment">/* Reading the state values */</span>
<a name="l00308"></a>00308 Xn1 = pState[0];
<a name="l00309"></a>00309 Xn2 = pState[1];
<a name="l00310"></a>00310 Yn1 = pState[2];
<a name="l00311"></a>00311 Yn2 = pState[3];
<a name="l00312"></a>00312
<a name="l00313"></a>00313 <span class="comment">/* The variables acc holds the output value that is computed: </span>
<a name="l00314"></a>00314 <span class="comment"> * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] </span>
<a name="l00315"></a>00315 <span class="comment"> */</span>
<a name="l00316"></a>00316
<a name="l00317"></a>00317 sample = <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>;
<a name="l00318"></a>00318
<a name="l00319"></a>00319 <span class="keywordflow">while</span>(sample &gt; 0u)
<a name="l00320"></a>00320 {
<a name="l00321"></a>00321 <span class="comment">/* Read the input */</span>
<a name="l00322"></a>00322 Xn = *pIn++;
<a name="l00323"></a>00323
<a name="l00324"></a>00324 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00325"></a>00325 <span class="comment">/* acc = b0 * x[n] */</span>
<a name="l00326"></a>00326 acc = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) b0 *Xn;
<a name="l00327"></a>00327
<a name="l00328"></a>00328 <span class="comment">/* acc += b1 * x[n-1] */</span>
<a name="l00329"></a>00329 acc += (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) b1 *Xn1;
<a name="l00330"></a>00330 <span class="comment">/* acc += b[2] * x[n-2] */</span>
<a name="l00331"></a>00331 acc += (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) b2 *Xn2;
<a name="l00332"></a>00332 <span class="comment">/* acc += a1 * y[n-1] */</span>
<a name="l00333"></a>00333 acc += (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) a1 *Yn1;
<a name="l00334"></a>00334 <span class="comment">/* acc += a2 * y[n-2] */</span>
<a name="l00335"></a>00335 acc += (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) a2 *Yn2;
<a name="l00336"></a>00336
<a name="l00337"></a>00337 <span class="comment">/* The result is converted to 1.31 */</span>
<a name="l00338"></a>00338 acc = __SSAT((acc &gt;&gt; shift), 16);
<a name="l00339"></a>00339
<a name="l00340"></a>00340 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00341"></a>00341 <span class="comment">/* The states should be updated as: */</span>
<a name="l00342"></a>00342 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00343"></a>00343 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00344"></a>00344 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00345"></a>00345 <span class="comment">/* Yn1 = acc */</span>
<a name="l00346"></a>00346 Xn2 = Xn1;
<a name="l00347"></a>00347 Xn1 = Xn;
<a name="l00348"></a>00348 Yn2 = Yn1;
<a name="l00349"></a>00349 Yn1 = (<a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a>) acc;
<a name="l00350"></a>00350
<a name="l00351"></a>00351 <span class="comment">/* Store the output in the destination buffer. */</span>
<a name="l00352"></a>00352 *pOut++ = (<a class="code" href="arm__math_8h.html#ab5a8fb21a5b3b983d5f54f31614052ea" title="16-bit fractional data type in 1.15 format.">q15_t</a>) acc;
<a name="l00353"></a>00353
<a name="l00354"></a>00354 <span class="comment">/* decrement the loop counter */</span>
<a name="l00355"></a>00355 sample--;
<a name="l00356"></a>00356 }
<a name="l00357"></a>00357
<a name="l00358"></a>00358 <span class="comment">/* The first stage goes from the input buffer to the output buffer. */</span>
<a name="l00359"></a>00359 <span class="comment">/* Subsequent stages occur in-place in the output buffer */</span>
<a name="l00360"></a>00360 pIn = pDst;
<a name="l00361"></a>00361
<a name="l00362"></a>00362 <span class="comment">/* Reset to destination pointer */</span>
<a name="l00363"></a>00363 pOut = pDst;
<a name="l00364"></a>00364
<a name="l00365"></a>00365 <span class="comment">/* Store the updated state variables back into the pState array */</span>
<a name="l00366"></a>00366 *pState++ = Xn1;
<a name="l00367"></a>00367 *pState++ = Xn2;
<a name="l00368"></a>00368 *pState++ = Yn1;
<a name="l00369"></a>00369 *pState++ = Yn2;
<a name="l00370"></a>00370
<a name="l00371"></a>00371 } <span class="keywordflow">while</span>(--stage);
<a name="l00372"></a>00372
<a name="l00373"></a>00373 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_CM0 */</span>
<a name="l00374"></a>00374
<a name="l00375"></a>00375 }
<a name="l00376"></a>00376
<a name="l00377"></a>00377
</pre></div></div>
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
<p><a href="arm__biquad__cascade__df1__q31_8c_source.html">Go to the source code of this file.</a></p>
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Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___biquad_cascade_d_f1.html#ga27b0c54da702713976e5202d20b4473f">arm_biquad_cascade_df1_q31</a> (const <a class="el" href="structarm__biquad__casd__df1__inst__q31.html">arm_biquad_casd_df1_inst_q31</a> *S, <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> *pSrc, <a class="el" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0">q31_t</a> *pDst, uint32_t <a class="el" href="arm__variance__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)</td></tr>
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<a href="arm__biquad__cascade__df1__q31_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ---------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_biquad_cascade_df1_q31.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: Processing function for the </span>
<a name="l00011"></a>00011 <span class="comment">* Q31 Biquad cascade filter </span>
<a name="l00012"></a>00012 <span class="comment">* </span>
<a name="l00013"></a>00013 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0</span>
<a name="l00014"></a>00014 <span class="comment">* </span>
<a name="l00015"></a>00015 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00016"></a>00016 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00017"></a>00017 <span class="comment">* </span>
<a name="l00018"></a>00018 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00019"></a>00019 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00020"></a>00020 <span class="comment">* </span>
<a name="l00021"></a>00021 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00022"></a>00022 <span class="comment">* Documentation updated. </span>
<a name="l00023"></a>00023 <span class="comment">* </span>
<a name="l00024"></a>00024 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00025"></a>00025 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00026"></a>00026 <span class="comment">* </span>
<a name="l00027"></a>00027 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00028"></a>00028 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00029"></a>00029 <span class="comment">* </span>
<a name="l00030"></a>00030 <span class="comment">* Version 0.0.5 2010/04/26 </span>
<a name="l00031"></a>00031 <span class="comment">* incorporated review comments and updated with latest CMSIS layer </span>
<a name="l00032"></a>00032 <span class="comment">* </span>
<a name="l00033"></a>00033 <span class="comment">* Version 0.0.3 2010/03/10 </span>
<a name="l00034"></a>00034 <span class="comment">* Initial version </span>
<a name="l00035"></a>00035 <span class="comment">* -------------------------------------------------------------------- */</span>
<a name="l00036"></a>00036
<a name="l00037"></a>00037 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00038"></a>00038
<a name="l00069"></a><a class="code" href="group___biquad_cascade_d_f1.html#ga27b0c54da702713976e5202d20b4473f">00069</a> <span class="keywordtype">void</span> <a class="code" href="group___biquad_cascade_d_f1.html#ga27b0c54da702713976e5202d20b4473f" title="Processing function for the Q31 Biquad cascade filter.">arm_biquad_cascade_df1_q31</a>(
<a name="l00070"></a>00070 <span class="keyword">const</span> <a class="code" href="structarm__biquad__casd__df1__inst__q31.html" title="Instance structure for the Q31 Biquad cascade filter.">arm_biquad_casd_df1_inst_q31</a> * S,
<a name="l00071"></a>00071 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> * pSrc,
<a name="l00072"></a>00072 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> * pDst,
<a name="l00073"></a>00073 uint32_t <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)
<a name="l00074"></a>00074 {
<a name="l00075"></a>00075 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> *pIn = pSrc; <span class="comment">/* input pointer initialization */</span>
<a name="l00076"></a>00076 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> *pOut = pDst; <span class="comment">/* output pointer initialization */</span>
<a name="l00077"></a>00077 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> *pState = S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q31.html#a5dcf4727f58eb4e8e8b392508d8657bb">pState</a>; <span class="comment">/* pState pointer initialization */</span>
<a name="l00078"></a>00078 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> *pCoeffs = S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q31.html#aa62366c632f3b5305086f841f079dbd2">pCoeffs</a>; <span class="comment">/* coeff pointer initialization */</span>
<a name="l00079"></a>00079 <a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a> acc; <span class="comment">/* accumulator */</span>
<a name="l00080"></a>00080 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> Xn1, Xn2, Yn1, Yn2; <span class="comment">/* Filter state variables */</span>
<a name="l00081"></a>00081 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> b0, b1, b2, a1, a2; <span class="comment">/* Filter coefficients */</span>
<a name="l00082"></a>00082 <a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a> Xn; <span class="comment">/* temporary input */</span>
<a name="l00083"></a>00083 uint32_t shift = 32u - ((uint32_t) S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q31.html#a636c7fbe09ec4bef0bc0a4b4e2151cbe">postShift</a> + 1u); <span class="comment">/* Shift to be applied to the output */</span>
<a name="l00084"></a>00084 uint32_t sample, stage = S-&gt;<a class="code" href="structarm__biquad__casd__df1__inst__q31.html#a2c2b579f1df1d8273a5d9d945c27e1b2">numStages</a>; <span class="comment">/* loop counters */</span>
<a name="l00085"></a>00085
<a name="l00086"></a>00086
<a name="l00087"></a>00087 <span class="preprocessor">#ifndef ARM_MATH_CM0</span>
<a name="l00088"></a>00088 <span class="preprocessor"></span>
<a name="l00089"></a>00089 <span class="comment">/* Run the below code for Cortex-M4 and Cortex-M3 */</span>
<a name="l00090"></a>00090
<a name="l00091"></a>00091 <span class="keywordflow">do</span>
<a name="l00092"></a>00092 {
<a name="l00093"></a>00093 <span class="comment">/* Reading the coefficients */</span>
<a name="l00094"></a>00094 b0 = *pCoeffs++;
<a name="l00095"></a>00095 b1 = *pCoeffs++;
<a name="l00096"></a>00096 b2 = *pCoeffs++;
<a name="l00097"></a>00097 a1 = *pCoeffs++;
<a name="l00098"></a>00098 a2 = *pCoeffs++;
<a name="l00099"></a>00099
<a name="l00100"></a>00100 <span class="comment">/* Reading the state values */</span>
<a name="l00101"></a>00101 Xn1 = pState[0];
<a name="l00102"></a>00102 Xn2 = pState[1];
<a name="l00103"></a>00103 Yn1 = pState[2];
<a name="l00104"></a>00104 Yn2 = pState[3];
<a name="l00105"></a>00105
<a name="l00106"></a>00106 <span class="comment">/* Apply loop unrolling and compute 4 output values simultaneously. */</span>
<a name="l00107"></a>00107 <span class="comment">/* The variable acc hold output values that are being computed: </span>
<a name="l00108"></a>00108 <span class="comment"> * </span>
<a name="l00109"></a>00109 <span class="comment"> * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] </span>
<a name="l00110"></a>00110 <span class="comment"> */</span>
<a name="l00111"></a>00111
<a name="l00112"></a>00112 sample = blockSize &gt;&gt; 2u;
<a name="l00113"></a>00113
<a name="l00114"></a>00114 <span class="comment">/* First part of the processing with loop unrolling. Compute 4 outputs at a time. </span>
<a name="l00115"></a>00115 <span class="comment"> ** a second loop below computes the remaining 1 to 3 samples. */</span>
<a name="l00116"></a>00116 <span class="keywordflow">while</span>(sample &gt; 0u)
<a name="l00117"></a>00117 {
<a name="l00118"></a>00118 <span class="comment">/* Read the input */</span>
<a name="l00119"></a>00119 Xn = *pIn++;
<a name="l00120"></a>00120
<a name="l00121"></a>00121 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00122"></a>00122
<a name="l00123"></a>00123 <span class="comment">/* acc = b0 * x[n] */</span>
<a name="l00124"></a>00124 acc = (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b0 *Xn;
<a name="l00125"></a>00125 <span class="comment">/* acc += b1 * x[n-1] */</span>
<a name="l00126"></a>00126 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b1 *Xn1;
<a name="l00127"></a>00127 <span class="comment">/* acc += b[2] * x[n-2] */</span>
<a name="l00128"></a>00128 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b2 *Xn2;
<a name="l00129"></a>00129 <span class="comment">/* acc += a1 * y[n-1] */</span>
<a name="l00130"></a>00130 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) a1 *Yn1;
<a name="l00131"></a>00131 <span class="comment">/* acc += a2 * y[n-2] */</span>
<a name="l00132"></a>00132 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) a2 *Yn2;
<a name="l00133"></a>00133
<a name="l00134"></a>00134 <span class="comment">/* The result is converted to 1.31 , Yn2 variable is reused */</span>
<a name="l00135"></a>00135 Yn2 = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) (acc &gt;&gt; shift);
<a name="l00136"></a>00136
<a name="l00137"></a>00137 <span class="comment">/* Store the output in the destination buffer. */</span>
<a name="l00138"></a>00138 *pOut++ = Yn2;
<a name="l00139"></a>00139
<a name="l00140"></a>00140 <span class="comment">/* Read the second input */</span>
<a name="l00141"></a>00141 Xn2 = *pIn++;
<a name="l00142"></a>00142
<a name="l00143"></a>00143 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00144"></a>00144
<a name="l00145"></a>00145 <span class="comment">/* acc = b0 * x[n] */</span>
<a name="l00146"></a>00146 acc = (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b0 *Xn2;
<a name="l00147"></a>00147 <span class="comment">/* acc += b1 * x[n-1] */</span>
<a name="l00148"></a>00148 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b1 *Xn;
<a name="l00149"></a>00149 <span class="comment">/* acc += b[2] * x[n-2] */</span>
<a name="l00150"></a>00150 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b2 *Xn1;
<a name="l00151"></a>00151 <span class="comment">/* acc += a1 * y[n-1] */</span>
<a name="l00152"></a>00152 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) a1 *Yn2;
<a name="l00153"></a>00153 <span class="comment">/* acc += a2 * y[n-2] */</span>
<a name="l00154"></a>00154 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) a2 *Yn1;
<a name="l00155"></a>00155
<a name="l00156"></a>00156
<a name="l00157"></a>00157 <span class="comment">/* The result is converted to 1.31, Yn1 variable is reused */</span>
<a name="l00158"></a>00158 Yn1 = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) (acc &gt;&gt; shift);
<a name="l00159"></a>00159
<a name="l00160"></a>00160 <span class="comment">/* Store the output in the destination buffer. */</span>
<a name="l00161"></a>00161 *pOut++ = Yn1;
<a name="l00162"></a>00162
<a name="l00163"></a>00163 <span class="comment">/* Read the third input */</span>
<a name="l00164"></a>00164 Xn1 = *pIn++;
<a name="l00165"></a>00165
<a name="l00166"></a>00166 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00167"></a>00167
<a name="l00168"></a>00168 <span class="comment">/* acc = b0 * x[n] */</span>
<a name="l00169"></a>00169 acc = (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b0 *Xn1;
<a name="l00170"></a>00170 <span class="comment">/* acc += b1 * x[n-1] */</span>
<a name="l00171"></a>00171 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b1 *Xn2;
<a name="l00172"></a>00172 <span class="comment">/* acc += b[2] * x[n-2] */</span>
<a name="l00173"></a>00173 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b2 *Xn;
<a name="l00174"></a>00174 <span class="comment">/* acc += a1 * y[n-1] */</span>
<a name="l00175"></a>00175 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) a1 *Yn1;
<a name="l00176"></a>00176 <span class="comment">/* acc += a2 * y[n-2] */</span>
<a name="l00177"></a>00177 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) a2 *Yn2;
<a name="l00178"></a>00178
<a name="l00179"></a>00179 <span class="comment">/* The result is converted to 1.31, Yn2 variable is reused */</span>
<a name="l00180"></a>00180 Yn2 = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) (acc &gt;&gt; shift);
<a name="l00181"></a>00181
<a name="l00182"></a>00182 <span class="comment">/* Store the output in the destination buffer. */</span>
<a name="l00183"></a>00183 *pOut++ = Yn2;
<a name="l00184"></a>00184
<a name="l00185"></a>00185 <span class="comment">/* Read the forth input */</span>
<a name="l00186"></a>00186 Xn = *pIn++;
<a name="l00187"></a>00187
<a name="l00188"></a>00188 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00189"></a>00189
<a name="l00190"></a>00190 <span class="comment">/* acc = b0 * x[n] */</span>
<a name="l00191"></a>00191 acc = (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b0 *Xn;
<a name="l00192"></a>00192 <span class="comment">/* acc += b1 * x[n-1] */</span>
<a name="l00193"></a>00193 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b1 *Xn1;
<a name="l00194"></a>00194 <span class="comment">/* acc += b[2] * x[n-2] */</span>
<a name="l00195"></a>00195 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b2 *Xn2;
<a name="l00196"></a>00196 <span class="comment">/* acc += a1 * y[n-1] */</span>
<a name="l00197"></a>00197 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) a1 *Yn2;
<a name="l00198"></a>00198 <span class="comment">/* acc += a2 * y[n-2] */</span>
<a name="l00199"></a>00199 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) a2 *Yn1;
<a name="l00200"></a>00200
<a name="l00201"></a>00201 <span class="comment">/* The result is converted to 1.31, Yn1 variable is reused */</span>
<a name="l00202"></a>00202 Yn1 = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) (acc &gt;&gt; shift);
<a name="l00203"></a>00203
<a name="l00204"></a>00204 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00205"></a>00205 <span class="comment">/* The states should be updated as: */</span>
<a name="l00206"></a>00206 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00207"></a>00207 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00208"></a>00208 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00209"></a>00209 <span class="comment">/* Yn1 = acc */</span>
<a name="l00210"></a>00210 Xn2 = Xn1;
<a name="l00211"></a>00211 Xn1 = Xn;
<a name="l00212"></a>00212
<a name="l00213"></a>00213 <span class="comment">/* Store the output in the destination buffer. */</span>
<a name="l00214"></a>00214 *pOut++ = Yn1;
<a name="l00215"></a>00215
<a name="l00216"></a>00216 <span class="comment">/* decrement the loop counter */</span>
<a name="l00217"></a>00217 sample--;
<a name="l00218"></a>00218 }
<a name="l00219"></a>00219
<a name="l00220"></a>00220 <span class="comment">/* If the blockSize is not a multiple of 4, compute any remaining output samples here. </span>
<a name="l00221"></a>00221 <span class="comment"> ** No loop unrolling is used. */</span>
<a name="l00222"></a>00222 sample = (blockSize &amp; 0x3u);
<a name="l00223"></a>00223
<a name="l00224"></a>00224 <span class="keywordflow">while</span>(sample &gt; 0u)
<a name="l00225"></a>00225 {
<a name="l00226"></a>00226 <span class="comment">/* Read the input */</span>
<a name="l00227"></a>00227 Xn = *pIn++;
<a name="l00228"></a>00228
<a name="l00229"></a>00229 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00230"></a>00230
<a name="l00231"></a>00231 <span class="comment">/* acc = b0 * x[n] */</span>
<a name="l00232"></a>00232 acc = (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b0 *Xn;
<a name="l00233"></a>00233 <span class="comment">/* acc += b1 * x[n-1] */</span>
<a name="l00234"></a>00234 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b1 *Xn1;
<a name="l00235"></a>00235 <span class="comment">/* acc += b[2] * x[n-2] */</span>
<a name="l00236"></a>00236 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b2 *Xn2;
<a name="l00237"></a>00237 <span class="comment">/* acc += a1 * y[n-1] */</span>
<a name="l00238"></a>00238 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) a1 *Yn1;
<a name="l00239"></a>00239 <span class="comment">/* acc += a2 * y[n-2] */</span>
<a name="l00240"></a>00240 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) a2 *Yn2;
<a name="l00241"></a>00241
<a name="l00242"></a>00242 <span class="comment">/* The result is converted to 1.31 */</span>
<a name="l00243"></a>00243 acc = acc &gt;&gt; shift;
<a name="l00244"></a>00244
<a name="l00245"></a>00245 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00246"></a>00246 <span class="comment">/* The states should be updated as: */</span>
<a name="l00247"></a>00247 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00248"></a>00248 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00249"></a>00249 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00250"></a>00250 <span class="comment">/* Yn1 = acc */</span>
<a name="l00251"></a>00251 Xn2 = Xn1;
<a name="l00252"></a>00252 Xn1 = Xn;
<a name="l00253"></a>00253 Yn2 = Yn1;
<a name="l00254"></a>00254 Yn1 = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) acc;
<a name="l00255"></a>00255
<a name="l00256"></a>00256 <span class="comment">/* Store the output in the destination buffer. */</span>
<a name="l00257"></a>00257 *pOut++ = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) acc;
<a name="l00258"></a>00258
<a name="l00259"></a>00259 <span class="comment">/* decrement the loop counter */</span>
<a name="l00260"></a>00260 sample--;
<a name="l00261"></a>00261 }
<a name="l00262"></a>00262
<a name="l00263"></a>00263 <span class="comment">/* The first stage goes from the input buffer to the output buffer. */</span>
<a name="l00264"></a>00264 <span class="comment">/* Subsequent stages occur in-place in the output buffer */</span>
<a name="l00265"></a>00265 pIn = pDst;
<a name="l00266"></a>00266
<a name="l00267"></a>00267 <span class="comment">/* Reset to destination pointer */</span>
<a name="l00268"></a>00268 pOut = pDst;
<a name="l00269"></a>00269
<a name="l00270"></a>00270 <span class="comment">/* Store the updated state variables back into the pState array */</span>
<a name="l00271"></a>00271 *pState++ = Xn1;
<a name="l00272"></a>00272 *pState++ = Xn2;
<a name="l00273"></a>00273 *pState++ = Yn1;
<a name="l00274"></a>00274 *pState++ = Yn2;
<a name="l00275"></a>00275
<a name="l00276"></a>00276 } <span class="keywordflow">while</span>(--stage);
<a name="l00277"></a>00277
<a name="l00278"></a>00278 <span class="preprocessor">#else</span>
<a name="l00279"></a>00279 <span class="preprocessor"></span>
<a name="l00280"></a>00280 <span class="comment">/* Run the below code for Cortex-M0 */</span>
<a name="l00281"></a>00281
<a name="l00282"></a>00282 <span class="keywordflow">do</span>
<a name="l00283"></a>00283 {
<a name="l00284"></a>00284 <span class="comment">/* Reading the coefficients */</span>
<a name="l00285"></a>00285 b0 = *pCoeffs++;
<a name="l00286"></a>00286 b1 = *pCoeffs++;
<a name="l00287"></a>00287 b2 = *pCoeffs++;
<a name="l00288"></a>00288 a1 = *pCoeffs++;
<a name="l00289"></a>00289 a2 = *pCoeffs++;
<a name="l00290"></a>00290
<a name="l00291"></a>00291 <span class="comment">/* Reading the state values */</span>
<a name="l00292"></a>00292 Xn1 = pState[0];
<a name="l00293"></a>00293 Xn2 = pState[1];
<a name="l00294"></a>00294 Yn1 = pState[2];
<a name="l00295"></a>00295 Yn2 = pState[3];
<a name="l00296"></a>00296
<a name="l00297"></a>00297 <span class="comment">/* The variables acc holds the output value that is computed: </span>
<a name="l00298"></a>00298 <span class="comment"> * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] </span>
<a name="l00299"></a>00299 <span class="comment"> */</span>
<a name="l00300"></a>00300
<a name="l00301"></a>00301 sample = <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>;
<a name="l00302"></a>00302
<a name="l00303"></a>00303 <span class="keywordflow">while</span>(sample &gt; 0u)
<a name="l00304"></a>00304 {
<a name="l00305"></a>00305 <span class="comment">/* Read the input */</span>
<a name="l00306"></a>00306 Xn = *pIn++;
<a name="l00307"></a>00307
<a name="l00308"></a>00308 <span class="comment">/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */</span>
<a name="l00309"></a>00309 <span class="comment">/* acc = b0 * x[n] */</span>
<a name="l00310"></a>00310 acc = (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b0 *Xn;
<a name="l00311"></a>00311
<a name="l00312"></a>00312 <span class="comment">/* acc += b1 * x[n-1] */</span>
<a name="l00313"></a>00313 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b1 *Xn1;
<a name="l00314"></a>00314 <span class="comment">/* acc += b[2] * x[n-2] */</span>
<a name="l00315"></a>00315 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) b2 *Xn2;
<a name="l00316"></a>00316 <span class="comment">/* acc += a1 * y[n-1] */</span>
<a name="l00317"></a>00317 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) a1 *Yn1;
<a name="l00318"></a>00318 <span class="comment">/* acc += a2 * y[n-2] */</span>
<a name="l00319"></a>00319 acc += (<a class="code" href="arm__math_8h.html#a5aea1cb12fc02d9d44c8abf217eaa5c6" title="64-bit fractional data type in 1.63 format.">q63_t</a>) a2 *Yn2;
<a name="l00320"></a>00320
<a name="l00321"></a>00321 <span class="comment">/* The result is converted to 1.31 */</span>
<a name="l00322"></a>00322 acc = acc &gt;&gt; shift;
<a name="l00323"></a>00323
<a name="l00324"></a>00324 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00325"></a>00325 <span class="comment">/* The states should be updated as: */</span>
<a name="l00326"></a>00326 <span class="comment">/* Xn2 = Xn1 */</span>
<a name="l00327"></a>00327 <span class="comment">/* Xn1 = Xn */</span>
<a name="l00328"></a>00328 <span class="comment">/* Yn2 = Yn1 */</span>
<a name="l00329"></a>00329 <span class="comment">/* Yn1 = acc */</span>
<a name="l00330"></a>00330 Xn2 = Xn1;
<a name="l00331"></a>00331 Xn1 = Xn;
<a name="l00332"></a>00332 Yn2 = Yn1;
<a name="l00333"></a>00333 Yn1 = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) acc;
<a name="l00334"></a>00334
<a name="l00335"></a>00335 <span class="comment">/* Store the output in the destination buffer. */</span>
<a name="l00336"></a>00336 *pOut++ = (<a class="code" href="arm__math_8h.html#adc89a3547f5324b7b3b95adec3806bc0" title="32-bit fractional data type in 1.31 format.">q31_t</a>) acc;
<a name="l00337"></a>00337
<a name="l00338"></a>00338 <span class="comment">/* decrement the loop counter */</span>
<a name="l00339"></a>00339 sample--;
<a name="l00340"></a>00340 }
<a name="l00341"></a>00341
<a name="l00342"></a>00342 <span class="comment">/* The first stage goes from the input buffer to the output buffer. */</span>
<a name="l00343"></a>00343 <span class="comment">/* Subsequent stages occur in-place in the output buffer */</span>
<a name="l00344"></a>00344 pIn = pDst;
<a name="l00345"></a>00345
<a name="l00346"></a>00346 <span class="comment">/* Reset to destination pointer */</span>
<a name="l00347"></a>00347 pOut = pDst;
<a name="l00348"></a>00348
<a name="l00349"></a>00349 <span class="comment">/* Store the updated state variables back into the pState array */</span>
<a name="l00350"></a>00350 *pState++ = Xn1;
<a name="l00351"></a>00351 *pState++ = Xn2;
<a name="l00352"></a>00352 *pState++ = Yn1;
<a name="l00353"></a>00353 *pState++ = Yn2;
<a name="l00354"></a>00354
<a name="l00355"></a>00355 } <span class="keywordflow">while</span>(--stage);
<a name="l00356"></a>00356
<a name="l00357"></a>00357 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_CM0 */</span>
<a name="l00358"></a>00358 }
<a name="l00359"></a>00359
</pre></div></div>
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<h1>arm_biquad_cascade_df2T_f32.c File Reference</h1> </div>
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
<p><a href="arm__biquad__cascade__df2_t__f32_8c_source.html">Go to the source code of this file.</a></p>
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Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___biquad_cascade_d_f2_t.html#ga646c25998bf35991c60299b1431460f7">arm_biquad_cascade_df2T_f32</a> (const <a class="el" href="structarm__biquad__cascade__df2_t__instance__f32.html">arm_biquad_cascade_df2T_instance_f32</a> *S, <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> *pSrc, <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> *pDst, uint32_t <a class="el" href="arm__variance__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)</td></tr>
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<a href="arm__biquad__cascade__df2_t__f32_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/* ---------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_biquad_cascade_df2T_f32.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: Processing function for the floating-point transposed </span>
<a name="l00011"></a>00011 <span class="comment">* direct form II Biquad cascade filter. </span>
<a name="l00012"></a>00012 <span class="comment">* </span>
<a name="l00013"></a>00013 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0</span>
<a name="l00014"></a>00014 <span class="comment">* </span>
<a name="l00015"></a>00015 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00016"></a>00016 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00017"></a>00017 <span class="comment">* </span>
<a name="l00018"></a>00018 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00019"></a>00019 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00020"></a>00020 <span class="comment">* </span>
<a name="l00021"></a>00021 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00022"></a>00022 <span class="comment">* Documentation updated. </span>
<a name="l00023"></a>00023 <span class="comment">* </span>
<a name="l00024"></a>00024 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00025"></a>00025 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00026"></a>00026 <span class="comment">* </span>
<a name="l00027"></a>00027 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00028"></a>00028 <span class="comment">* Production release and review comments incorporated </span>
<a name="l00029"></a>00029 <span class="comment">* </span>
<a name="l00030"></a>00030 <span class="comment">* Version 0.0.7 2010/06/10 </span>
<a name="l00031"></a>00031 <span class="comment">* Misra-C changes done </span>
<a name="l00032"></a>00032 <span class="comment">* -------------------------------------------------------------------- */</span>
<a name="l00033"></a>00033
<a name="l00034"></a>00034 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00035"></a>00035
<a name="l00143"></a><a class="code" href="group___biquad_cascade_d_f2_t.html#ga646c25998bf35991c60299b1431460f7">00143</a> <span class="keywordtype">void</span> <a class="code" href="group___biquad_cascade_d_f2_t.html#ga646c25998bf35991c60299b1431460f7" title="Processing function for the floating-point transposed direct form II Biquad cascade filter...">arm_biquad_cascade_df2T_f32</a>(
<a name="l00144"></a>00144 <span class="keyword">const</span> <a class="code" href="structarm__biquad__cascade__df2_t__instance__f32.html" title="Instance structure for the floating-point transposed direct form II Biquad cascade filter...">arm_biquad_cascade_df2T_instance_f32</a> * S,
<a name="l00145"></a>00145 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> * pSrc,
<a name="l00146"></a>00146 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> * pDst,
<a name="l00147"></a>00147 uint32_t <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>)
<a name="l00148"></a>00148 {
<a name="l00149"></a>00149
<a name="l00150"></a>00150 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> *pIn = pSrc; <span class="comment">/* source pointer */</span>
<a name="l00151"></a>00151 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> *pOut = pDst; <span class="comment">/* destination pointer */</span>
<a name="l00152"></a>00152 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> *pState = S-&gt;<a class="code" href="structarm__biquad__cascade__df2_t__instance__f32.html#a24d223addfd926a7177088cf2efe76b1">pState</a>; <span class="comment">/* State pointer */</span>
<a name="l00153"></a>00153 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> *pCoeffs = S-&gt;<a class="code" href="structarm__biquad__cascade__df2_t__instance__f32.html#a49a24fe1b6ad3b0b26779c32d8d80b2e">pCoeffs</a>; <span class="comment">/* coefficient pointer */</span>
<a name="l00154"></a>00154 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> acc0; <span class="comment">/* Simulates the accumulator */</span>
<a name="l00155"></a>00155 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> b0, b1, b2, a1, a2; <span class="comment">/* Filter coefficients */</span>
<a name="l00156"></a>00156 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> Xn; <span class="comment">/* temporary input */</span>
<a name="l00157"></a>00157 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> d1, d2; <span class="comment">/* state variables */</span>
<a name="l00158"></a>00158 uint32_t sample, stage = S-&gt;<a class="code" href="structarm__biquad__cascade__df2_t__instance__f32.html#a4d17958c33c3d0a905f974bac50f033f">numStages</a>; <span class="comment">/* loop counters */</span>
<a name="l00159"></a>00159
<a name="l00160"></a>00160
<a name="l00161"></a>00161 <span class="preprocessor">#ifndef ARM_MATH_CM0</span>
<a name="l00162"></a>00162 <span class="preprocessor"></span>
<a name="l00163"></a>00163 <span class="comment">/* Run the below code for Cortex-M4 and Cortex-M3 */</span>
<a name="l00164"></a>00164
<a name="l00165"></a>00165 <span class="keywordflow">do</span>
<a name="l00166"></a>00166 {
<a name="l00167"></a>00167 <span class="comment">/* Reading the coefficients */</span>
<a name="l00168"></a>00168 b0 = *pCoeffs++;
<a name="l00169"></a>00169 b1 = *pCoeffs++;
<a name="l00170"></a>00170 b2 = *pCoeffs++;
<a name="l00171"></a>00171 a1 = *pCoeffs++;
<a name="l00172"></a>00172 a2 = *pCoeffs++;
<a name="l00173"></a>00173
<a name="l00174"></a>00174 <span class="comment">/*Reading the state values */</span>
<a name="l00175"></a>00175 d1 = pState[0];
<a name="l00176"></a>00176 d2 = pState[1];
<a name="l00177"></a>00177
<a name="l00178"></a>00178 <span class="comment">/* Apply loop unrolling and compute 4 output values simultaneously. */</span>
<a name="l00179"></a>00179 sample = blockSize &gt;&gt; 2u;
<a name="l00180"></a>00180
<a name="l00181"></a>00181 <span class="comment">/* First part of the processing with loop unrolling. Compute 4 outputs at a time. </span>
<a name="l00182"></a>00182 <span class="comment"> ** a second loop below computes the remaining 1 to 3 samples. */</span>
<a name="l00183"></a>00183 <span class="keywordflow">while</span>(sample &gt; 0u)
<a name="l00184"></a>00184 {
<a name="l00185"></a>00185 <span class="comment">/* Read the first input */</span>
<a name="l00186"></a>00186 Xn = *pIn++;
<a name="l00187"></a>00187
<a name="l00188"></a>00188 <span class="comment">/* y[n] = b0 * x[n] + d1 */</span>
<a name="l00189"></a>00189 acc0 = (b0 * Xn) + d1;
<a name="l00190"></a>00190
<a name="l00191"></a>00191 <span class="comment">/* Store the result in the accumulator in the destination buffer. */</span>
<a name="l00192"></a>00192 *pOut++ = acc0;
<a name="l00193"></a>00193
<a name="l00194"></a>00194 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00195"></a>00195 <span class="comment">/* d1 = b1 * x[n] + a1 * y[n] + d2 */</span>
<a name="l00196"></a>00196 d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
<a name="l00197"></a>00197
<a name="l00198"></a>00198 <span class="comment">/* d2 = b2 * x[n] + a2 * y[n] */</span>
<a name="l00199"></a>00199 d2 = (b2 * Xn) + (a2 * acc0);
<a name="l00200"></a>00200
<a name="l00201"></a>00201 <span class="comment">/* Read the second input */</span>
<a name="l00202"></a>00202 Xn = *pIn++;
<a name="l00203"></a>00203
<a name="l00204"></a>00204 <span class="comment">/* y[n] = b0 * x[n] + d1 */</span>
<a name="l00205"></a>00205 acc0 = (b0 * Xn) + d1;
<a name="l00206"></a>00206
<a name="l00207"></a>00207 <span class="comment">/* Store the result in the accumulator in the destination buffer. */</span>
<a name="l00208"></a>00208 *pOut++ = acc0;
<a name="l00209"></a>00209
<a name="l00210"></a>00210 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00211"></a>00211 <span class="comment">/* d1 = b1 * x[n] + a1 * y[n] + d2 */</span>
<a name="l00212"></a>00212 d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
<a name="l00213"></a>00213
<a name="l00214"></a>00214 <span class="comment">/* d2 = b2 * x[n] + a2 * y[n] */</span>
<a name="l00215"></a>00215 d2 = (b2 * Xn) + (a2 * acc0);
<a name="l00216"></a>00216
<a name="l00217"></a>00217 <span class="comment">/* Read the third input */</span>
<a name="l00218"></a>00218 Xn = *pIn++;
<a name="l00219"></a>00219
<a name="l00220"></a>00220 <span class="comment">/* y[n] = b0 * x[n] + d1 */</span>
<a name="l00221"></a>00221 acc0 = (b0 * Xn) + d1;
<a name="l00222"></a>00222
<a name="l00223"></a>00223 <span class="comment">/* Store the result in the accumulator in the destination buffer. */</span>
<a name="l00224"></a>00224 *pOut++ = acc0;
<a name="l00225"></a>00225
<a name="l00226"></a>00226 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00227"></a>00227 <span class="comment">/* d1 = b1 * x[n] + a1 * y[n] + d2 */</span>
<a name="l00228"></a>00228 d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
<a name="l00229"></a>00229
<a name="l00230"></a>00230 <span class="comment">/* d2 = b2 * x[n] + a2 * y[n] */</span>
<a name="l00231"></a>00231 d2 = (b2 * Xn) + (a2 * acc0);
<a name="l00232"></a>00232
<a name="l00233"></a>00233 <span class="comment">/* Read the fourth input */</span>
<a name="l00234"></a>00234 Xn = *pIn++;
<a name="l00235"></a>00235
<a name="l00236"></a>00236 <span class="comment">/* y[n] = b0 * x[n] + d1 */</span>
<a name="l00237"></a>00237 acc0 = (b0 * Xn) + d1;
<a name="l00238"></a>00238
<a name="l00239"></a>00239 <span class="comment">/* Store the result in the accumulator in the destination buffer. */</span>
<a name="l00240"></a>00240 *pOut++ = acc0;
<a name="l00241"></a>00241
<a name="l00242"></a>00242 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00243"></a>00243 <span class="comment">/* d1 = b1 * x[n] + a1 * y[n] + d2 */</span>
<a name="l00244"></a>00244 d1 = (b1 * Xn) + (a1 * acc0) + d2;
<a name="l00245"></a>00245
<a name="l00246"></a>00246 <span class="comment">/* d2 = b2 * x[n] + a2 * y[n] */</span>
<a name="l00247"></a>00247 d2 = (b2 * Xn) + (a2 * acc0);
<a name="l00248"></a>00248
<a name="l00249"></a>00249 <span class="comment">/* decrement the loop counter */</span>
<a name="l00250"></a>00250 sample--;
<a name="l00251"></a>00251
<a name="l00252"></a>00252 }
<a name="l00253"></a>00253
<a name="l00254"></a>00254 <span class="comment">/* If the blockSize is not a multiple of 4, compute any remaining output samples here. </span>
<a name="l00255"></a>00255 <span class="comment"> ** No loop unrolling is used. */</span>
<a name="l00256"></a>00256 sample = blockSize &amp; 0x3u;
<a name="l00257"></a>00257
<a name="l00258"></a>00258 <span class="keywordflow">while</span>(sample &gt; 0u)
<a name="l00259"></a>00259 {
<a name="l00260"></a>00260 <span class="comment">/* Read the input */</span>
<a name="l00261"></a>00261 Xn = *pIn++;
<a name="l00262"></a>00262
<a name="l00263"></a>00263 <span class="comment">/* y[n] = b0 * x[n] + d1 */</span>
<a name="l00264"></a>00264 acc0 = (b0 * Xn) + d1;
<a name="l00265"></a>00265
<a name="l00266"></a>00266 <span class="comment">/* Store the result in the accumulator in the destination buffer. */</span>
<a name="l00267"></a>00267 *pOut++ = acc0;
<a name="l00268"></a>00268
<a name="l00269"></a>00269 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00270"></a>00270 <span class="comment">/* d1 = b1 * x[n] + a1 * y[n] + d2 */</span>
<a name="l00271"></a>00271 d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
<a name="l00272"></a>00272
<a name="l00273"></a>00273 <span class="comment">/* d2 = b2 * x[n] + a2 * y[n] */</span>
<a name="l00274"></a>00274 d2 = (b2 * Xn) + (a2 * acc0);
<a name="l00275"></a>00275
<a name="l00276"></a>00276 <span class="comment">/* decrement the loop counter */</span>
<a name="l00277"></a>00277 sample--;
<a name="l00278"></a>00278 }
<a name="l00279"></a>00279
<a name="l00280"></a>00280 <span class="comment">/* Store the updated state variables back into the state array */</span>
<a name="l00281"></a>00281 *pState++ = d1;
<a name="l00282"></a>00282 *pState++ = d2;
<a name="l00283"></a>00283
<a name="l00284"></a>00284 <span class="comment">/* The current stage input is given as the output to the next stage */</span>
<a name="l00285"></a>00285 pIn = pDst;
<a name="l00286"></a>00286
<a name="l00287"></a>00287 <span class="comment">/*Reset the output working pointer */</span>
<a name="l00288"></a>00288 pOut = pDst;
<a name="l00289"></a>00289
<a name="l00290"></a>00290 <span class="comment">/* decrement the loop counter */</span>
<a name="l00291"></a>00291 stage--;
<a name="l00292"></a>00292
<a name="l00293"></a>00293 } <span class="keywordflow">while</span>(stage &gt; 0u);
<a name="l00294"></a>00294
<a name="l00295"></a>00295 <span class="preprocessor">#else</span>
<a name="l00296"></a>00296 <span class="preprocessor"></span>
<a name="l00297"></a>00297 <span class="comment">/* Run the below code for Cortex-M0 */</span>
<a name="l00298"></a>00298
<a name="l00299"></a>00299 <span class="keywordflow">do</span>
<a name="l00300"></a>00300 {
<a name="l00301"></a>00301 <span class="comment">/* Reading the coefficients */</span>
<a name="l00302"></a>00302 b0 = *pCoeffs++;
<a name="l00303"></a>00303 b1 = *pCoeffs++;
<a name="l00304"></a>00304 b2 = *pCoeffs++;
<a name="l00305"></a>00305 a1 = *pCoeffs++;
<a name="l00306"></a>00306 a2 = *pCoeffs++;
<a name="l00307"></a>00307
<a name="l00308"></a>00308 <span class="comment">/*Reading the state values */</span>
<a name="l00309"></a>00309 d1 = pState[0];
<a name="l00310"></a>00310 d2 = pState[1];
<a name="l00311"></a>00311
<a name="l00312"></a>00312
<a name="l00313"></a>00313 sample = <a class="code" href="arm__fir__example__f32_8c.html#ab6558f40a619c2502fbc24c880fd4fb0">blockSize</a>;
<a name="l00314"></a>00314
<a name="l00315"></a>00315 <span class="keywordflow">while</span>(sample &gt; 0u)
<a name="l00316"></a>00316 {
<a name="l00317"></a>00317 <span class="comment">/* Read the input */</span>
<a name="l00318"></a>00318 Xn = *pIn++;
<a name="l00319"></a>00319
<a name="l00320"></a>00320 <span class="comment">/* y[n] = b0 * x[n] + d1 */</span>
<a name="l00321"></a>00321 acc0 = (b0 * Xn) + d1;
<a name="l00322"></a>00322
<a name="l00323"></a>00323 <span class="comment">/* Store the result in the accumulator in the destination buffer. */</span>
<a name="l00324"></a>00324 *pOut++ = acc0;
<a name="l00325"></a>00325
<a name="l00326"></a>00326 <span class="comment">/* Every time after the output is computed state should be updated. */</span>
<a name="l00327"></a>00327 <span class="comment">/* d1 = b1 * x[n] + a1 * y[n] + d2 */</span>
<a name="l00328"></a>00328 d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
<a name="l00329"></a>00329
<a name="l00330"></a>00330 <span class="comment">/* d2 = b2 * x[n] + a2 * y[n] */</span>
<a name="l00331"></a>00331 d2 = (b2 * Xn) + (a2 * acc0);
<a name="l00332"></a>00332
<a name="l00333"></a>00333 <span class="comment">/* decrement the loop counter */</span>
<a name="l00334"></a>00334 sample--;
<a name="l00335"></a>00335 }
<a name="l00336"></a>00336
<a name="l00337"></a>00337 <span class="comment">/* Store the updated state variables back into the state array */</span>
<a name="l00338"></a>00338 *pState++ = d1;
<a name="l00339"></a>00339 *pState++ = d2;
<a name="l00340"></a>00340
<a name="l00341"></a>00341 <span class="comment">/* The current stage input is given as the output to the next stage */</span>
<a name="l00342"></a>00342 pIn = pDst;
<a name="l00343"></a>00343
<a name="l00344"></a>00344 <span class="comment">/*Reset the output working pointer */</span>
<a name="l00345"></a>00345 pOut = pDst;
<a name="l00346"></a>00346
<a name="l00347"></a>00347 <span class="comment">/* decrement the loop counter */</span>
<a name="l00348"></a>00348 stage--;
<a name="l00349"></a>00349
<a name="l00350"></a>00350 } <span class="keywordflow">while</span>(stage &gt; 0u);
<a name="l00351"></a>00351
<a name="l00352"></a>00352 <span class="preprocessor">#endif </span><span class="comment">/* #ifndef ARM_MATH_CM0 */</span>
<a name="l00353"></a>00353
<a name="l00354"></a>00354 }
<a name="l00355"></a>00355
<a name="l00356"></a>00356
</pre></div></div>
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<h1>arm_biquad_cascade_df2T_init_f32.c File Reference</h1> </div>
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<code>#include &quot;<a class="el" href="arm__math_8h_source.html">arm_math.h</a>&quot;</code><br/>
<p><a href="arm__biquad__cascade__df2_t__init__f32_8c_source.html">Go to the source code of this file.</a></p>
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Functions</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___biquad_cascade_d_f2_t.html#ga70eaddf317a4a8bde6bd6a97df67fedd">arm_biquad_cascade_df2T_init_f32</a> (<a class="el" href="structarm__biquad__cascade__df2_t__instance__f32.html">arm_biquad_cascade_df2T_instance_f32</a> *S, uint8_t numStages, <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> *pCoeffs, <a class="el" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715">float32_t</a> *pState)</td></tr>
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<a href="arm__biquad__cascade__df2_t__init__f32_8c.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/*----------------------------------------------------------------------------- </span>
<a name="l00002"></a>00002 <span class="comment">* Copyright (C) 2010 ARM Limited. All rights reserved. </span>
<a name="l00003"></a>00003 <span class="comment">* </span>
<a name="l00004"></a>00004 <span class="comment">* $Date: 15. July 2011 </span>
<a name="l00005"></a>00005 <span class="comment">* $Revision: V1.0.10 </span>
<a name="l00006"></a>00006 <span class="comment">* </span>
<a name="l00007"></a>00007 <span class="comment">* Project: CMSIS DSP Library </span>
<a name="l00008"></a>00008 <span class="comment">* Title: arm_biquad_cascade_df2T_init_f32.c </span>
<a name="l00009"></a>00009 <span class="comment">* </span>
<a name="l00010"></a>00010 <span class="comment">* Description: Initialization function for the floating-point transposed </span>
<a name="l00011"></a>00011 <span class="comment">* direct form II Biquad cascade filter. </span>
<a name="l00012"></a>00012 <span class="comment">* </span>
<a name="l00013"></a>00013 <span class="comment">* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0</span>
<a name="l00014"></a>00014 <span class="comment">* </span>
<a name="l00015"></a>00015 <span class="comment">* Version 1.0.10 2011/7/15 </span>
<a name="l00016"></a>00016 <span class="comment">* Big Endian support added and Merged M0 and M3/M4 Source code. </span>
<a name="l00017"></a>00017 <span class="comment">* </span>
<a name="l00018"></a>00018 <span class="comment">* Version 1.0.3 2010/11/29 </span>
<a name="l00019"></a>00019 <span class="comment">* Re-organized the CMSIS folders and updated documentation. </span>
<a name="l00020"></a>00020 <span class="comment">* </span>
<a name="l00021"></a>00021 <span class="comment">* Version 1.0.2 2010/11/11 </span>
<a name="l00022"></a>00022 <span class="comment">* Documentation updated. </span>
<a name="l00023"></a>00023 <span class="comment">* </span>
<a name="l00024"></a>00024 <span class="comment">* Version 1.0.1 2010/10/05 </span>
<a name="l00025"></a>00025 <span class="comment">* Production release and review comments incorporated. </span>
<a name="l00026"></a>00026 <span class="comment">* </span>
<a name="l00027"></a>00027 <span class="comment">* Version 1.0.0 2010/09/20 </span>
<a name="l00028"></a>00028 <span class="comment">* Production release and review comments incorporated </span>
<a name="l00029"></a>00029 <span class="comment">* </span>
<a name="l00030"></a>00030 <span class="comment">* Version 0.0.7 2010/06/10 </span>
<a name="l00031"></a>00031 <span class="comment">* Misra-C changes done </span>
<a name="l00032"></a>00032 <span class="comment">* ---------------------------------------------------------------------------*/</span>
<a name="l00033"></a>00033
<a name="l00034"></a>00034 <span class="preprocessor">#include &quot;<a class="code" href="arm__math_8h.html">arm_math.h</a>&quot;</span>
<a name="l00035"></a>00035
<a name="l00073"></a><a class="code" href="group___biquad_cascade_d_f2_t.html#ga70eaddf317a4a8bde6bd6a97df67fedd">00073</a> <span class="keywordtype">void</span> <a class="code" href="group___biquad_cascade_d_f2_t.html#ga70eaddf317a4a8bde6bd6a97df67fedd" title="Initialization function for the floating-point transposed direct form II Biquad cascade filter...">arm_biquad_cascade_df2T_init_f32</a>(
<a name="l00074"></a>00074 <a class="code" href="structarm__biquad__cascade__df2_t__instance__f32.html" title="Instance structure for the floating-point transposed direct form II Biquad cascade filter...">arm_biquad_cascade_df2T_instance_f32</a> * S,
<a name="l00075"></a>00075 uint8_t numStages,
<a name="l00076"></a>00076 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> * pCoeffs,
<a name="l00077"></a>00077 <a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a> * pState)
<a name="l00078"></a>00078 {
<a name="l00079"></a>00079 <span class="comment">/* Assign filter stages */</span>
<a name="l00080"></a>00080 S-&gt;<a class="code" href="structarm__biquad__cascade__df2_t__instance__f32.html#a4d17958c33c3d0a905f974bac50f033f">numStages</a> = numStages;
<a name="l00081"></a>00081
<a name="l00082"></a>00082 <span class="comment">/* Assign coefficient pointer */</span>
<a name="l00083"></a>00083 S-&gt;<a class="code" href="structarm__biquad__cascade__df2_t__instance__f32.html#a49a24fe1b6ad3b0b26779c32d8d80b2e">pCoeffs</a> = pCoeffs;
<a name="l00084"></a>00084
<a name="l00085"></a>00085 <span class="comment">/* Clear state buffer and size is always 2 * numStages */</span>
<a name="l00086"></a>00086 memset(pState, 0, (2u * (uint32_t) numStages) * <span class="keyword">sizeof</span>(<a class="code" href="arm__math_8h.html#a4611b605e45ab401f02cab15c5e38715" title="32-bit floating-point type definition.">float32_t</a>));
<a name="l00087"></a>00087
<a name="l00088"></a>00088 <span class="comment">/* Assign state pointer */</span>
<a name="l00089"></a>00089 S-&gt;<a class="code" href="structarm__biquad__cascade__df2_t__instance__f32.html#a24d223addfd926a7177088cf2efe76b1">pState</a> = pState;
<a name="l00090"></a>00090 }
<a name="l00091"></a>00091
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