100 lines
2.9 KiB
C
100 lines
2.9 KiB
C
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/*
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* stm32f4xx_ctx.c
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*
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* Created on: Oct 1, 2015
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* Author: tkl
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*/
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#include <stdbool.h>
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#include "stm32f4xx.h"
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#include "stack.h"
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#include "queue.h"
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#include "thread.h"
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#include "stm32f4xx_ctx.h"
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#ifdef __NVIC_PRIO_BITS
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/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
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#define configPRIO_BITS __NVIC_PRIO_BITS
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#else
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#define configPRIO_BITS 4 /* 15 priority levels */
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#endif
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#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf
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#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
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#define portNVIC_SYSPRI2_REG (*((volatile uint32_t *)0xe000ed20))
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#define portNVIC_PENDSV_PRI (((uint32_t)configKERNEL_INTERRUPT_PRIORITY) << 16UL)
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#define portNVIC_SYSTICK_PRI (((uint32_t)configKERNEL_INTERRUPT_PRIORITY) << 24UL)
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extern volatile struct thread_context *current_thread;
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void start_first_task(void) __attribute__ ((naked));
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void PendSV_Handler(void) __attribute__ ((naked));
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void SVC_Handler(void) __attribute__ ((naked));
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void start_first_task(void)
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{
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portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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__asm volatile("ldr r0, =0xE000ED08");
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__asm volatile("ldr r0, [r0]");
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__asm volatile("ldr r0, [r0]");
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__asm volatile("msr msp, r0");
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__asm volatile("cpsie i");
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__asm volatile("cpsie f");
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__asm volatile("dsb");
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__asm volatile("isb");
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__asm volatile("svc 0");
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__asm volatile("nop");
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}
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void arch_schedule(void)
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{
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*((volatile unsigned long *) 0xe000ed04) = 0x10000000;
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}
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#define MAX_SYSCALL_INTERRUPT_PRIORITY ( 5 << (8 - __NVIC_PRIO_BITS) )
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void PendSV_Handler (void)
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{
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__asm volatile("mrs r0, psp");
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__asm volatile("isb");
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__asm volatile("ldr r3, =current_thread");
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__asm volatile("ldr r2, [r3]");
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__asm volatile("tst r14, #0x10");
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__asm volatile("it eq");
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__asm volatile("vstmdbeq r0!, {s16-s31}");
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__asm volatile("stmdb r0!, {r4-r11, r14}");
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__asm volatile("str r0, [r2]");
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__asm volatile("stmdb sp!, {r3}");
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__asm volatile("mov r0, %0"::"i"(MAX_SYSCALL_INTERRUPT_PRIORITY));
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__asm volatile("msr basepri, r0");
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__asm volatile("dsb");
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__asm volatile("isb");
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__asm volatile("bl thread_switch_context");
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__asm volatile("mov r0, #0");
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__asm volatile("msr basepri, r0");
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__asm volatile("ldmia sp!, {r3}");
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__asm volatile("ldr r1, [r3]");
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__asm volatile("ldr r0, [r1]");
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__asm volatile("ldmia r0!, {r4-r11, r14}");
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__asm volatile("tst r14, #0x10");
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__asm volatile("it eq");
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__asm volatile("vldmiaeq r0!, {s16-s31}");
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__asm volatile("msr psp, r0");
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__asm volatile("isb");
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__asm volatile("bx r14");
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}
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void SVC_Handler(void)
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{
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__asm volatile("ldr r3, =current_thread");
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__asm volatile("ldr r1, [r3]");
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__asm volatile("ldr r0, [r1]");
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__asm volatile("ldmia r0!, {r4-r11, r14}");
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__asm volatile("msr psp, r0");
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__asm volatile("isb");
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__asm volatile("mov r0, #0");
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__asm volatile("msr basepri, r0");
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__asm volatile("bx r14");
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}
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