100 lines
2.9 KiB
C
100 lines
2.9 KiB
C
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/*
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* stm32f4_pwm.c
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*
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* Created on: Aug 9, 2016
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* Author: tkl
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*/
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#include <stdint.h>
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#include "stm32f4xx.h"
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#include "stm32f4_pwm.h"
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struct stm32f4_pwm_object {
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uint8_t used_channels;
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uint32_t channel_1_max_period;
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uint32_t channel_2_max_period;
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uint32_t channel_3_max_period;
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uint32_t channel_4_max_period;
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};
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static struct stm32f4_pwm_object stm32f4_pwm_object = {
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.used_channels = 0,
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.channel_1_max_period = 0,
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.channel_2_max_period = 0,
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.channel_3_max_period = 0,
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.channel_4_max_period = 0,
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};
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int stm32f4_pwm_open(struct stm32f4_pwm *pwm)
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{
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uint32_t clk_ahb_timer = 0, clk_ahb_gpio = 0;
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uint8_t gpio_af_timer = 0;
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if(pwm->timer == TIM4) {
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clk_ahb_timer = RCC_APB1Periph_TIM4;
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gpio_af_timer = GPIO_AF_TIM4;
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}
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RCC_APB1PeriphClockCmd(clk_ahb_timer, ENABLE);
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if(pwm->port == GPIOD) {
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clk_ahb_gpio = RCC_AHB1Periph_GPIOD;
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}
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RCC_AHB1PeriphClockCmd(clk_ahb_gpio, ENABLE);
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GPIO_Init(pwm->port, (GPIO_InitTypeDef *)pwm->port_cfg);
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GPIO_PinAFConfig(pwm->port, pwm->pin_src, gpio_af_timer);
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TIM_TimeBaseInit(pwm->timer, (TIM_TimeBaseInitTypeDef *)pwm->timer_cfg);
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switch(pwm->channel) {
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case channel_1:
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TIM_OC1Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg);
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TIM_OC1PreloadConfig(pwm->timer, TIM_OCPreload_Enable);
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stm32f4_pwm_object.channel_1_max_period = pwm->timer_cfg->TIM_Period + 1;
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break;
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case channel_2:
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TIM_OC2Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg);
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TIM_OC2PreloadConfig(pwm->timer, TIM_OCPreload_Enable);
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stm32f4_pwm_object.channel_2_max_period = pwm->timer_cfg->TIM_Period + 1;
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break;
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case channel_3:
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TIM_OC3Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg);
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TIM_OC3PreloadConfig(pwm->timer, TIM_OCPreload_Enable);
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stm32f4_pwm_object.channel_3_max_period = pwm->timer_cfg->TIM_Period + 1;
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break;
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case channel_4:
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TIM_OC4Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg);
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TIM_OC4PreloadConfig(pwm->timer, TIM_OCPreload_Enable);
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stm32f4_pwm_object.channel_4_max_period = pwm->timer_cfg->TIM_Period + 1;
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break;
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}
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TIM_ARRPreloadConfig(pwm->timer, ENABLE);
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TIM_Cmd(pwm->timer, ENABLE);
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stm32f4_pwm_object.used_channels++;
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return 0;
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}
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int stm32f4_pwm_close(struct stm32f4_pwm *pwm)
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{
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stm32f4_pwm_object.used_channels--;
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if(stm32f4_pwm_object.used_channels == 0) {
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TIM_Cmd(pwm->timer, DISABLE);
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}
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return 0;
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}
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int stm32f4_pwm_set_duty_cycle(struct stm32f4_pwm *pwm, unsigned int duty_cycle_percent)
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{
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switch(pwm->channel) {
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case channel_1:
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TIM_SetCompare1(pwm->timer, stm32f4_pwm_object.channel_1_max_period * duty_cycle_percent / 100);
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break;
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case channel_2:
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TIM_SetCompare2(pwm->timer, stm32f4_pwm_object.channel_2_max_period * duty_cycle_percent / 100);
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break;
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case channel_3:
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TIM_SetCompare3(pwm->timer, stm32f4_pwm_object.channel_3_max_period * duty_cycle_percent / 100);
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break;
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case channel_4:
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TIM_SetCompare4(pwm->timer, stm32f4_pwm_object.channel_4_max_period * duty_cycle_percent / 100);
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break;
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}
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}
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