From 43d07d71b587135b780e86d82b492a8455c02f8a Mon Sep 17 00:00:00 2001 From: tkl Date: Mon, 8 Aug 2016 11:19:08 +0200 Subject: [PATCH 1/8] pwm test app --- .cproject | 23 +++++++++++++++++++++- Makefile | 2 +- config/make/stm32f4xx.mk | 5 ++--- source/firmware/kernel/shell.c | 8 ++++---- source/test/pwm/main.c | 35 ++++++++++++++++++++++++++++++++++ source/test/pwm/pwm.mk | 4 ++++ source/test/test.mk | 5 ++++- 7 files changed, 72 insertions(+), 10 deletions(-) create mode 100644 source/test/pwm/main.c create mode 100644 source/test/pwm/pwm.mk diff --git a/.cproject b/.cproject index 4507fd4..e426cac 100755 --- a/.cproject +++ b/.cproject @@ -136,6 +136,7 @@ make + all true true @@ -143,6 +144,7 @@ make + clean true true @@ -150,7 +152,6 @@ make - distclean true false @@ -206,6 +207,7 @@ make + all true true @@ -237,6 +239,7 @@ make + distclean true false @@ -282,6 +285,22 @@ false true + + make + TEST_APP=pwm BOARD=stm32f4-discovery DEBUG=y + test + true + false + true + + + make + TEST_APP=pwm BOARD=stm32f4-discovery DEBUG=y + install + true + false + true + make APP=example_radio_rx BOARD=msp430-ccrf DEBUG=y @@ -308,6 +327,7 @@ make + all true true @@ -315,6 +335,7 @@ make + clean true true diff --git a/Makefile b/Makefile index 1fccb67..1f44a67 100755 --- a/Makefile +++ b/Makefile @@ -83,7 +83,7 @@ doc: @$(MKDIR) $(DOC_DIR) (cat $(DOXYFILE) ; echo "INPUT=$(DOC_SRC)" ; echo "OUTPUT_DIRECTORY=$(DOC_DIR)") | doxygen - -test: check $(OBJECTS) $(ASM_OBJECTS) +test: $(OBJECTS) $(ASM_OBJECTS) @$(MKDIR) $(EXE_DIR) @$(MKDIR) $(MAP_DIR) @$(MKDIR) $(SIZE_DIR) diff --git a/config/make/stm32f4xx.mk b/config/make/stm32f4xx.mk index 4a9e9f3..252ca65 100644 --- a/config/make/stm32f4xx.mk +++ b/config/make/stm32f4xx.mk @@ -9,8 +9,8 @@ endif CROSS_COMPILE=arm-none-eabi- INCLUDES += \ - /usr/lib/arm-none-eabi/include \ - /usr/lib/gcc/arm-none-eabi/4.8/include + /opt/arm-2011.09/arm-none-eabi/include \ + /opt/arm-2011.09/lib/gcc/arm-none-eabi/4.6.1/include ifeq ($(DEBUG),y) OPTIM = 0 @@ -35,7 +35,6 @@ CFLAGS += \ -mfloat-abi=softfp \ -fdata-sections \ -ffunction-sections -# -D inline= -mthumb\ CPPCHECK_FLAGS += \ -D USE_STDPERIPH_DRIVER\ diff --git a/source/firmware/kernel/shell.c b/source/firmware/kernel/shell.c index 0cfdba2..3a832da 100644 --- a/source/firmware/kernel/shell.c +++ b/source/firmware/kernel/shell.c @@ -23,9 +23,9 @@ struct shell_object { struct shell_object shell_object; -#define RX_STACK_SIZE 256 -stack_t rx_stack[RX_STACK_SIZE]; -struct thread_context rx_thread; +#define TH_STACK_SIZE 256 +stack_t th_stack[TH_STACK_SIZE]; +struct thread_context th_ctx; static void parse(const char *buffer, unsigned int len) { @@ -71,7 +71,7 @@ int shell_init(const struct driver *shell_device) return -1; list_init(&shell_object.command_list); shell_object.shell_device = shell_device; - thread_create(&rx_thread, rx_stack, RX_STACK_SIZE, rx_func, NULL, THREAD_PRIO_LOW); + thread_create(&th_ctx, th_stack, TH_STACK_SIZE, rx_func, NULL, THREAD_PRIO_LOW); return 0; } diff --git a/source/test/pwm/main.c b/source/test/pwm/main.c new file mode 100644 index 0000000..343676f --- /dev/null +++ b/source/test/pwm/main.c @@ -0,0 +1,35 @@ +/* + * main.c + * + * Created on: Aug 2, 2016 + * Author: tkl + */ + +#include + +#include "driver.h" +#include "board.h" +#include "stack.h" +#include "queue.h" +#include "kernel.h" +#include "driver.h" +#include "list.h" +#include "shell.h" + +#define TH_STACK_SIZE 256 +stack_t th_stack[TH_STACK_SIZE]; +struct thread_context th_ctx; +static void th_func(void *arg) +{ + while(1) { + } +} + +int main(void) +{ + thread_create(&th_ctx, th_stack, TH_STACK_SIZE, th_func, NULL, THREAD_PRIO_LOW); + + schedule_start(); + + return 0; +} diff --git a/source/test/pwm/pwm.mk b/source/test/pwm/pwm.mk new file mode 100644 index 0000000..0ce5cc1 --- /dev/null +++ b/source/test/pwm/pwm.mk @@ -0,0 +1,4 @@ +CHECK_FOLDER += source/test/pwm +SUB_FOLDER += source/test/pwm +INCLUDES += source/test/pwm +DOC_SRC += source/test/pwm diff --git a/source/test/test.mk b/source/test/test.mk index 910224c..e16b6ff 100644 --- a/source/test/test.mk +++ b/source/test/test.mk @@ -1,3 +1,6 @@ ifeq ($(TEST_APP), shell) include source/test/shell/shell.mk -endif \ No newline at end of file +endif +ifeq ($(TEST_APP), pwm) +include source/test/pwm/pwm.mk +endif From 969d35919e11faf02c063347532d5995194c3314 Mon Sep 17 00:00:00 2001 From: tkl Date: Tue, 9 Aug 2016 10:43:47 +0200 Subject: [PATCH 2/8] wip --- source/test/pwm/main.c | 146 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) diff --git a/source/test/pwm/main.c b/source/test/pwm/main.c index 343676f..6e381a3 100644 --- a/source/test/pwm/main.c +++ b/source/test/pwm/main.c @@ -16,17 +16,163 @@ #include "list.h" #include "shell.h" +#include "stm32f4xx.h" + +struct stm32f4_pwm { + TIM_TypeDef *timer; + const TIM_TimeBaseInitTypeDef *timer_cfg; + const TIM_OCInitTypeDef *output_compare_cfg; + const TIM_BDTRInitTypeDef *bdtr_cfg; + GPIO_TypeDef *port; + uint8_t pin_src; + const GPIO_InitTypeDef *port_cfg; +}; + +static const TIM_TimeBaseInitTypeDef timer_4_cfg = { + .TIM_RepetitionCounter = 0x0000, + .TIM_Prescaler = ((168000000 / 2 ) / 1000000) - 1, + .TIM_ClockDivision = TIM_CKD_DIV1, + .TIM_CounterMode = TIM_CounterMode_Up, + .TIM_Period = 20000 +}; + +static const TIM_OCInitTypeDef t4_output_compare_cfg = { + .TIM_OutputNState = TIM_OutputNState_Disable, + .TIM_OCNPolarity = TIM_OCPolarity_High, + .TIM_OCIdleState = TIM_OCIdleState_Reset, + .TIM_OCNIdleState = TIM_OCNIdleState_Set, + .TIM_OCMode = TIM_OCMode_PWM1, + .TIM_OCPolarity = TIM_OCPolarity_High, + .TIM_OutputState = TIM_OutputState_Enable, + .TIM_Pulse = 1500 // Initiale Pulsweite in Millisekunden +}; + +static const TIM_BDTRInitTypeDef t4_bdtr_cfg = { + .TIM_OSSRState = TIM_OSSRState_Disable, + .TIM_OSSIState = TIM_OSSIState_Disable, + .TIM_LOCKLevel = TIM_LOCKLevel_OFF, + .TIM_DeadTime = 0x00, + .TIM_Break = TIM_Break_Disable, + .TIM_BreakPolarity = TIM_BreakPolarity_Low, + .TIM_AutomaticOutput = TIM_AutomaticOutput_Disable, + + + .TIM_AutomaticOutput = TIM_AutomaticOutput_Enable, +}; + +static const GPIO_InitTypeDef port_cfg = { + .GPIO_Pin = GPIO_Pin_12, + .GPIO_Mode = GPIO_Mode_AF, + .GPIO_OType = GPIO_OType_PP, + .GPIO_PuPd = GPIO_PuPd_UP, + .GPIO_Speed = GPIO_Speed_50MHz, +}; + +static struct stm32f4_pwm str32f4_pwm = { + .timer = TIM4, + .timer_cfg = &timer_4_cfg, + .output_compare_cfg = &t4_output_compare_cfg, + .bdtr_cfg = &t4_bdtr_cfg, + .port = GPIOD, + .pin_src = GPIO_PinSource12, + .port_cfg = &port_cfg, +}; + +extern uint32_t SystemCoreClock; +void pwm_open(struct stm32f4_pwm *pwm) +{ + TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; + TIM_OCInitTypeDef TIM_OCInitStructure; + + /* TIM config */ + GPIO_InitTypeDef GPIO_InitStructure; + + /* TIM4 clock enable */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE); + + /* LEDs are on GPIOD */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_TIM4); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource13, GPIO_AF_TIM4); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_TIM4); + GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_TIM4); + + /* pwm set up */ + /* Compute the prescaler value */ + uint16_t PrescalerValue = (uint16_t) ((SystemCoreClock /2) / 21000000) - 1; + + /* apb1 clock = 84MHz */ + /* period_reg = src_clk / presc / cnt_clk */ + /* 4199 = 84MHZ / (0 + 1) / 20kHz - 1 */ + + /* Time base configuration */ + TIM_TimeBaseStructure.TIM_Period = 4199;//665; + TIM_TimeBaseStructure.TIM_Prescaler = 0;//PrescalerValue; + TIM_TimeBaseStructure.TIM_ClockDivision = 1; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure); + + /* PWM1 Mode configuration: Channel1 */ + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = 0; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OC1Init(TIM4, &TIM_OCInitStructure); + TIM_OC1PreloadConfig(TIM4, TIM_OCPreload_Enable); + + /* PWM1 Mode configuration: Channel2 */ + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = 0; + TIM_OC2Init(TIM4, &TIM_OCInitStructure); + TIM_OC2PreloadConfig(TIM4, TIM_OCPreload_Enable); + + /* PWM1 Mode configuration: Channel3 */ + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = 0; + TIM_OC3Init(TIM4, &TIM_OCInitStructure); + TIM_OC3PreloadConfig(TIM4, TIM_OCPreload_Enable); + + /* PWM1 Mode configuration: Channel4 */ + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OCInitStructure.TIM_Pulse = 0; + TIM_OC4Init(TIM4, &TIM_OCInitStructure); + TIM_OC4PreloadConfig(TIM4, TIM_OCPreload_Enable); + TIM_ARRPreloadConfig(TIM4, ENABLE); + + /* TIM4 enable counter */ + TIM_Cmd(TIM4, ENABLE); +} + #define TH_STACK_SIZE 256 stack_t th_stack[TH_STACK_SIZE]; struct thread_context th_ctx; static void th_func(void *arg) { + uint32_t brightness = 4200 / 2; + TIM4->CCR4 = brightness; while(1) { + brightness++; + if(brightness == UINT32_MAX) + brightness = 0; +#if 0 + TIM4->CCR3 = 333 - (brightness + 0) % 333; // set brightness + TIM4->CCR4 = 333 - (brightness + 166/2) % 333; // set brightness + TIM4->CCR1 = 333 - (brightness + 333/2) % 333; // set brightness + TIM4->CCR2 = 333 - (brightness + 499/2) % 333; // set brightness +#endif + sleep_ms(1); } } int main(void) { + pwm_open(&str32f4_pwm); thread_create(&th_ctx, th_stack, TH_STACK_SIZE, th_func, NULL, THREAD_PRIO_LOW); schedule_start(); From c44104b301330df42b0e9eb39e882fd78ddb7bf6 Mon Sep 17 00:00:00 2001 From: tkl Date: Tue, 9 Aug 2016 11:20:33 +0200 Subject: [PATCH 3/8] wip --- source/test/pwm/main.c | 133 ++++++++++++++++------------------------- 1 file changed, 52 insertions(+), 81 deletions(-) diff --git a/source/test/pwm/main.c b/source/test/pwm/main.c index 6e381a3..fde0061 100644 --- a/source/test/pwm/main.c +++ b/source/test/pwm/main.c @@ -18,6 +18,13 @@ #include "stm32f4xx.h" +enum stm32f4_pwm_channel { + channel_1 = 1, + channel_2, + channel_3, + channel_4 +}; + struct stm32f4_pwm { TIM_TypeDef *timer; const TIM_TimeBaseInitTypeDef *timer_cfg; @@ -26,14 +33,18 @@ struct stm32f4_pwm { GPIO_TypeDef *port; uint8_t pin_src; const GPIO_InitTypeDef *port_cfg; + enum stm32f4_pwm_channel channel; }; +/* apb1 clock = 84MHz */ +/* period_reg = src_clk / presc / cnt_clk */ +/* 4199 = 84MHZ / (0 + 1) / 20kHz - 1 */ static const TIM_TimeBaseInitTypeDef timer_4_cfg = { .TIM_RepetitionCounter = 0x0000, - .TIM_Prescaler = ((168000000 / 2 ) / 1000000) - 1, + .TIM_Prescaler = 0, .TIM_ClockDivision = TIM_CKD_DIV1, .TIM_CounterMode = TIM_CounterMode_Up, - .TIM_Period = 20000 + .TIM_Period = 4199 }; static const TIM_OCInitTypeDef t4_output_compare_cfg = { @@ -44,109 +55,69 @@ static const TIM_OCInitTypeDef t4_output_compare_cfg = { .TIM_OCMode = TIM_OCMode_PWM1, .TIM_OCPolarity = TIM_OCPolarity_High, .TIM_OutputState = TIM_OutputState_Enable, - .TIM_Pulse = 1500 // Initiale Pulsweite in Millisekunden -}; - -static const TIM_BDTRInitTypeDef t4_bdtr_cfg = { - .TIM_OSSRState = TIM_OSSRState_Disable, - .TIM_OSSIState = TIM_OSSIState_Disable, - .TIM_LOCKLevel = TIM_LOCKLevel_OFF, - .TIM_DeadTime = 0x00, - .TIM_Break = TIM_Break_Disable, - .TIM_BreakPolarity = TIM_BreakPolarity_Low, - .TIM_AutomaticOutput = TIM_AutomaticOutput_Disable, - - - .TIM_AutomaticOutput = TIM_AutomaticOutput_Enable, + .TIM_Pulse = 0 // Initiale Pulsweite in Millisekunden }; static const GPIO_InitTypeDef port_cfg = { - .GPIO_Pin = GPIO_Pin_12, + .GPIO_Pin = GPIO_Pin_15, .GPIO_Mode = GPIO_Mode_AF, .GPIO_OType = GPIO_OType_PP, .GPIO_PuPd = GPIO_PuPd_UP, - .GPIO_Speed = GPIO_Speed_50MHz, + .GPIO_Speed = GPIO_Speed_100MHz, }; static struct stm32f4_pwm str32f4_pwm = { .timer = TIM4, .timer_cfg = &timer_4_cfg, .output_compare_cfg = &t4_output_compare_cfg, - .bdtr_cfg = &t4_bdtr_cfg, .port = GPIOD, - .pin_src = GPIO_PinSource12, + .pin_src = GPIO_PinSource15, .port_cfg = &port_cfg, + .channel = channel_4, }; extern uint32_t SystemCoreClock; void pwm_open(struct stm32f4_pwm *pwm) { - TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; - TIM_OCInitTypeDef TIM_OCInitStructure; - - /* TIM config */ - GPIO_InitTypeDef GPIO_InitStructure; - - /* TIM4 clock enable */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE); + uint32_t clk_ahb_timer = 0, clk_ahb_gpio = 0; + uint8_t gpio_af_timer = 0; + if(pwm->timer == TIM4) { + clk_ahb_timer = RCC_APB1Periph_TIM4; + gpio_af_timer = GPIO_AF_TIM4; + } + RCC_APB1PeriphClockCmd(clk_ahb_timer, ENABLE); + if(pwm->port == GPIOD) { + clk_ahb_gpio = RCC_AHB1Periph_GPIOD; + } /* LEDs are on GPIOD */ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; - GPIO_Init(GPIOD, &GPIO_InitStructure); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_TIM4); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource13, GPIO_AF_TIM4); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_TIM4); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_TIM4); - - /* pwm set up */ - /* Compute the prescaler value */ - uint16_t PrescalerValue = (uint16_t) ((SystemCoreClock /2) / 21000000) - 1; - - /* apb1 clock = 84MHz */ - /* period_reg = src_clk / presc / cnt_clk */ - /* 4199 = 84MHZ / (0 + 1) / 20kHz - 1 */ + RCC_AHB1PeriphClockCmd(clk_ahb_gpio, ENABLE); + GPIO_Init(pwm->port, (GPIO_InitTypeDef *)pwm->port_cfg); + GPIO_PinAFConfig(pwm->port, pwm->pin_src, gpio_af_timer); /* Time base configuration */ - TIM_TimeBaseStructure.TIM_Period = 4199;//665; - TIM_TimeBaseStructure.TIM_Prescaler = 0;//PrescalerValue; - TIM_TimeBaseStructure.TIM_ClockDivision = 1; - TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure); + TIM_TimeBaseInit(pwm->timer, (TIM_TimeBaseInitTypeDef *)pwm->timer_cfg); - /* PWM1 Mode configuration: Channel1 */ - TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; - TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; - TIM_OCInitStructure.TIM_Pulse = 0; - TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OC1Init(TIM4, &TIM_OCInitStructure); - TIM_OC1PreloadConfig(TIM4, TIM_OCPreload_Enable); - - /* PWM1 Mode configuration: Channel2 */ - TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; - TIM_OCInitStructure.TIM_Pulse = 0; - TIM_OC2Init(TIM4, &TIM_OCInitStructure); - TIM_OC2PreloadConfig(TIM4, TIM_OCPreload_Enable); - - /* PWM1 Mode configuration: Channel3 */ - TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; - TIM_OCInitStructure.TIM_Pulse = 0; - TIM_OC3Init(TIM4, &TIM_OCInitStructure); - TIM_OC3PreloadConfig(TIM4, TIM_OCPreload_Enable); - - /* PWM1 Mode configuration: Channel4 */ - TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; - TIM_OCInitStructure.TIM_Pulse = 0; - TIM_OC4Init(TIM4, &TIM_OCInitStructure); - TIM_OC4PreloadConfig(TIM4, TIM_OCPreload_Enable); - TIM_ARRPreloadConfig(TIM4, ENABLE); - - /* TIM4 enable counter */ - TIM_Cmd(TIM4, ENABLE); + switch(pwm->channel) { + case channel_1: + TIM_OC1Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg); + TIM_OC1PreloadConfig(pwm->timer, TIM_OCPreload_Enable); + break; + case channel_2: + TIM_OC2Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg); + TIM_OC2PreloadConfig(pwm->timer, TIM_OCPreload_Enable); + break; + case channel_3: + TIM_OC3Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg); + TIM_OC3PreloadConfig(pwm->timer, TIM_OCPreload_Enable); + break; + case channel_4: + TIM_OC4Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg); + TIM_OC4PreloadConfig(pwm->timer, TIM_OCPreload_Enable); + break; + } + TIM_ARRPreloadConfig(pwm->timer, ENABLE); + TIM_Cmd(pwm->timer, ENABLE); } #define TH_STACK_SIZE 256 From d14354e47c046f261bc73fee0931bb2de3b9d931 Mon Sep 17 00:00:00 2001 From: tkl Date: Tue, 9 Aug 2016 11:57:54 +0200 Subject: [PATCH 4/8] wip --- .../stm32f4xx/driver/include/stm32f4_pwm.h | 34 +++++++ .../arch/stm32f4xx/driver/stm32f4_pwm.c | 99 +++++++++++++++++++ source/test/pwm/main.c | 82 ++------------- 3 files changed, 141 insertions(+), 74 deletions(-) create mode 100644 source/firmware/arch/stm32f4xx/driver/include/stm32f4_pwm.h create mode 100644 source/firmware/arch/stm32f4xx/driver/stm32f4_pwm.c diff --git a/source/firmware/arch/stm32f4xx/driver/include/stm32f4_pwm.h b/source/firmware/arch/stm32f4xx/driver/include/stm32f4_pwm.h new file mode 100644 index 0000000..2e1dff4 --- /dev/null +++ b/source/firmware/arch/stm32f4xx/driver/include/stm32f4_pwm.h @@ -0,0 +1,34 @@ +/* + * stm32f4_pwm.h + * + * Created on: Aug 9, 2016 + * Author: tkl + */ + +#ifndef SOURCE_FIRMWARE_ARCH_STM32F4XX_DRIVER_INCLUDE_STM32F4_PWM_H_ +#define SOURCE_FIRMWARE_ARCH_STM32F4XX_DRIVER_INCLUDE_STM32F4_PWM_H_ + +enum stm32f4_pwm_channel { + channel_1 = 1, + channel_2, + channel_3, + channel_4 +}; + +struct stm32f4_pwm { + TIM_TypeDef *timer; + const TIM_TimeBaseInitTypeDef *timer_cfg; + const TIM_OCInitTypeDef *output_compare_cfg; + const TIM_BDTRInitTypeDef *bdtr_cfg; + GPIO_TypeDef *port; + uint8_t pin_src; + const GPIO_InitTypeDef *port_cfg; + enum stm32f4_pwm_channel channel; +}; + + +int stm32f4_pwm_open(struct stm32f4_pwm *pwm); +int stm32f4_pwm_close(struct stm32f4_pwm *pwm); +int stm32f4_pwm_set_duty_cycle(struct stm32f4_pwm *pwm, unsigned int duty_cycle_percent); + +#endif /* SOURCE_FIRMWARE_ARCH_STM32F4XX_DRIVER_INCLUDE_STM32F4_PWM_H_ */ diff --git a/source/firmware/arch/stm32f4xx/driver/stm32f4_pwm.c b/source/firmware/arch/stm32f4xx/driver/stm32f4_pwm.c new file mode 100644 index 0000000..8b8505d --- /dev/null +++ b/source/firmware/arch/stm32f4xx/driver/stm32f4_pwm.c @@ -0,0 +1,99 @@ +/* + * stm32f4_pwm.c + * + * Created on: Aug 9, 2016 + * Author: tkl + */ +#include + +#include "stm32f4xx.h" +#include "stm32f4_pwm.h" + +struct stm32f4_pwm_object { + uint8_t used_channels; + uint32_t channel_1_max_period; + uint32_t channel_2_max_period; + uint32_t channel_3_max_period; + uint32_t channel_4_max_period; +}; + +static struct stm32f4_pwm_object stm32f4_pwm_object = { + .used_channels = 0, + .channel_1_max_period = 0, + .channel_2_max_period = 0, + .channel_3_max_period = 0, + .channel_4_max_period = 0, +}; + +int stm32f4_pwm_open(struct stm32f4_pwm *pwm) +{ + uint32_t clk_ahb_timer = 0, clk_ahb_gpio = 0; + uint8_t gpio_af_timer = 0; + if(pwm->timer == TIM4) { + clk_ahb_timer = RCC_APB1Periph_TIM4; + gpio_af_timer = GPIO_AF_TIM4; + } + RCC_APB1PeriphClockCmd(clk_ahb_timer, ENABLE); + if(pwm->port == GPIOD) { + clk_ahb_gpio = RCC_AHB1Periph_GPIOD; + } + RCC_AHB1PeriphClockCmd(clk_ahb_gpio, ENABLE); + GPIO_Init(pwm->port, (GPIO_InitTypeDef *)pwm->port_cfg); + GPIO_PinAFConfig(pwm->port, pwm->pin_src, gpio_af_timer); + + TIM_TimeBaseInit(pwm->timer, (TIM_TimeBaseInitTypeDef *)pwm->timer_cfg); + + switch(pwm->channel) { + case channel_1: + TIM_OC1Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg); + TIM_OC1PreloadConfig(pwm->timer, TIM_OCPreload_Enable); + stm32f4_pwm_object.channel_1_max_period = pwm->timer_cfg->TIM_Period + 1; + break; + case channel_2: + TIM_OC2Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg); + TIM_OC2PreloadConfig(pwm->timer, TIM_OCPreload_Enable); + stm32f4_pwm_object.channel_2_max_period = pwm->timer_cfg->TIM_Period + 1; + break; + case channel_3: + TIM_OC3Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg); + TIM_OC3PreloadConfig(pwm->timer, TIM_OCPreload_Enable); + stm32f4_pwm_object.channel_3_max_period = pwm->timer_cfg->TIM_Period + 1; + break; + case channel_4: + TIM_OC4Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg); + TIM_OC4PreloadConfig(pwm->timer, TIM_OCPreload_Enable); + stm32f4_pwm_object.channel_4_max_period = pwm->timer_cfg->TIM_Period + 1; + break; + } + TIM_ARRPreloadConfig(pwm->timer, ENABLE); + TIM_Cmd(pwm->timer, ENABLE); + stm32f4_pwm_object.used_channels++; + return 0; +} + +int stm32f4_pwm_close(struct stm32f4_pwm *pwm) +{ + stm32f4_pwm_object.used_channels--; + if(stm32f4_pwm_object.used_channels == 0) { + TIM_Cmd(pwm->timer, DISABLE); + } + return 0; +} + +int stm32f4_pwm_set_duty_cycle(struct stm32f4_pwm *pwm, unsigned int duty_cycle_percent) +{ + switch(pwm->channel) { + case channel_1: + TIM_SetCompare1(pwm->timer, stm32f4_pwm_object.channel_1_max_period * duty_cycle_percent / 100); + break; + case channel_2: + TIM_SetCompare2(pwm->timer, stm32f4_pwm_object.channel_2_max_period * duty_cycle_percent / 100); + break; + case channel_3: + TIM_SetCompare3(pwm->timer, stm32f4_pwm_object.channel_3_max_period * duty_cycle_percent / 100); + break; + case channel_4: + TIM_SetCompare4(pwm->timer, stm32f4_pwm_object.channel_4_max_period * duty_cycle_percent / 100); + break; + } +} diff --git a/source/test/pwm/main.c b/source/test/pwm/main.c index fde0061..edcbf59 100644 --- a/source/test/pwm/main.c +++ b/source/test/pwm/main.c @@ -17,24 +17,7 @@ #include "shell.h" #include "stm32f4xx.h" - -enum stm32f4_pwm_channel { - channel_1 = 1, - channel_2, - channel_3, - channel_4 -}; - -struct stm32f4_pwm { - TIM_TypeDef *timer; - const TIM_TimeBaseInitTypeDef *timer_cfg; - const TIM_OCInitTypeDef *output_compare_cfg; - const TIM_BDTRInitTypeDef *bdtr_cfg; - GPIO_TypeDef *port; - uint8_t pin_src; - const GPIO_InitTypeDef *port_cfg; - enum stm32f4_pwm_channel channel; -}; +#include "stm32f4_pwm.h" /* apb1 clock = 84MHz */ /* period_reg = src_clk / presc / cnt_clk */ @@ -76,74 +59,25 @@ static struct stm32f4_pwm str32f4_pwm = { .channel = channel_4, }; -extern uint32_t SystemCoreClock; -void pwm_open(struct stm32f4_pwm *pwm) -{ - - uint32_t clk_ahb_timer = 0, clk_ahb_gpio = 0; - uint8_t gpio_af_timer = 0; - if(pwm->timer == TIM4) { - clk_ahb_timer = RCC_APB1Periph_TIM4; - gpio_af_timer = GPIO_AF_TIM4; - } - RCC_APB1PeriphClockCmd(clk_ahb_timer, ENABLE); - if(pwm->port == GPIOD) { - clk_ahb_gpio = RCC_AHB1Periph_GPIOD; - } - /* LEDs are on GPIOD */ - RCC_AHB1PeriphClockCmd(clk_ahb_gpio, ENABLE); - GPIO_Init(pwm->port, (GPIO_InitTypeDef *)pwm->port_cfg); - GPIO_PinAFConfig(pwm->port, pwm->pin_src, gpio_af_timer); - - /* Time base configuration */ - TIM_TimeBaseInit(pwm->timer, (TIM_TimeBaseInitTypeDef *)pwm->timer_cfg); - - switch(pwm->channel) { - case channel_1: - TIM_OC1Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg); - TIM_OC1PreloadConfig(pwm->timer, TIM_OCPreload_Enable); - break; - case channel_2: - TIM_OC2Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg); - TIM_OC2PreloadConfig(pwm->timer, TIM_OCPreload_Enable); - break; - case channel_3: - TIM_OC3Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg); - TIM_OC3PreloadConfig(pwm->timer, TIM_OCPreload_Enable); - break; - case channel_4: - TIM_OC4Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg); - TIM_OC4PreloadConfig(pwm->timer, TIM_OCPreload_Enable); - break; - } - TIM_ARRPreloadConfig(pwm->timer, ENABLE); - TIM_Cmd(pwm->timer, ENABLE); -} #define TH_STACK_SIZE 256 stack_t th_stack[TH_STACK_SIZE]; struct thread_context th_ctx; static void th_func(void *arg) { - uint32_t brightness = 4200 / 2; - TIM4->CCR4 = brightness; + unsigned int duty = 0; while(1) { - brightness++; - if(brightness == UINT32_MAX) - brightness = 0; -#if 0 - TIM4->CCR3 = 333 - (brightness + 0) % 333; // set brightness - TIM4->CCR4 = 333 - (brightness + 166/2) % 333; // set brightness - TIM4->CCR1 = 333 - (brightness + 333/2) % 333; // set brightness - TIM4->CCR2 = 333 - (brightness + 499/2) % 333; // set brightness -#endif - sleep_ms(1); + stm32f4_pwm_set_duty_cycle(&str32f4_pwm, duty); + sleep_ms(100); + duty++; + if(duty > 100) + duty = 0; } } int main(void) { - pwm_open(&str32f4_pwm); + stm32f4_pwm_open(&str32f4_pwm); thread_create(&th_ctx, th_stack, TH_STACK_SIZE, th_func, NULL, THREAD_PRIO_LOW); schedule_start(); From b80a44a4d9ccfea418be75185383be9ab14b10cc Mon Sep 17 00:00:00 2001 From: tkl Date: Tue, 9 Aug 2016 12:28:01 +0200 Subject: [PATCH 5/8] wip --- .../stm32f4xx/driver/include/stm32f4_pwm.h | 12 +++- .../arch/stm32f4xx/driver/stm32f4_pwm.c | 72 +++++++++++-------- source/firmware/kernel/driver/include/pwm.h | 35 +++++++++ source/firmware/kernel/driver/pwm.c | 33 +++++++++ source/test/pwm/main.c | 10 ++- 5 files changed, 128 insertions(+), 34 deletions(-) create mode 100644 source/firmware/kernel/driver/include/pwm.h create mode 100644 source/firmware/kernel/driver/pwm.c diff --git a/source/firmware/arch/stm32f4xx/driver/include/stm32f4_pwm.h b/source/firmware/arch/stm32f4xx/driver/include/stm32f4_pwm.h index 2e1dff4..c46174f 100644 --- a/source/firmware/arch/stm32f4xx/driver/include/stm32f4_pwm.h +++ b/source/firmware/arch/stm32f4xx/driver/include/stm32f4_pwm.h @@ -27,8 +27,14 @@ struct stm32f4_pwm { }; -int stm32f4_pwm_open(struct stm32f4_pwm *pwm); -int stm32f4_pwm_close(struct stm32f4_pwm *pwm); -int stm32f4_pwm_set_duty_cycle(struct stm32f4_pwm *pwm, unsigned int duty_cycle_percent); +int stm32f4_pwm_open(const void *pwm); +int stm32f4_pwm_close(const void *pwm); +int stm32f4_pwm_set_duty_cycle(const void *pwm, unsigned int duty_cycle_percent); + +static const struct pwm_fp stm32f4_pwm_fp = { + .open = stm32f4_pwm_open, + .close = stm32f4_pwm_close, + .set_duty_cycle = stm32f4_pwm_set_duty_cycle, +}; #endif /* SOURCE_FIRMWARE_ARCH_STM32F4XX_DRIVER_INCLUDE_STM32F4_PWM_H_ */ diff --git a/source/firmware/arch/stm32f4xx/driver/stm32f4_pwm.c b/source/firmware/arch/stm32f4xx/driver/stm32f4_pwm.c index 8b8505d..80faa5d 100644 --- a/source/firmware/arch/stm32f4xx/driver/stm32f4_pwm.c +++ b/source/firmware/arch/stm32f4xx/driver/stm32f4_pwm.c @@ -5,8 +5,11 @@ * Author: tkl */ #include +#include #include "stm32f4xx.h" + +#include "pwm.h" #include "stm32f4_pwm.h" struct stm32f4_pwm_object { @@ -25,75 +28,86 @@ static struct stm32f4_pwm_object stm32f4_pwm_object = { .channel_4_max_period = 0, }; -int stm32f4_pwm_open(struct stm32f4_pwm *pwm) +int stm32f4_pwm_open(const void *pwm) { + if(NULL == pwm) + return -1; + struct stm32f4_pwm *this = (struct stm32f4_pwm *)pwm; uint32_t clk_ahb_timer = 0, clk_ahb_gpio = 0; uint8_t gpio_af_timer = 0; - if(pwm->timer == TIM4) { + if(this->timer == TIM4) { clk_ahb_timer = RCC_APB1Periph_TIM4; gpio_af_timer = GPIO_AF_TIM4; } RCC_APB1PeriphClockCmd(clk_ahb_timer, ENABLE); - if(pwm->port == GPIOD) { + if(this->port == GPIOD) { clk_ahb_gpio = RCC_AHB1Periph_GPIOD; } RCC_AHB1PeriphClockCmd(clk_ahb_gpio, ENABLE); - GPIO_Init(pwm->port, (GPIO_InitTypeDef *)pwm->port_cfg); - GPIO_PinAFConfig(pwm->port, pwm->pin_src, gpio_af_timer); + GPIO_Init(this->port, (GPIO_InitTypeDef *)this->port_cfg); + GPIO_PinAFConfig(this->port, this->pin_src, gpio_af_timer); - TIM_TimeBaseInit(pwm->timer, (TIM_TimeBaseInitTypeDef *)pwm->timer_cfg); + TIM_TimeBaseInit(this->timer, (TIM_TimeBaseInitTypeDef *)this->timer_cfg); - switch(pwm->channel) { + switch(this->channel) { case channel_1: - TIM_OC1Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg); - TIM_OC1PreloadConfig(pwm->timer, TIM_OCPreload_Enable); - stm32f4_pwm_object.channel_1_max_period = pwm->timer_cfg->TIM_Period + 1; + TIM_OC1Init(this->timer, (TIM_OCInitTypeDef *)this->output_compare_cfg); + TIM_OC1PreloadConfig(this->timer, TIM_OCPreload_Enable); + stm32f4_pwm_object.channel_1_max_period = this->timer_cfg->TIM_Period + 1; break; case channel_2: - TIM_OC2Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg); - TIM_OC2PreloadConfig(pwm->timer, TIM_OCPreload_Enable); - stm32f4_pwm_object.channel_2_max_period = pwm->timer_cfg->TIM_Period + 1; + TIM_OC2Init(this->timer, (TIM_OCInitTypeDef *)this->output_compare_cfg); + TIM_OC2PreloadConfig(this->timer, TIM_OCPreload_Enable); + stm32f4_pwm_object.channel_2_max_period = this->timer_cfg->TIM_Period + 1; break; case channel_3: - TIM_OC3Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg); - TIM_OC3PreloadConfig(pwm->timer, TIM_OCPreload_Enable); - stm32f4_pwm_object.channel_3_max_period = pwm->timer_cfg->TIM_Period + 1; + TIM_OC3Init(this->timer, (TIM_OCInitTypeDef *)this->output_compare_cfg); + TIM_OC3PreloadConfig(this->timer, TIM_OCPreload_Enable); + stm32f4_pwm_object.channel_3_max_period = this->timer_cfg->TIM_Period + 1; break; case channel_4: - TIM_OC4Init(pwm->timer, (TIM_OCInitTypeDef *)pwm->output_compare_cfg); - TIM_OC4PreloadConfig(pwm->timer, TIM_OCPreload_Enable); - stm32f4_pwm_object.channel_4_max_period = pwm->timer_cfg->TIM_Period + 1; + TIM_OC4Init(this->timer, (TIM_OCInitTypeDef *)this->output_compare_cfg); + TIM_OC4PreloadConfig(this->timer, TIM_OCPreload_Enable); + stm32f4_pwm_object.channel_4_max_period = this->timer_cfg->TIM_Period + 1; break; } - TIM_ARRPreloadConfig(pwm->timer, ENABLE); - TIM_Cmd(pwm->timer, ENABLE); + TIM_ARRPreloadConfig(this->timer, ENABLE); + TIM_Cmd(this->timer, ENABLE); stm32f4_pwm_object.used_channels++; return 0; } -int stm32f4_pwm_close(struct stm32f4_pwm *pwm) +int stm32f4_pwm_close(const void *pwm) { + if(NULL == pwm) + return -1; + struct stm32f4_pwm *this = (struct stm32f4_pwm *)pwm; + stm32f4_pwm_set_duty_cycle(pwm, 0); stm32f4_pwm_object.used_channels--; if(stm32f4_pwm_object.used_channels == 0) { - TIM_Cmd(pwm->timer, DISABLE); + TIM_Cmd(this->timer, DISABLE); } return 0; } -int stm32f4_pwm_set_duty_cycle(struct stm32f4_pwm *pwm, unsigned int duty_cycle_percent) +int stm32f4_pwm_set_duty_cycle(const void *pwm, unsigned int duty_cycle_percent) { - switch(pwm->channel) { + if(NULL == pwm) + return -1; + struct stm32f4_pwm *this = (struct stm32f4_pwm *)pwm; + switch(this->channel) { case channel_1: - TIM_SetCompare1(pwm->timer, stm32f4_pwm_object.channel_1_max_period * duty_cycle_percent / 100); + TIM_SetCompare1(this->timer, stm32f4_pwm_object.channel_1_max_period * duty_cycle_percent / 100); break; case channel_2: - TIM_SetCompare2(pwm->timer, stm32f4_pwm_object.channel_2_max_period * duty_cycle_percent / 100); + TIM_SetCompare2(this->timer, stm32f4_pwm_object.channel_2_max_period * duty_cycle_percent / 100); break; case channel_3: - TIM_SetCompare3(pwm->timer, stm32f4_pwm_object.channel_3_max_period * duty_cycle_percent / 100); + TIM_SetCompare3(this->timer, stm32f4_pwm_object.channel_3_max_period * duty_cycle_percent / 100); break; case channel_4: - TIM_SetCompare4(pwm->timer, stm32f4_pwm_object.channel_4_max_period * duty_cycle_percent / 100); + TIM_SetCompare4(this->timer, stm32f4_pwm_object.channel_4_max_period * duty_cycle_percent / 100); break; } + return 0; } diff --git a/source/firmware/kernel/driver/include/pwm.h b/source/firmware/kernel/driver/include/pwm.h new file mode 100644 index 0000000..6d1d883 --- /dev/null +++ b/source/firmware/kernel/driver/include/pwm.h @@ -0,0 +1,35 @@ +/* + * pwm.h + * + * Created on: Aug 9, 2016 + * Author: tkl + */ + +#ifndef SOURCE_FIRMWARE_KERNEL_DRIVER_INCLUDE_PWM_H_ +#define SOURCE_FIRMWARE_KERNEL_DRIVER_INCLUDE_PWM_H_ + +//! \brief Function pointer to the open function. +typedef int (*pwm_fp_open_t)(const void*); + +//! \brief Function pointer to the close function. +typedef int (*pwm_fp_close_t)(const void*); + +//! \brief Function pointer to the read function. +typedef int (*pwm_fp_set_duty_cycle_t)(const void*, unsigned int duty_cycle_percent); + +struct pwm_fp { + const pwm_fp_open_t open; + const pwm_fp_close_t close; + const pwm_fp_set_duty_cycle_t set_duty_cycle; +}; + +struct pwm { + const void *arch_dep_device; //!< Architecture depended pwm device (i.e. stm32f10x_pwm_t). + const struct pwm_fp *fp; //!< Function pointer for the pwm driver access. +}; + +int pwm_open(const struct pwm *device); +int pwm_close(const struct pwm *device); +int pwm_set_duty_cycle(const struct pwm *device, unsigned int duty_cycle_percent); + +#endif /* SOURCE_FIRMWARE_KERNEL_DRIVER_INCLUDE_PWM_H_ */ diff --git a/source/firmware/kernel/driver/pwm.c b/source/firmware/kernel/driver/pwm.c new file mode 100644 index 0000000..a8e733e --- /dev/null +++ b/source/firmware/kernel/driver/pwm.c @@ -0,0 +1,33 @@ +/* + * pwm.c + * + * Created on: Aug 9, 2016 + * Author: tkl + */ + +#include +#include + +int pwm_open(const struct pwm *device) +{ + if(NULL == device) + return -1; + pwm_fp_open_t open = device->fp->open; + return open(device->arch_dep_device); +} + +int pwm_close(const struct pwm *device) +{ + if(NULL == device) + return -1; + pwm_fp_close_t close = device->fp->close; + return close(device->arch_dep_device); +} + +int pwm_set_duty_cycle(const struct pwm *device, unsigned int duty_cycle_percent) +{ + if(NULL == device) + return -1; + pwm_fp_set_duty_cycle_t set = device->fp->set_duty_cycle; + return set(device->arch_dep_device, duty_cycle_percent); +} diff --git a/source/test/pwm/main.c b/source/test/pwm/main.c index edcbf59..9ad07bd 100644 --- a/source/test/pwm/main.c +++ b/source/test/pwm/main.c @@ -17,6 +17,8 @@ #include "shell.h" #include "stm32f4xx.h" + +#include "pwm.h" #include "stm32f4_pwm.h" /* apb1 clock = 84MHz */ @@ -59,6 +61,10 @@ static struct stm32f4_pwm str32f4_pwm = { .channel = channel_4, }; +static const struct pwm pwm_ch4 = { + .arch_dep_device = &str32f4_pwm, + .fp = &stm32f4_pwm_fp, +}; #define TH_STACK_SIZE 256 stack_t th_stack[TH_STACK_SIZE]; @@ -66,8 +72,9 @@ struct thread_context th_ctx; static void th_func(void *arg) { unsigned int duty = 0; + pwm_open(&pwm_ch4); while(1) { - stm32f4_pwm_set_duty_cycle(&str32f4_pwm, duty); + pwm_set_duty_cycle(&pwm_ch4, duty); sleep_ms(100); duty++; if(duty > 100) @@ -77,7 +84,6 @@ static void th_func(void *arg) int main(void) { - stm32f4_pwm_open(&str32f4_pwm); thread_create(&th_ctx, th_stack, TH_STACK_SIZE, th_func, NULL, THREAD_PRIO_LOW); schedule_start(); From 461f219b085e60a46d1cb614e8a37cfd6938eadc Mon Sep 17 00:00:00 2001 From: tkl Date: Tue, 9 Aug 2016 12:32:19 +0200 Subject: [PATCH 6/8] wip --- source/test/pwm/main.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/source/test/pwm/main.c b/source/test/pwm/main.c index 9ad07bd..b9150fa 100644 --- a/source/test/pwm/main.c +++ b/source/test/pwm/main.c @@ -74,11 +74,16 @@ static void th_func(void *arg) unsigned int duty = 0; pwm_open(&pwm_ch4); while(1) { - pwm_set_duty_cycle(&pwm_ch4, duty); - sleep_ms(100); - duty++; - if(duty > 100) - duty = 0; + while(duty < 100) { + pwm_set_duty_cycle(&pwm_ch4, duty); + sleep_ms(10); + duty++; + } + while(duty > 0) { + pwm_set_duty_cycle(&pwm_ch4, duty); + sleep_ms(10); + duty--; + } } } From 2f13f30b3d954a646a1384692d9b06189930489b Mon Sep 17 00:00:00 2001 From: tkl Date: Tue, 9 Aug 2016 12:35:56 +0200 Subject: [PATCH 7/8] wip --- .../include/stm32f4-discovery.h | 50 +++++++++++++++++++ source/test/pwm/main.c | 50 ------------------- 2 files changed, 50 insertions(+), 50 deletions(-) diff --git a/source/firmware/arch/stm32f4xx/board/stm32f4-discovery/include/stm32f4-discovery.h b/source/firmware/arch/stm32f4xx/board/stm32f4-discovery/include/stm32f4-discovery.h index 81faad3..e6a7408 100755 --- a/source/firmware/arch/stm32f4xx/board/stm32f4-discovery/include/stm32f4-discovery.h +++ b/source/firmware/arch/stm32f4xx/board/stm32f4-discovery/include/stm32f4-discovery.h @@ -13,15 +13,18 @@ #include "driver.h" #include "gpio.h" +#include "pwm.h" #include "timer.h" #include "uart.h" #include "ringbuffer.h" #include "sys_tick.h" #include "stm32f4xx.h" #include "stm32f4_gpio.h" +#include "stm32f4_pwm.h" #include "stm32f4_uart.h" #include "stm32_sys_tick.h" + // SYSTEM TICK static const enum stm32_sys_tick_time_base stm23_sys_tick_time_base = STM32_SYS_TICK_TIME_BASE_MS; @@ -36,6 +39,53 @@ static const struct loki_timer timer_1 = { &timer_fp }; +// PWM CHANNEL 4 +/* apb1 clock = 84MHz */ +/* period_reg = src_clk / presc / cnt_clk */ +/* 4199 = 84MHZ / (0 + 1) / 20kHz - 1 */ +static const TIM_TimeBaseInitTypeDef timer_4_cfg = { + .TIM_RepetitionCounter = 0x0000, + .TIM_Prescaler = 0, + .TIM_ClockDivision = TIM_CKD_DIV1, + .TIM_CounterMode = TIM_CounterMode_Up, + .TIM_Period = 4199 +}; + +static const TIM_OCInitTypeDef t4_output_compare_cfg = { + .TIM_OutputNState = TIM_OutputNState_Disable, + .TIM_OCNPolarity = TIM_OCPolarity_High, + .TIM_OCIdleState = TIM_OCIdleState_Reset, + .TIM_OCNIdleState = TIM_OCNIdleState_Set, + .TIM_OCMode = TIM_OCMode_PWM1, + .TIM_OCPolarity = TIM_OCPolarity_High, + .TIM_OutputState = TIM_OutputState_Enable, + .TIM_Pulse = 0 // Initiale Pulsweite in Millisekunden +}; + +static const GPIO_InitTypeDef port_cfg = { + .GPIO_Pin = GPIO_Pin_15, + .GPIO_Mode = GPIO_Mode_AF, + .GPIO_OType = GPIO_OType_PP, + .GPIO_PuPd = GPIO_PuPd_UP, + .GPIO_Speed = GPIO_Speed_100MHz, +}; + +static struct stm32f4_pwm str32f4_pwm = { + .timer = TIM4, + .timer_cfg = &timer_4_cfg, + .output_compare_cfg = &t4_output_compare_cfg, + .port = GPIOD, + .pin_src = GPIO_PinSource15, + .port_cfg = &port_cfg, + .channel = channel_4, +}; + +static const struct pwm pwm_ch4 = { + .arch_dep_device = &str32f4_pwm, + .fp = &stm32f4_pwm_fp, +}; + +// UART 1 static char console_linear_buffer[80]; static struct ringbuffer console_buffer = { console_linear_buffer, diff --git a/source/test/pwm/main.c b/source/test/pwm/main.c index b9150fa..f0aa726 100644 --- a/source/test/pwm/main.c +++ b/source/test/pwm/main.c @@ -16,55 +16,6 @@ #include "list.h" #include "shell.h" -#include "stm32f4xx.h" - -#include "pwm.h" -#include "stm32f4_pwm.h" - -/* apb1 clock = 84MHz */ -/* period_reg = src_clk / presc / cnt_clk */ -/* 4199 = 84MHZ / (0 + 1) / 20kHz - 1 */ -static const TIM_TimeBaseInitTypeDef timer_4_cfg = { - .TIM_RepetitionCounter = 0x0000, - .TIM_Prescaler = 0, - .TIM_ClockDivision = TIM_CKD_DIV1, - .TIM_CounterMode = TIM_CounterMode_Up, - .TIM_Period = 4199 -}; - -static const TIM_OCInitTypeDef t4_output_compare_cfg = { - .TIM_OutputNState = TIM_OutputNState_Disable, - .TIM_OCNPolarity = TIM_OCPolarity_High, - .TIM_OCIdleState = TIM_OCIdleState_Reset, - .TIM_OCNIdleState = TIM_OCNIdleState_Set, - .TIM_OCMode = TIM_OCMode_PWM1, - .TIM_OCPolarity = TIM_OCPolarity_High, - .TIM_OutputState = TIM_OutputState_Enable, - .TIM_Pulse = 0 // Initiale Pulsweite in Millisekunden -}; - -static const GPIO_InitTypeDef port_cfg = { - .GPIO_Pin = GPIO_Pin_15, - .GPIO_Mode = GPIO_Mode_AF, - .GPIO_OType = GPIO_OType_PP, - .GPIO_PuPd = GPIO_PuPd_UP, - .GPIO_Speed = GPIO_Speed_100MHz, -}; - -static struct stm32f4_pwm str32f4_pwm = { - .timer = TIM4, - .timer_cfg = &timer_4_cfg, - .output_compare_cfg = &t4_output_compare_cfg, - .port = GPIOD, - .pin_src = GPIO_PinSource15, - .port_cfg = &port_cfg, - .channel = channel_4, -}; - -static const struct pwm pwm_ch4 = { - .arch_dep_device = &str32f4_pwm, - .fp = &stm32f4_pwm_fp, -}; #define TH_STACK_SIZE 256 stack_t th_stack[TH_STACK_SIZE]; @@ -90,7 +41,6 @@ static void th_func(void *arg) int main(void) { thread_create(&th_ctx, th_stack, TH_STACK_SIZE, th_func, NULL, THREAD_PRIO_LOW); - schedule_start(); return 0; From 24770a1266411eba35a66dc16c87d24d050bee0c Mon Sep 17 00:00:00 2001 From: tkl Date: Tue, 9 Aug 2016 12:52:38 +0200 Subject: [PATCH 8/8] done --- .../include/stm32f4-discovery.h | 11 ++++- source/firmware/kernel/driver/driver.c | 41 +++++++++++++++++++ source/firmware/kernel/interface/driver.h | 4 ++ source/test/pwm/main.c | 5 ++- 4 files changed, 58 insertions(+), 3 deletions(-) diff --git a/source/firmware/arch/stm32f4xx/board/stm32f4-discovery/include/stm32f4-discovery.h b/source/firmware/arch/stm32f4xx/board/stm32f4-discovery/include/stm32f4-discovery.h index e6a7408..d70a788 100755 --- a/source/firmware/arch/stm32f4xx/board/stm32f4-discovery/include/stm32f4-discovery.h +++ b/source/firmware/arch/stm32f4xx/board/stm32f4-discovery/include/stm32f4-discovery.h @@ -59,7 +59,7 @@ static const TIM_OCInitTypeDef t4_output_compare_cfg = { .TIM_OCMode = TIM_OCMode_PWM1, .TIM_OCPolarity = TIM_OCPolarity_High, .TIM_OutputState = TIM_OutputState_Enable, - .TIM_Pulse = 0 // Initiale Pulsweite in Millisekunden + .TIM_Pulse = 0, }; static const GPIO_InitTypeDef port_cfg = { @@ -85,6 +85,15 @@ static const struct pwm pwm_ch4 = { .fp = &stm32f4_pwm_fp, }; +#ifdef TEST_APP +static const struct driver pwm_4 = { +#else +const struct driver pwm_4 = { +#endif + DRIVER_TYPE_PWM, + &pwm_ch4, +}; + // UART 1 static char console_linear_buffer[80]; static struct ringbuffer console_buffer = { diff --git a/source/firmware/kernel/driver/driver.c b/source/firmware/kernel/driver/driver.c index 06b4747..654c647 100644 --- a/source/firmware/kernel/driver/driver.c +++ b/source/firmware/kernel/driver/driver.c @@ -11,6 +11,7 @@ #include "adc.h" #include "gpio.h" #include "i2c.h" +#include "pwm.h" #include "rtc.h" #include "spi.h" #include "uart.h" @@ -30,6 +31,9 @@ int open(const struct driver *driver) case DRIVER_TYPE_I2C: ret = i2c_open((struct i2c *)(driver->device_driver)); break; + case DRIVER_TYPE_PWM: + ret = pwm_open((const struct pwm *)(driver->device_driver)); + break; case DRIVER_TYPE_RTC: ret = rtc_open((const struct rtc *)(driver->device_driver)); break; @@ -58,6 +62,9 @@ int close(const struct driver *driver) case DRIVER_TYPE_I2C: ret = i2c_close((struct i2c *)(driver->device_driver)); break; + case DRIVER_TYPE_PWM: + ret = pwm_close((const struct pwm *)(driver->device_driver)); + break; case DRIVER_TYPE_RTC: ret = rtc_close((const struct rtc *)(driver->device_driver)); break; @@ -88,6 +95,9 @@ int read(const struct driver *driver, char *buffer, int len) break; case DRIVER_TYPE_I2C: break; + case DRIVER_TYPE_PWM: + ret = -1; + break; case DRIVER_TYPE_RTC: break; case DRIVER_TYPE_SPI: @@ -118,6 +128,9 @@ int write(const struct driver *driver, const char *buffer, int len) break; case DRIVER_TYPE_I2C: break; + case DRIVER_TYPE_PWM: + ret = -1; + break; case DRIVER_TYPE_RTC: break; case DRIVER_TYPE_SPI: @@ -128,3 +141,31 @@ int write(const struct driver *driver, const char *buffer, int len) } return ret; } + +int ioctl(const struct driver *driver, unsigned int cmd, const void *data) +{ + int ret = -1; + if(NULL == driver) + return ret; + switch(driver->driver_type) { + case DRIVER_TYPE_ADC: + break; + case DRIVER_TYPE_GPIO: + break; + case DRIVER_TYPE_I2C: + break; + case DRIVER_TYPE_PWM: + if(cmd == IOCTL_PWM_SET_DUTY_CYCLE) { + unsigned int *duty = (unsigned int *)data; + pwm_set_duty_cycle((const struct pwm *)(driver->device_driver), *duty); + } + break; + case DRIVER_TYPE_RTC: + break; + case DRIVER_TYPE_SPI: + break; + case DRIVER_TYPE_UART: + break; + } + return ret; +} diff --git a/source/firmware/kernel/interface/driver.h b/source/firmware/kernel/interface/driver.h index ee82abf..14923d9 100644 --- a/source/firmware/kernel/interface/driver.h +++ b/source/firmware/kernel/interface/driver.h @@ -8,10 +8,13 @@ #ifndef SOURCE_FIRMWARE_KERNEL_DRIVER_INCLUDE_DRIVER_H_ #define SOURCE_FIRMWARE_KERNEL_DRIVER_INCLUDE_DRIVER_H_ +#define IOCTL_PWM_SET_DUTY_CYCLE 0 + enum driver_type { DRIVER_TYPE_ADC, DRIVER_TYPE_GPIO, DRIVER_TYPE_I2C, + DRIVER_TYPE_PWM, DRIVER_TYPE_RTC, DRIVER_TYPE_SPI, DRIVER_TYPE_UART @@ -26,5 +29,6 @@ int open(const struct driver *driver); int close(const struct driver *driver); int read(const struct driver *driver, char *buffer, int len); int write(const struct driver *driver, const char *buffer, int len); +int ioctl(const struct driver *driver, unsigned int cmd, const void *data); #endif /* SOURCE_FIRMWARE_KERNEL_DRIVER_INCLUDE_DRIVER_H_ */ diff --git a/source/test/pwm/main.c b/source/test/pwm/main.c index f0aa726..e8b0418 100644 --- a/source/test/pwm/main.c +++ b/source/test/pwm/main.c @@ -23,15 +23,16 @@ struct thread_context th_ctx; static void th_func(void *arg) { unsigned int duty = 0; - pwm_open(&pwm_ch4); + open(&pwm_4); while(1) { while(duty < 100) { + ioctl(&pwm_4, IOCTL_PWM_SET_DUTY_CYCLE, (const void *)&duty); pwm_set_duty_cycle(&pwm_ch4, duty); sleep_ms(10); duty++; } while(duty > 0) { - pwm_set_duty_cycle(&pwm_ch4, duty); + ioctl(&pwm_4, IOCTL_PWM_SET_DUTY_CYCLE, (const void *)&duty); sleep_ms(10); duty--; }