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source/firmware/arch/stm32f4xx/lib/stdperiph/src/misc.c Executable file
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/**
******************************************************************************
* @file misc.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides all the miscellaneous firmware functions (add-on
* to CMSIS functions).
*
* @verbatim
*
* ===================================================================
* How to configure Interrupts using driver
* ===================================================================
*
* This section provide functions allowing to configure the NVIC interrupts (IRQ).
* The Cortex-M4 exceptions are managed by CMSIS functions.
*
* 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
* function according to the following table.
* The table below gives the allowed values of the pre-emption priority and subpriority according
* to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
* ==========================================================================================================================
* NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
* ==========================================================================================================================
* NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
* | | | 4 bits for subpriority
* --------------------------------------------------------------------------------------------------------------------------
* NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
* | | | 3 bits for subpriority
* --------------------------------------------------------------------------------------------------------------------------
* NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
* | | | 2 bits for subpriority
* --------------------------------------------------------------------------------------------------------------------------
* NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
* | | | 1 bits for subpriority
* --------------------------------------------------------------------------------------------------------------------------
* NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
* | | | 0 bits for subpriority
* ==========================================================================================================================
*
* 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init()
*
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
*
* @note IRQ priority order (sorted by highest to lowest priority):
* - Lowest pre-emption priority
* - Lowest subpriority
* - Lowest hardware priority (IRQ number)
*
* @endverbatim
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "misc.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup MISC
* @brief MISC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup MISC_Private_Functions
* @{
*/
/**
* @brief Configures the priority grouping: pre-emption priority and subpriority.
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
* 4 bits for subpriority
* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
* 3 bits for subpriority
* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
* 2 bits for subpriority
* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
* 1 bits for subpriority
* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
* 0 bits for subpriority
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
}
/**
* @brief Initializes the NVIC peripheral according to the specified
* parameters in the NVIC_InitStruct.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before.
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
* the configuration information for the specified NVIC peripheral.
* @retval None
*/
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
{
uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
{
/* Compute the Corresponding IRQ Priority --------------------------------*/
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
tmppre = (0x4 - tmppriority);
tmpsub = tmpsub >> tmppriority;
tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
tmppriority = tmppriority << 0x04;
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
/* Enable the Selected IRQ Channels --------------------------------------*/
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
}
else
{
/* Disable the Selected IRQ Channels -------------------------------------*/
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
}
}
/**
* @brief Sets the vector table location and Offset.
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
* This parameter can be one of the following values:
* @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
* @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
* @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
* @retval None
*/
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
{
/* Check the parameters */
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
assert_param(IS_NVIC_OFFSET(Offset));
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
}
/**
* @brief Selects the condition for the system to enter low power mode.
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
* This parameter can be one of the following values:
* @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
* @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
* @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_NVIC_LP(LowPowerMode));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
SCB->SCR |= LowPowerMode;
}
else
{
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
}
}
/**
* @brief Configures the SysTick clock source.
* @param SysTick_CLKSource: specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
* @retval None
*/
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
{
/* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
{
SysTick->CTRL |= SysTick_CLKSource_HCLK;
}
else
{
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_adc.c Executable file
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source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_can.c Executable file
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source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_crc.c Executable file
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/**
******************************************************************************
* @file stm32f4xx_crc.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides all the CRC firmware functions.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_crc.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup CRC
* @brief CRC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CRC_Private_Functions
* @{
*/
/**
* @brief Resets the CRC Data register (DR).
* @param None
* @retval None
*/
void CRC_ResetDR(void)
{
/* Reset CRC generator */
CRC->CR = CRC_CR_RESET;
}
/**
* @brief Computes the 32-bit CRC of a given data word(32-bit).
* @param Data: data word(32-bit) to compute its CRC
* @retval 32-bit CRC
*/
uint32_t CRC_CalcCRC(uint32_t Data)
{
CRC->DR = Data;
return (CRC->DR);
}
/**
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
* @param pBuffer: pointer to the buffer containing the data to be computed
* @param BufferLength: length of the buffer to be computed
* @retval 32-bit CRC
*/
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index = 0;
for(index = 0; index < BufferLength; index++)
{
CRC->DR = pBuffer[index];
}
return (CRC->DR);
}
/**
* @brief Returns the current CRC value.
* @param None
* @retval 32-bit CRC
*/
uint32_t CRC_GetCRC(void)
{
return (CRC->DR);
}
/**
* @brief Stores a 8-bit data in the Independent Data(ID) register.
* @param IDValue: 8-bit value to be stored in the ID register
* @retval None
*/
void CRC_SetIDRegister(uint8_t IDValue)
{
CRC->IDR = IDValue;
}
/**
* @brief Returns the 8-bit data stored in the Independent Data(ID) register
* @param None
* @retval 8-bit value of the ID register
*/
uint8_t CRC_GetIDRegister(void)
{
return (CRC->IDR);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_cryp.c Executable file
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/**
******************************************************************************
* @file stm32f4xx_cryp.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Cryptographic processor (CRYP) peripheral:
* - Initialization and Configuration functions
* - Data treatment functions
* - Context swapping functions
* - DMA interface function
* - Interrupts and flags management
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Enable the CRYP controller clock using
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
*
* 2. Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if
* needed CRYP_IVInit().
*
* 3. Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function.
*
* 4. Enable the CRYP controller using the CRYP_Cmd() function.
*
* 5. If using DMA for Data input and output transfer,
* Activate the needed DMA Requests using CRYP_DMACmd() function
* 6. If DMA is not used for data transfer, use CRYP_DataIn() and
* CRYP_DataOut() functions to enter data to IN FIFO and get result
* from OUT FIFO.
*
* 7. To control CRYP events you can use one of the following
* two methods:
* - Check on CRYP flags using the CRYP_GetFlagStatus() function.
* - Use CRYP interrupts through the function CRYP_ITConfig() at
* initialization phase and CRYP_GetITStatus() function into
* interrupt routines in processing phase.
*
* 8. Save and restore Cryptographic processor context using
* CRYP_SaveContext() and CRYP_RestoreContext() functions.
*
*
* ===================================================================
* Procedure to perform an encryption or a decryption
* ===================================================================
*
* Initialization
* ===============
* 1. Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and
* CRYP_IVInit functions:
* - Configure the key size (128-, 192- or 256-bit, in the AES only)
* - Enter the symmetric key
* - Configure the data type
* - In case of decryption in AES-ECB or AES-CBC, you must prepare
* the key: configure the key preparation mode. Then Enable the CRYP
* peripheral using CRYP_Cmd() function: the BUSY flag is set.
* Wait until BUSY flag is reset : the key is prepared for decryption
* - Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the
* AES in ECB/CBC/CTR)
* - Configure the direction (encryption/decryption).
* - Write the initialization vectors (in CBC or CTR modes only)
*
* 2. Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function
*
*
* Basic Processing mode (polling mode)
* ====================================
* 1. Enable the cryptographic processor using CRYP_Cmd() function.
*
* 2. Write the first blocks in the input FIFO (2 to 8 words) using
* CRYP_DataIn() function.
*
* 3. Repeat the following sequence until the complete message has been
* processed:
*
* a) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus()
* function), then read the OUT-FIFO using CRYP_DataOut() function
* (1 block or until the FIFO is empty)
*
* b) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus()
* function then write the IN FIFO using CRYP_DataIn() function
* (1 block or until the FIFO is full)
*
* 4. At the end of the processing, CRYP_FLAG_BUSY flag will be reset and
* both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is
* reset). You can disable the peripheral using CRYP_Cmd() function.
*
* Interrupts Processing mode
* ===========================
* In this mode, Processing is done when the data are transferred by the
* CPU during interrupts.
*
* 1. Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using
* CRYP_ITConfig() function.
*
* 2. Enable the cryptographic processor using CRYP_Cmd() function.
*
* 3. In the CRYP_IT_INI interrupt handler : load the input message into the
* IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a
* time, or load data until the IN FIFO is full. When the last word of
* the message has been entered into the IN FIFO, disable the CRYP_IT_INI
* interrupt (using CRYP_ITConfig() function).
*
* 4. In the CRYP_IT_OUTI interrupt handler : read the output message from
* the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or
* 4 words) at a time or read data until the FIFO is empty.
* When the last word has been read, INIM=0, BUSY=0 and both FIFOs are
* empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset).
* You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig()
* function) and you can disable the peripheral using CRYP_Cmd() function.
*
* DMA Processing mode
* ====================
* In this mode, Processing is done when the DMA is used to transfer the
* data from/to the memory.
*
* 1. Configure the DMA controller to transfer the input data from the
* memory using DMA_Init() function.
* The transfer length is the length of the message.
* As message padding is not managed by the peripheral, the message
* length must be an entire number of blocks. The data are transferred
* in burst mode. The burst length is 4 words in the AES and 2 or 4
* words in the DES/TDES. The DMA should be configured to set an
* interrupt on transfer completion of the output data to indicate that
* the processing is finished.
* Refer to DMA peripheral driver for more details.
*
* 2. Enable the cryptographic processor using CRYP_Cmd() function.
* Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT
* using CRYP_DMACmd() function.
*
* 3. All the transfers and processing are managed by the DMA and the
* cryptographic processor. The DMA transfer complete interrupt indicates
* that the processing is complete. Both FIFOs are normally empty and
* CRYP_FLAG_BUSY flag is reset.
*
* @endverbatim
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_cryp.h"
#include "stm32f4xx_rcc.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup CRYP
* @brief CRYP driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define FLAG_MASK ((uint8_t)0x20)
#define MAX_TIMEOUT ((uint16_t)0xFFFF)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CRYP_Private_Functions
* @{
*/
/** @defgroup CRYP_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
Initialization and Configuration functions
===============================================================================
This section provides functions allowing to
- Initialize the cryptographic Processor using CRYP_Init() function
- Encrypt or Decrypt
- mode : TDES-ECB, TDES-CBC,
DES-ECB, DES-CBC,
AES-ECB, AES-CBC, AES-CTR, AES-Key
- DataType : 32-bit data, 16-bit data, bit data or bit-string
- Key Size (only in AES modes)
- Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function
- Configure the Initialization Vectors(IV) for CBC and CTR modes using
CRYP_IVInit() function.
- Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function.
- Enable or disable the CRYP Processor using CRYP_Cmd() function
@endverbatim
* @{
*/
/**
* @brief Deinitializes the CRYP peripheral registers to their default reset values
* @param None
* @retval None
*/
void CRYP_DeInit(void)
{
/* Enable CRYP reset state */
RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, ENABLE);
/* Release CRYP from reset state */
RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, DISABLE);
}
/**
* @brief Initializes the CRYP peripheral according to the specified parameters
* in the CRYP_InitStruct.
* @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure that contains
* the configuration information for the CRYP peripheral.
* @retval None
*/
void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct)
{
/* Check the parameters */
assert_param(IS_CRYP_ALGOMODE(CRYP_InitStruct->CRYP_AlgoMode));
assert_param(IS_CRYP_DATATYPE(CRYP_InitStruct->CRYP_DataType));
assert_param(IS_CRYP_ALGODIR(CRYP_InitStruct->CRYP_AlgoDir));
/* Select Algorithm mode*/
CRYP->CR &= ~CRYP_CR_ALGOMODE;
CRYP->CR |= CRYP_InitStruct->CRYP_AlgoMode;
/* Select dataType */
CRYP->CR &= ~CRYP_CR_DATATYPE;
CRYP->CR |= CRYP_InitStruct->CRYP_DataType;
/* select Key size (used only with AES algorithm) */
if ((CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_ECB) ||
(CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CBC) ||
(CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CTR) ||
(CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_Key))
{
assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize));
CRYP->CR &= ~CRYP_CR_KEYSIZE;
CRYP->CR |= CRYP_InitStruct->CRYP_KeySize; /* Key size and value must be
configured once the key has
been prepared */
}
/* Select data Direction */
CRYP->CR &= ~CRYP_CR_ALGODIR;
CRYP->CR |= CRYP_InitStruct->CRYP_AlgoDir;
}
/**
* @brief Fills each CRYP_InitStruct member with its default value.
* @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct)
{
/* Initialize the CRYP_AlgoDir member */
CRYP_InitStruct->CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
/* initialize the CRYP_AlgoMode member */
CRYP_InitStruct->CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB;
/* initialize the CRYP_DataType member */
CRYP_InitStruct->CRYP_DataType = CRYP_DataType_32b;
/* Initialize the CRYP_KeySize member */
CRYP_InitStruct->CRYP_KeySize = CRYP_KeySize_128b;
}
/**
* @brief Initializes the CRYP Keys according to the specified parameters in
* the CRYP_KeyInitStruct.
* @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that
* contains the configuration information for the CRYP Keys.
* @retval None
*/
void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
{
/* Key Initialisation */
CRYP->K0LR = CRYP_KeyInitStruct->CRYP_Key0Left;
CRYP->K0RR = CRYP_KeyInitStruct->CRYP_Key0Right;
CRYP->K1LR = CRYP_KeyInitStruct->CRYP_Key1Left;
CRYP->K1RR = CRYP_KeyInitStruct->CRYP_Key1Right;
CRYP->K2LR = CRYP_KeyInitStruct->CRYP_Key2Left;
CRYP->K2RR = CRYP_KeyInitStruct->CRYP_Key2Right;
CRYP->K3LR = CRYP_KeyInitStruct->CRYP_Key3Left;
CRYP->K3RR = CRYP_KeyInitStruct->CRYP_Key3Right;
}
/**
* @brief Fills each CRYP_KeyInitStruct member with its default value.
* @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure
* which will be initialized.
* @retval None
*/
void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
{
CRYP_KeyInitStruct->CRYP_Key0Left = 0;
CRYP_KeyInitStruct->CRYP_Key0Right = 0;
CRYP_KeyInitStruct->CRYP_Key1Left = 0;
CRYP_KeyInitStruct->CRYP_Key1Right = 0;
CRYP_KeyInitStruct->CRYP_Key2Left = 0;
CRYP_KeyInitStruct->CRYP_Key2Right = 0;
CRYP_KeyInitStruct->CRYP_Key3Left = 0;
CRYP_KeyInitStruct->CRYP_Key3Right = 0;
}
/**
* @brief Initializes the CRYP Initialization Vectors(IV) according to the
* specified parameters in the CRYP_IVInitStruct.
* @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef structure that contains
* the configuration information for the CRYP Initialization Vectors(IV).
* @retval None
*/
void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct)
{
CRYP->IV0LR = CRYP_IVInitStruct->CRYP_IV0Left;
CRYP->IV0RR = CRYP_IVInitStruct->CRYP_IV0Right;
CRYP->IV1LR = CRYP_IVInitStruct->CRYP_IV1Left;
CRYP->IV1RR = CRYP_IVInitStruct->CRYP_IV1Right;
}
/**
* @brief Fills each CRYP_IVInitStruct member with its default value.
* @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef Initialization
* Vectors(IV) structure which will be initialized.
* @retval None
*/
void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct)
{
CRYP_IVInitStruct->CRYP_IV0Left = 0;
CRYP_IVInitStruct->CRYP_IV0Right = 0;
CRYP_IVInitStruct->CRYP_IV1Left = 0;
CRYP_IVInitStruct->CRYP_IV1Right = 0;
}
/**
* @brief Flushes the IN and OUT FIFOs (that is read and write pointers of the
* FIFOs are reset)
* @note The FIFOs must be flushed only when BUSY flag is reset.
* @param None
* @retval None
*/
void CRYP_FIFOFlush(void)
{
/* Reset the read and write pointers of the FIFOs */
CRYP->CR |= CRYP_CR_FFLUSH;
}
/**
* @brief Enables or disables the CRYP peripheral.
* @param NewState: new state of the CRYP peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void CRYP_Cmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the Cryptographic processor */
CRYP->CR |= CRYP_CR_CRYPEN;
}
else
{
/* Disable the Cryptographic processor */
CRYP->CR &= ~CRYP_CR_CRYPEN;
}
}
/**
* @}
*/
/** @defgroup CRYP_Group2 CRYP Data processing functions
* @brief CRYP Data processing functions
*
@verbatim
===============================================================================
CRYP Data processing functions
===============================================================================
This section provides functions allowing the encryption and decryption
operations:
- Enter data to be treated in the IN FIFO : using CRYP_DataIn() function.
- Get the data result from the OUT FIFO : using CRYP_DataOut() function.
@endverbatim
* @{
*/
/**
* @brief Writes data in the Data Input register (DIN).
* @note After the DIN register has been read once or several times,
* the FIFO must be flushed (using CRYP_FIFOFlush() function).
* @param Data: data to write in Data Input register
* @retval None
*/
void CRYP_DataIn(uint32_t Data)
{
CRYP->DR = Data;
}
/**
* @brief Returns the last data entered into the output FIFO.
* @param None
* @retval Last data entered into the output FIFO.
*/
uint32_t CRYP_DataOut(void)
{
return CRYP->DOUT;
}
/**
* @}
*/
/** @defgroup CRYP_Group3 Context swapping functions
* @brief Context swapping functions
*
@verbatim
===============================================================================
Context swapping functions
===============================================================================
This section provides functions allowing to save and store CRYP Context
It is possible to interrupt an encryption/ decryption/ key generation process
to perform another processing with a higher priority, and to complete the
interrupted process later on, when the higher-priority task is complete. To do
so, the context of the interrupted task must be saved from the CRYP registers
to memory, and then be restored from memory to the CRYP registers.
1. To save the current context, use CRYP_SaveContext() function
2. To restore the saved context, use CRYP_RestoreContext() function
@endverbatim
* @{
*/
/**
* @brief Saves the CRYP peripheral Context.
* @note This function stops DMA transfer before to save the context. After
* restoring the context, you have to enable the DMA again (if the DMA
* was previously used).
* @param CRYP_ContextSave: pointer to a CRYP_Context structure that contains
* the repository for current context.
* @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that
* contains the configuration information for the CRYP Keys.
* @retval None
*/
ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
{
__IO uint32_t timeout = 0;
uint32_t ckeckmask = 0, bitstatus;
ErrorStatus status = ERROR;
/* Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR */
CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DIEN;
/* Wait until both the IN and OUT FIFOs are empty
(IFEM=1 and OFNE=0 in the CRYP_SR register) and the
BUSY bit is cleared. */
if ((CRYP->CR & (uint32_t)(CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE_TDES_CBC)) != (uint32_t)0 )/* TDES */
{
ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY ;
}
else /* AES or DES */
{
ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY | CRYP_SR_OFNE;
}
do
{
bitstatus = CRYP->SR & ckeckmask;
timeout++;
}
while ((timeout != MAX_TIMEOUT) && (bitstatus != CRYP_SR_IFEM));
if ((CRYP->SR & ckeckmask) != CRYP_SR_IFEM)
{
status = ERROR;
}
else
{
/* Stop DMA transfers on the OUT FIFO by
- writing the DOEN bit to 0 in the CRYP_DMACR register
- and clear the CRYPEN bit. */
CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN;
CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN;
/* Save the current configuration (bits [9:2] in the CRYP_CR register) */
CRYP_ContextSave->CR_bits9to2 = CRYP->CR & (CRYP_CR_KEYSIZE |
CRYP_CR_DATATYPE |
CRYP_CR_ALGOMODE |
CRYP_CR_ALGODIR);
/* and, if not in ECB mode, the initialization vectors. */
CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR;
CRYP_ContextSave->CRYP_IV0RR = CRYP->IV0RR;
CRYP_ContextSave->CRYP_IV1LR = CRYP->IV1LR;
CRYP_ContextSave->CRYP_IV1RR = CRYP->IV1RR;
/* save The key value */
CRYP_ContextSave->CRYP_K0LR = CRYP_KeyInitStruct->CRYP_Key0Left;
CRYP_ContextSave->CRYP_K0RR = CRYP_KeyInitStruct->CRYP_Key0Right;
CRYP_ContextSave->CRYP_K1LR = CRYP_KeyInitStruct->CRYP_Key1Left;
CRYP_ContextSave->CRYP_K1RR = CRYP_KeyInitStruct->CRYP_Key1Right;
CRYP_ContextSave->CRYP_K2LR = CRYP_KeyInitStruct->CRYP_Key2Left;
CRYP_ContextSave->CRYP_K2RR = CRYP_KeyInitStruct->CRYP_Key2Right;
CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left;
CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right;
/* When needed, save the DMA status (pointers for IN and OUT messages,
number of remaining bytes, etc.) */
status = SUCCESS;
}
return status;
}
/**
* @brief Restores the CRYP peripheral Context.
* @note Since teh DMA transfer is stopped in CRYP_SaveContext() function,
* after restoring the context, you have to enable the DMA again (if the
* DMA was previously used).
* @param CRYP_ContextRestore: pointer to a CRYP_Context structure that contains
* the repository for saved context.
* @note The data that were saved during context saving must be rewrited into
* the IN FIFO.
* @retval None
*/
void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore)
{
/* Configure the processor with the saved configuration */
CRYP->CR = CRYP_ContextRestore->CR_bits9to2;
/* restore The key value */
CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR;
CRYP->K0RR = CRYP_ContextRestore->CRYP_K0RR;
CRYP->K1LR = CRYP_ContextRestore->CRYP_K1LR;
CRYP->K1RR = CRYP_ContextRestore->CRYP_K1RR;
CRYP->K2LR = CRYP_ContextRestore->CRYP_K2LR;
CRYP->K2RR = CRYP_ContextRestore->CRYP_K2RR;
CRYP->K3LR = CRYP_ContextRestore->CRYP_K3LR;
CRYP->K3RR = CRYP_ContextRestore->CRYP_K3RR;
/* and the initialization vectors. */
CRYP->IV0LR = CRYP_ContextRestore->CRYP_IV0LR;
CRYP->IV0RR = CRYP_ContextRestore->CRYP_IV0RR;
CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR;
CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR;
/* Enable the cryptographic processor */
CRYP->CR |= CRYP_CR_CRYPEN;
}
/**
* @}
*/
/** @defgroup CRYP_Group4 CRYP's DMA interface Configuration function
* @brief CRYP's DMA interface Configuration function
*
@verbatim
===============================================================================
CRYP's DMA interface Configuration function
===============================================================================
This section provides functions allowing to configure the DMA interface for
CRYP data input and output transfer.
When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be
transferred:
- From memory to the CRYP IN FIFO using the DMA peripheral by enabling
the CRYP_DMAReq_DataIN request.
- From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling
the CRYP_DMAReq_DataOUT request.
@endverbatim
* @{
*/
/**
* @brief Enables or disables the CRYP DMA interface.
* @param CRYP_DMAReq: specifies the CRYP DMA transfer request to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer
* @arg CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer
* @param NewState: new state of the selected CRYP DMA transfer request.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_CRYP_DMAREQ(CRYP_DMAReq));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected CRYP DMA request */
CRYP->DMACR |= CRYP_DMAReq;
}
else
{
/* Disable the selected CRYP DMA request */
CRYP->DMACR &= (uint8_t)~CRYP_DMAReq;
}
}
/**
* @}
*/
/** @defgroup CRYP_Group5 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
Interrupts and flags management functions
===============================================================================
This section provides functions allowing to configure the CRYP Interrupts and
to get the status and Interrupts pending bits.
The CRYP provides 2 Interrupts sources and 7 Flags:
Flags :
-------
1. CRYP_FLAG_IFEM : Set when Input FIFO is empty.
This Flag is cleared only by hardware.
2. CRYP_FLAG_IFNF : Set when Input FIFO is not full.
This Flag is cleared only by hardware.
3. CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending
it gives the raw interrupt state prior to masking
of the input FIFO service interrupt.
This Flag is cleared only by hardware.
4. CRYP_FLAG_OFNE : Set when Output FIFO not empty.
This Flag is cleared only by hardware.
5. CRYP_FLAG_OFFU : Set when Output FIFO is full.
This Flag is cleared only by hardware.
6. CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending
it gives the raw interrupt state prior to masking
of the output FIFO service interrupt.
This Flag is cleared only by hardware.
7. CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a
block of data or a key preparation (for AES
decryption).
This Flag is cleared only by hardware.
To clear it, the CRYP core must be disabled and the
last processing has completed.
Interrupts :
------------
1. CRYP_IT_INI : The input FIFO service interrupt is asserted when there
are less than 4 words in the input FIFO.
This interrupt is associated to CRYP_FLAG_INRIS flag.
@note This interrupt is cleared by performing write operations
to the input FIFO until it holds 4 or more words. The
input FIFO service interrupt INMIS is enabled with the
CRYP enable bit. Consequently, when CRYP is disabled, the
INMIS signal is low even if the input FIFO is empty.
2. CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there
is one or more (32-bit word) data items in the output FIFO.
This interrupt is associated to CRYP_FLAG_OUTRIS flag.
@note This interrupt is cleared by reading data from the output
FIFO until there is no valid (32-bit) word left (that is,
the interrupt follows the state of the OFNE (output FIFO
not empty) flag).
Managing the CRYP controller events :
------------------------------------
The user should identify which mode will be used in his application to manage
the CRYP controller events: Polling mode or Interrupt mode.
1. In the Polling Mode it is advised to use the following functions:
- CRYP_GetFlagStatus() : to check if flags events occur.
@note The CRYPT flags do not need to be cleared since they are cleared as
soon as the associated event are reset.
2. In the Interrupt Mode it is advised to use the following functions:
- CRYP_ITConfig() : to enable or disable the interrupt source.
- CRYP_GetITStatus() : to check if Interrupt occurs.
@note The CRYPT interrupts have no pending bits, the interrupt is cleared as
soon as the associated event is reset.
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified CRYP interrupts.
* @param CRYP_IT: specifies the CRYP interrupt source to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg CRYP_IT_INI: Input FIFO interrupt
* @arg CRYP_IT_OUTI: Output FIFO interrupt
* @param NewState: new state of the specified CRYP interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_CRYP_CONFIG_IT(CRYP_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected CRYP interrupt */
CRYP->IMSCR |= CRYP_IT;
}
else
{
/* Disable the selected CRYP interrupt */
CRYP->IMSCR &= (uint8_t)~CRYP_IT;
}
}
/**
* @brief Checks whether the specified CRYP interrupt has occurred or not.
* @note This function checks the status of the masked interrupt (i.e the
* interrupt should be previously enabled).
* @param CRYP_IT: specifies the CRYP (masked) interrupt source to check.
* This parameter can be one of the following values:
* @arg CRYP_IT_INI: Input FIFO interrupt
* @arg CRYP_IT_OUTI: Output FIFO interrupt
* @retval The new state of CRYP_IT (SET or RESET).
*/
ITStatus CRYP_GetITStatus(uint8_t CRYP_IT)
{
ITStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_CRYP_GET_IT(CRYP_IT));
/* Check the status of the specified CRYP interrupt */
if ((CRYP->MISR & CRYP_IT) != (uint8_t)RESET)
{
/* CRYP_IT is set */
bitstatus = SET;
}
else
{
/* CRYP_IT is reset */
bitstatus = RESET;
}
/* Return the CRYP_IT status */
return bitstatus;
}
/**
* @brief Checks whether the specified CRYP flag is set or not.
* @param CRYP_FLAG: specifies the CRYP flag to check.
* This parameter can be one of the following values:
* @arg CRYP_FLAG_IFEM: Input FIFO Empty flag.
* @arg CRYP_FLAG_IFNF: Input FIFO Not Full flag.
* @arg CRYP_FLAG_OFNE: Output FIFO Not Empty flag.
* @arg CRYP_FLAG_OFFU: Output FIFO Full flag.
* @arg CRYP_FLAG_BUSY: Busy flag.
* @arg CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag.
* @arg CRYP_FLAG_INRIS: Input FIFO raw interrupt flag.
* @retval The new state of CRYP_FLAG (SET or RESET).
*/
FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t tempreg = 0;
/* Check the parameters */
assert_param(IS_CRYP_GET_FLAG(CRYP_FLAG));
/* check if the FLAG is in RISR register */
if ((CRYP_FLAG & FLAG_MASK) != 0x00)
{
tempreg = CRYP->RISR;
}
else /* The FLAG is in SR register */
{
tempreg = CRYP->SR;
}
/* Check the status of the specified CRYP flag */
if ((tempreg & CRYP_FLAG ) != (uint8_t)RESET)
{
/* CRYP_FLAG is set */
bitstatus = SET;
}
else
{
/* CRYP_FLAG is reset */
bitstatus = RESET;
}
/* Return the CRYP_FLAG status */
return bitstatus;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_cryp_aes.c Executable file
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@@ -0,0 +1,638 @@
/**
******************************************************************************
* @file stm32f4xx_cryp_aes.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides high level functions to encrypt and decrypt an
* input message using AES in ECB/CBC/CTR modes.
* It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
* peripheral.
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Enable The CRYP controller clock using
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
*
* 2. Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB()
* function.
*
* 3. Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC()
* function.
*
* 4. Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR()
* function.
*
* @endverbatim
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_cryp.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup CRYP
* @brief CRYP driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define AESBUSY_TIMEOUT ((uint32_t) 0x00010000)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CRYP_Private_Functions
* @{
*/
/** @defgroup CRYP_Group6 High Level AES functions
* @brief High Level AES functions
*
@verbatim
===============================================================================
High Level AES functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Encrypt and decrypt using AES in ECB Mode
* @param Mode: encryption or decryption Mode.
* This parameter can be one of the following values:
* @arg MODE_ENCRYPT: Encryption
* @arg MODE_DECRYPT: Decryption
* @param Key: Key used for AES algorithm.
* @param Keysize: length of the Key, must be a 128, 192 or 256.
* @param Input: pointer to the Input buffer.
* @param Ilength: length of the Input buffer, must be a multiple of 16.
* @param Output: pointer to the returned buffer.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Operation done
* - ERROR: Operation failed
*/
ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t* Key, uint16_t Keysize,
uint8_t* Input, uint32_t Ilength, uint8_t* Output)
{
CRYP_InitTypeDef AES_CRYP_InitStructure;
CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
__IO uint32_t counter = 0;
uint32_t busystatus = 0;
ErrorStatus status = SUCCESS;
uint32_t keyaddr = (uint32_t)Key;
uint32_t inputaddr = (uint32_t)Input;
uint32_t outputaddr = (uint32_t)Output;
uint32_t i = 0;
/* Crypto structures initialisation*/
CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
switch(Keysize)
{
case 128:
AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
break;
case 192:
AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b;
AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
break;
case 256:
AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b;
AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
break;
default:
break;
}
/*------------------ AES Decryption ------------------*/
if(Mode == MODE_DECRYPT) /* AES decryption */
{
/* Flush IN/OUT FIFOs */
CRYP_FIFOFlush();
/* Crypto Init for Key preparation for decryption process */
AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key;
AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b;
CRYP_Init(&AES_CRYP_InitStructure);
/* Key Initialisation */
CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
/* Enable Crypto processor */
CRYP_Cmd(ENABLE);
/* wait until the Busy flag is RESET */
do
{
busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
counter++;
}while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
if (busystatus != RESET)
{
status = ERROR;
}
else
{
/* Crypto Init for decryption process */
AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
}
}
/*------------------ AES Encryption ------------------*/
else /* AES encryption */
{
CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
/* Crypto Init for Encryption process */
AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
}
AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB;
AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
CRYP_Init(&AES_CRYP_InitStructure);
/* Flush IN/OUT FIFOs */
CRYP_FIFOFlush();
/* Enable Crypto processor */
CRYP_Cmd(ENABLE);
for(i=0; ((i<Ilength) && (status != ERROR)); i+=16)
{
/* Write the Input block in the IN FIFO */
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
/* Wait until the complete message has been processed */
counter = 0;
do
{
busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
counter++;
}while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
if (busystatus != RESET)
{
status = ERROR;
}
else
{
/* Read the Output block from the Output FIFO */
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
}
}
/* Disable Crypto */
CRYP_Cmd(DISABLE);
return status;
}
/**
* @brief Encrypt and decrypt using AES in CBC Mode
* @param Mode: encryption or decryption Mode.
* This parameter can be one of the following values:
* @arg MODE_ENCRYPT: Encryption
* @arg MODE_DECRYPT: Decryption
* @param InitVectors: Initialisation Vectors used for AES algorithm.
* @param Key: Key used for AES algorithm.
* @param Keysize: length of the Key, must be a 128, 192 or 256.
* @param Input: pointer to the Input buffer.
* @param Ilength: length of the Input buffer, must be a multiple of 16.
* @param Output: pointer to the returned buffer.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Operation done
* - ERROR: Operation failed
*/
ErrorStatus CRYP_AES_CBC(uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key,
uint16_t Keysize, uint8_t *Input, uint32_t Ilength,
uint8_t *Output)
{
CRYP_InitTypeDef AES_CRYP_InitStructure;
CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
CRYP_IVInitTypeDef AES_CRYP_IVInitStructure;
__IO uint32_t counter = 0;
uint32_t busystatus = 0;
ErrorStatus status = SUCCESS;
uint32_t keyaddr = (uint32_t)Key;
uint32_t inputaddr = (uint32_t)Input;
uint32_t outputaddr = (uint32_t)Output;
uint32_t ivaddr = (uint32_t)InitVectors;
uint32_t i = 0;
/* Crypto structures initialisation*/
CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
switch(Keysize)
{
case 128:
AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
break;
case 192:
AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b;
AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
break;
case 256:
AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b;
AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
break;
default:
break;
}
/* CRYP Initialization Vectors */
AES_CRYP_IVInitStructure.CRYP_IV0Left = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
AES_CRYP_IVInitStructure.CRYP_IV0Right= __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
AES_CRYP_IVInitStructure.CRYP_IV1Left = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
AES_CRYP_IVInitStructure.CRYP_IV1Right= __REV(*(uint32_t*)(ivaddr));
/*------------------ AES Decryption ------------------*/
if(Mode == MODE_DECRYPT) /* AES decryption */
{
/* Flush IN/OUT FIFOs */
CRYP_FIFOFlush();
/* Crypto Init for Key preparation for decryption process */
AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key;
AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b;
CRYP_Init(&AES_CRYP_InitStructure);
/* Key Initialisation */
CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
/* Enable Crypto processor */
CRYP_Cmd(ENABLE);
/* wait until the Busy flag is RESET */
do
{
busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
counter++;
}while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
if (busystatus != RESET)
{
status = ERROR;
}
else
{
/* Crypto Init for decryption process */
AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
}
}
/*------------------ AES Encryption ------------------*/
else /* AES encryption */
{
CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
/* Crypto Init for Encryption process */
AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
}
AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CBC;
AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
CRYP_Init(&AES_CRYP_InitStructure);
/* CRYP Initialization Vectors */
CRYP_IVInit(&AES_CRYP_IVInitStructure);
/* Flush IN/OUT FIFOs */
CRYP_FIFOFlush();
/* Enable Crypto processor */
CRYP_Cmd(ENABLE);
for(i=0; ((i<Ilength) && (status != ERROR)); i+=16)
{
/* Write the Input block in the IN FIFO */
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
/* Wait until the complete message has been processed */
counter = 0;
do
{
busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
counter++;
}while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
if (busystatus != RESET)
{
status = ERROR;
}
else
{
/* Read the Output block from the Output FIFO */
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
}
}
/* Disable Crypto */
CRYP_Cmd(DISABLE);
return status;
}
/**
* @brief Encrypt and decrypt using AES in CTR Mode
* @param Mode: encryption or decryption Mode.
* This parameter can be one of the following values:
* @arg MODE_ENCRYPT: Encryption
* @arg MODE_DECRYPT: Decryption
* @param InitVectors: Initialisation Vectors used for AES algorithm.
* @param Key: Key used for AES algorithm.
* @param Keysize: length of the Key, must be a 128, 192 or 256.
* @param Input: pointer to the Input buffer.
* @param Ilength: length of the Input buffer, must be a multiple of 16.
* @param Output: pointer to the returned buffer.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Operation done
* - ERROR: Operation failed
*/
ErrorStatus CRYP_AES_CTR(uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key,
uint16_t Keysize, uint8_t *Input, uint32_t Ilength,
uint8_t *Output)
{
CRYP_InitTypeDef AES_CRYP_InitStructure;
CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
CRYP_IVInitTypeDef AES_CRYP_IVInitStructure;
__IO uint32_t counter = 0;
uint32_t busystatus = 0;
ErrorStatus status = SUCCESS;
uint32_t keyaddr = (uint32_t)Key;
uint32_t inputaddr = (uint32_t)Input;
uint32_t outputaddr = (uint32_t)Output;
uint32_t ivaddr = (uint32_t)InitVectors;
uint32_t i = 0;
/* Crypto structures initialisation*/
CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
switch(Keysize)
{
case 128:
AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
break;
case 192:
AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b;
AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
break;
case 256:
AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b;
AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
break;
default:
break;
}
/* CRYP Initialization Vectors */
AES_CRYP_IVInitStructure.CRYP_IV0Left = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
AES_CRYP_IVInitStructure.CRYP_IV0Right= __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
AES_CRYP_IVInitStructure.CRYP_IV1Left = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
AES_CRYP_IVInitStructure.CRYP_IV1Right= __REV(*(uint32_t*)(ivaddr));
/* Key Initialisation */
CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
/*------------------ AES Decryption ------------------*/
if(Mode == MODE_DECRYPT) /* AES decryption */
{
/* Crypto Init for decryption process */
AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
}
/*------------------ AES Encryption ------------------*/
else /* AES encryption */
{
/* Crypto Init for Encryption process */
AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
}
AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CTR;
AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
CRYP_Init(&AES_CRYP_InitStructure);
/* CRYP Initialization Vectors */
CRYP_IVInit(&AES_CRYP_IVInitStructure);
/* Flush IN/OUT FIFOs */
CRYP_FIFOFlush();
/* Enable Crypto processor */
CRYP_Cmd(ENABLE);
for(i=0; ((i<Ilength) && (status != ERROR)); i+=16)
{
/* Write the Input block in the IN FIFO */
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
/* Wait until the complete message has been processed */
counter = 0;
do
{
busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
counter++;
}while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
if (busystatus != RESET)
{
status = ERROR;
}
else
{
/* Read the Output block from the Output FIFO */
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
}
}
/* Disable Crypto */
CRYP_Cmd(DISABLE);
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

291
source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_cryp_des.c Executable file
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@@ -0,0 +1,291 @@
/**
******************************************************************************
* @file stm32f4xx_cryp_des.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides high level functions to encrypt and decrypt an
* input message using DES in ECB/CBC modes.
* It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
* peripheral.
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Enable The CRYP controller clock using
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
*
* 2. Encrypt and decrypt using DES in ECB Mode using CRYP_DES_ECB()
* function.
*
* 3. Encrypt and decrypt using DES in CBC Mode using CRYP_DES_CBC()
* function.
*
* @endverbatim
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_cryp.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup CRYP
* @brief CRYP driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define DESBUSY_TIMEOUT ((uint32_t) 0x00010000)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CRYP_Private_Functions
* @{
*/
/** @defgroup CRYP_Group8 High Level DES functions
* @brief High Level DES functions
*
@verbatim
===============================================================================
High Level DES functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Encrypt and decrypt using DES in ECB Mode
* @param Mode: encryption or decryption Mode.
* This parameter can be one of the following values:
* @arg MODE_ENCRYPT: Encryption
* @arg MODE_DECRYPT: Decryption
* @param Key: Key used for DES algorithm.
* @param Ilength: length of the Input buffer, must be a multiple of 8.
* @param Input: pointer to the Input buffer.
* @param Output: pointer to the returned buffer.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Operation done
* - ERROR: Operation failed
*/
ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input,
uint32_t Ilength, uint8_t *Output)
{
CRYP_InitTypeDef DES_CRYP_InitStructure;
CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure;
__IO uint32_t counter = 0;
uint32_t busystatus = 0;
ErrorStatus status = SUCCESS;
uint32_t keyaddr = (uint32_t)Key;
uint32_t inputaddr = (uint32_t)Input;
uint32_t outputaddr = (uint32_t)Output;
uint32_t i = 0;
/* Crypto structures initialisation*/
CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure);
/* Crypto Init for Encryption process */
if( Mode == MODE_ENCRYPT ) /* DES encryption */
{
DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
}
else/* if( Mode == MODE_DECRYPT )*/ /* DES decryption */
{
DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
}
DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB;
DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
CRYP_Init(&DES_CRYP_InitStructure);
/* Key Initialisation */
DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
CRYP_KeyInit(& DES_CRYP_KeyInitStructure);
/* Flush IN/OUT FIFO */
CRYP_FIFOFlush();
/* Enable Crypto processor */
CRYP_Cmd(ENABLE);
for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
{
/* Write the Input block in the Input FIFO */
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
/* Wait until the complete message has been processed */
counter = 0;
do
{
busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
counter++;
}while ((counter != DESBUSY_TIMEOUT) && (busystatus != RESET));
if (busystatus != RESET)
{
status = ERROR;
}
else
{
/* Read the Output block from the Output FIFO */
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
}
}
/* Disable Crypto */
CRYP_Cmd(DISABLE);
return status;
}
/**
* @brief Encrypt and decrypt using DES in CBC Mode
* @param Mode: encryption or decryption Mode.
* This parameter can be one of the following values:
* @arg MODE_ENCRYPT: Encryption
* @arg MODE_DECRYPT: Decryption
* @param Key: Key used for DES algorithm.
* @param InitVectors: Initialisation Vectors used for DES algorithm.
* @param Ilength: length of the Input buffer, must be a multiple of 8.
* @param Input: pointer to the Input buffer.
* @param Output: pointer to the returned buffer.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Operation done
* - ERROR: Operation failed
*/
ErrorStatus CRYP_DES_CBC(uint8_t Mode, uint8_t Key[8], uint8_t InitVectors[8],
uint8_t *Input, uint32_t Ilength, uint8_t *Output)
{
CRYP_InitTypeDef DES_CRYP_InitStructure;
CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure;
CRYP_IVInitTypeDef DES_CRYP_IVInitStructure;
__IO uint32_t counter = 0;
uint32_t busystatus = 0;
ErrorStatus status = SUCCESS;
uint32_t keyaddr = (uint32_t)Key;
uint32_t inputaddr = (uint32_t)Input;
uint32_t outputaddr = (uint32_t)Output;
uint32_t ivaddr = (uint32_t)InitVectors;
uint32_t i = 0;
/* Crypto structures initialisation*/
CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure);
/* Crypto Init for Encryption process */
if(Mode == MODE_ENCRYPT) /* DES encryption */
{
DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
}
else /*if(Mode == MODE_DECRYPT)*/ /* DES decryption */
{
DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
}
DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_CBC;
DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
CRYP_Init(&DES_CRYP_InitStructure);
/* Key Initialisation */
DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
CRYP_KeyInit(& DES_CRYP_KeyInitStructure);
/* Initialization Vectors */
DES_CRYP_IVInitStructure.CRYP_IV0Left = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
DES_CRYP_IVInitStructure.CRYP_IV0Right= __REV(*(uint32_t*)(ivaddr));
CRYP_IVInit(&DES_CRYP_IVInitStructure);
/* Flush IN/OUT FIFO */
CRYP_FIFOFlush();
/* Enable Crypto processor */
CRYP_Cmd(ENABLE);
for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
{
/* Write the Input block in the Input FIFO */
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
/* Wait until the complete message has been processed */
counter = 0;
do
{
busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
counter++;
}while ((counter != DESBUSY_TIMEOUT) && (busystatus != RESET));
if (busystatus != RESET)
{
status = ERROR;
}
else
{
/* Read the Output block from the Output FIFO */
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
}
}
/* Disable Crypto */
CRYP_Cmd(DISABLE);
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

308
source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_cryp_tdes.c Executable file
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@@ -0,0 +1,308 @@
/**
******************************************************************************
* @file stm32f4xx_cryp_tdes.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides high level functions to encrypt and decrypt an
* input message using TDES in ECB/CBC modes .
* It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
* peripheral.
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Enable The CRYP controller clock using
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
*
* 2. Encrypt and decrypt using TDES in ECB Mode using CRYP_TDES_ECB()
* function.
*
* 3. Encrypt and decrypt using TDES in CBC Mode using CRYP_TDES_CBC()
* function.
*
* @endverbatim
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_cryp.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup CRYP
* @brief CRYP driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define TDESBUSY_TIMEOUT ((uint32_t) 0x00010000)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CRYP_Private_Functions
* @{
*/
/** @defgroup CRYP_Group7 High Level TDES functions
* @brief High Level TDES functions
*
@verbatim
===============================================================================
High Level TDES functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Encrypt and decrypt using TDES in ECB Mode
* @param Mode: encryption or decryption Mode.
* This parameter can be one of the following values:
* @arg MODE_ENCRYPT: Encryption
* @arg MODE_DECRYPT: Decryption
* @param Key: Key used for TDES algorithm.
* @param Ilength: length of the Input buffer, must be a multiple of 8.
* @param Input: pointer to the Input buffer.
* @param Output: pointer to the returned buffer.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Operation done
* - ERROR: Operation failed
*/
ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input,
uint32_t Ilength, uint8_t *Output)
{
CRYP_InitTypeDef TDES_CRYP_InitStructure;
CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure;
__IO uint32_t counter = 0;
uint32_t busystatus = 0;
ErrorStatus status = SUCCESS;
uint32_t keyaddr = (uint32_t)Key;
uint32_t inputaddr = (uint32_t)Input;
uint32_t outputaddr = (uint32_t)Output;
uint32_t i = 0;
/* Crypto structures initialisation*/
CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure);
/* Crypto Init for Encryption process */
if(Mode == MODE_ENCRYPT) /* TDES encryption */
{
TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
}
else /*if(Mode == MODE_DECRYPT)*/ /* TDES decryption */
{
TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
}
TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB;
TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
CRYP_Init(&TDES_CRYP_InitStructure);
/* Key Initialisation */
TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
CRYP_KeyInit(& TDES_CRYP_KeyInitStructure);
/* Flush IN/OUT FIFO */
CRYP_FIFOFlush();
/* Enable Crypto processor */
CRYP_Cmd(ENABLE);
for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
{
/* Write the Input block in the Input FIFO */
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
/* Wait until the complete message has been processed */
counter = 0;
do
{
busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
counter++;
}while ((counter != TDESBUSY_TIMEOUT) && (busystatus != RESET));
if (busystatus != RESET)
{
status = ERROR;
}
else
{
/* Read the Output block from the Output FIFO */
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
}
}
/* Disable Crypto */
CRYP_Cmd(DISABLE);
return status;
}
/**
* @brief Encrypt and decrypt using TDES in CBC Mode
* @param Mode: encryption or decryption Mode.
* This parameter can be one of the following values:
* @arg MODE_ENCRYPT: Encryption
* @arg MODE_DECRYPT: Decryption
* @param Key: Key used for TDES algorithm.
* @param InitVectors: Initialisation Vectors used for TDES algorithm.
* @param Input: pointer to the Input buffer.
* @param Ilength: length of the Input buffer, must be a multiple of 8.
* @param Output: pointer to the returned buffer.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Operation done
* - ERROR: Operation failed
*/
ErrorStatus CRYP_TDES_CBC(uint8_t Mode, uint8_t Key[24], uint8_t InitVectors[8],
uint8_t *Input, uint32_t Ilength, uint8_t *Output)
{
CRYP_InitTypeDef TDES_CRYP_InitStructure;
CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure;
CRYP_IVInitTypeDef TDES_CRYP_IVInitStructure;
__IO uint32_t counter = 0;
uint32_t busystatus = 0;
ErrorStatus status = SUCCESS;
uint32_t keyaddr = (uint32_t)Key;
uint32_t inputaddr = (uint32_t)Input;
uint32_t outputaddr = (uint32_t)Output;
uint32_t ivaddr = (uint32_t)InitVectors;
uint32_t i = 0;
/* Crypto structures initialisation*/
CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure);
/* Crypto Init for Encryption process */
if(Mode == MODE_ENCRYPT) /* TDES encryption */
{
TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
}
else
{
TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
}
TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_CBC;
TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
CRYP_Init(&TDES_CRYP_InitStructure);
/* Key Initialisation */
TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
keyaddr+=4;
TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
CRYP_KeyInit(& TDES_CRYP_KeyInitStructure);
/* Initialization Vectors */
TDES_CRYP_IVInitStructure.CRYP_IV0Left = __REV(*(uint32_t*)(ivaddr));
ivaddr+=4;
TDES_CRYP_IVInitStructure.CRYP_IV0Right= __REV(*(uint32_t*)(ivaddr));
CRYP_IVInit(&TDES_CRYP_IVInitStructure);
/* Flush IN/OUT FIFO */
CRYP_FIFOFlush();
/* Enable Crypto processor */
CRYP_Cmd(ENABLE);
for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
{
/* Write the Input block in the Input FIFO */
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
CRYP_DataIn(*(uint32_t*)(inputaddr));
inputaddr+=4;
/* Wait until the complete message has been processed */
counter = 0;
do
{
busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
counter++;
}while ((counter != TDESBUSY_TIMEOUT) && (busystatus != RESET));
if (busystatus != RESET)
{
status = ERROR;
}
else
{
/* Read the Output block from the Output FIFO */
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
*(uint32_t*)(outputaddr) = CRYP_DataOut();
outputaddr+=4;
}
}
/* Disable Crypto */
CRYP_Cmd(DISABLE);
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_dac.c Executable file
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@@ -0,0 +1,701 @@
/**
******************************************************************************
* @file stm32f4xx_dac.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Digital-to-Analog Converter (DAC) peripheral:
* - DAC channels configuration: trigger, output buffer, data format
* - DMA management
* - Interrupts and flags management
*
* @verbatim
*
* ===================================================================
* DAC Peripheral features
* ===================================================================
*
* DAC Channels
* =============
* The device integrates two 12-bit Digital Analog Converters that can
* be used independently or simultaneously (dual mode):
* 1- DAC channel1 with DAC_OUT1 (PA4) as output
* 1- DAC channel2 with DAC_OUT2 (PA5) as output
*
* DAC Triggers
* =============
* Digital to Analog conversion can be non-triggered using DAC_Trigger_None
* and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register
* using DAC_SetChannel1Data() / DAC_SetChannel2Data() functions.
*
* Digital to Analog conversion can be triggered by:
* 1- External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
* The used pin (GPIOx_Pin9) must be configured in input mode.
*
* 2- Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
* (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
* The timer TRGO event should be selected using TIM_SelectOutputTrigger()
*
* 3- Software using DAC_Trigger_Software
*
* DAC Buffer mode feature
* ========================
* Each DAC channel integrates an output buffer that can be used to
* reduce the output impedance, and to drive external loads directly
* without having to add an external operational amplifier.
* To enable, the output buffer use
* DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
*
* Refer to the device datasheet for more details about output
* impedance value with and without output buffer.
*
* DAC wave generation feature
* =============================
* Both DAC channels can be used to generate
* 1- Noise wave using DAC_WaveGeneration_Noise
* 2- Triangle wave using DAC_WaveGeneration_Triangle
*
* Wave generation can be disabled using DAC_WaveGeneration_None
*
* DAC data format
* ================
* The DAC data format can be:
* 1- 8-bit right alignment using DAC_Align_8b_R
* 2- 12-bit left alignment using DAC_Align_12b_L
* 3- 12-bit right alignment using DAC_Align_12b_R
*
* DAC data value to voltage correspondence
* ========================================
* The analog output voltage on each DAC channel pin is determined
* by the following equation:
* DAC_OUTx = VREF+ * DOR / 4095
* with DOR is the Data Output Register
* VEF+ is the input voltage reference (refer to the device datasheet)
* e.g. To set DAC_OUT1 to 0.7V, use
* DAC_SetChannel1Data(DAC_Align_12b_R, 868);
* Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
*
* DMA requests
* =============
* A DMA1 request can be generated when an external trigger (but not
* a software trigger) occurs if DMA1 requests are enabled using
* DAC_DMACmd()
* DMA1 requests are mapped as following:
* 1- DAC channel1 : mapped on DMA1 Stream5 channel7 which must be
* already configured
* 2- DAC channel2 : mapped on DMA1 Stream6 channel7 which must be
* already configured
*
* ===================================================================
* How to use this driver
* ===================================================================
* - DAC APB clock must be enabled to get write access to DAC
* registers using
* RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
* - Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
* - Configure the DAC channel using DAC_Init() function
* - Enable the DAC channel using DAC_Cmd() function
*
* @endverbatim
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_dac.h"
#include "stm32f4xx_rcc.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup DAC
* @brief DAC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* CR register Mask */
#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
/* DAC Dual Channels SWTRIG masks */
#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
/* DHR registers offsets */
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
#define DHR12R2_OFFSET ((uint32_t)0x00000014)
#define DHR12RD_OFFSET ((uint32_t)0x00000020)
/* DOR register offset */
#define DOR_OFFSET ((uint32_t)0x0000002C)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DAC_Private_Functions
* @{
*/
/** @defgroup DAC_Group1 DAC channels configuration
* @brief DAC channels configuration: trigger, output buffer, data format
*
@verbatim
===============================================================================
DAC channels configuration: trigger, output buffer, data format
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the DAC peripheral registers to their default reset values.
* @param None
* @retval None
*/
void DAC_DeInit(void)
{
/* Enable DAC reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
/* Release DAC from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
}
/**
* @brief Initializes the DAC peripheral according to the specified parameters
* in the DAC_InitStruct.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains
* the configuration information for the specified DAC channel.
* @retval None
*/
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
{
uint32_t tmpreg1 = 0, tmpreg2 = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
/*---------------------------- DAC CR Configuration --------------------------*/
/* Get the DAC CR value */
tmpreg1 = DAC->CR;
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
/* Configure for the selected DAC channel: buffer output, trigger,
wave generation, mask/amplitude for wave generation */
/* Set TSELx and TENx bits according to DAC_Trigger value */
/* Set WAVEx bits according to DAC_WaveGeneration value */
/* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
/* Set BOFFx bit according to DAC_OutputBuffer value */
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \
DAC_InitStruct->DAC_OutputBuffer);
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << DAC_Channel;
/* Write to DAC CR */
DAC->CR = tmpreg1;
}
/**
* @brief Fills each DAC_InitStruct member with its default value.
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
{
/*--------------- Reset DAC init structure parameters values -----------------*/
/* Initialize the DAC_Trigger member */
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
/* Initialize the DAC_WaveGeneration member */
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
/* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
/* Initialize the DAC_OutputBuffer member */
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
}
/**
* @brief Enables or disables the specified DAC channel.
* @param DAC_Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the DAC channel.
* This parameter can be: ENABLE or DISABLE.
* @note When the DAC channel is enabled the trigger source can no more be modified.
* @retval None
*/
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DAC channel */
DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
}
else
{
/* Disable the selected DAC channel */
DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
}
}
/**
* @brief Enables or disables the selected DAC channel software trigger.
* @param DAC_Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the selected DAC channel software trigger.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for the selected DAC channel */
DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
}
else
{
/* Disable software trigger for the selected DAC channel */
DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
}
}
/**
* @brief Enables or disables simultaneously the two DAC channels software triggers.
* @param NewState: new state of the DAC channels software triggers.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for both DAC channels */
DAC->SWTRIGR |= DUAL_SWTRIG_SET;
}
else
{
/* Disable software trigger for both DAC channels */
DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
}
}
/**
* @brief Enables or disables the selected DAC channel wave generation.
* @param DAC_Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_Wave: specifies the wave type to enable or disable.
* This parameter can be one of the following values:
* @arg DAC_Wave_Noise: noise wave generation
* @arg DAC_Wave_Triangle: triangle wave generation
* @param NewState: new state of the selected DAC channel wave generation.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_WAVE(DAC_Wave));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected wave generation for the selected DAC channel */
DAC->CR |= DAC_Wave << DAC_Channel;
}
else
{
/* Disable the selected wave generation for the selected DAC channel */
DAC->CR &= ~(DAC_Wave << DAC_Channel);
}
}
/**
* @brief Set the specified data holding register value for DAC channel1.
* @param DAC_Align: Specifies the data alignment for DAC channel1.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignment selected
* @arg DAC_Align_12b_L: 12bit left data alignment selected
* @arg DAC_Align_12b_R: 12bit right data alignment selected
* @param Data: Data to be loaded in the selected data holding register.
* @retval None
*/
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data));
tmp = (uint32_t)DAC_BASE;
tmp += DHR12R1_OFFSET + DAC_Align;
/* Set the DAC channel1 selected data holding register */
*(__IO uint32_t *) tmp = Data;
}
/**
* @brief Set the specified data holding register value for DAC channel2.
* @param DAC_Align: Specifies the data alignment for DAC channel2.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignment selected
* @arg DAC_Align_12b_L: 12bit left data alignment selected
* @arg DAC_Align_12b_R: 12bit right data alignment selected
* @param Data: Data to be loaded in the selected data holding register.
* @retval None
*/
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data));
tmp = (uint32_t)DAC_BASE;
tmp += DHR12R2_OFFSET + DAC_Align;
/* Set the DAC channel2 selected data holding register */
*(__IO uint32_t *)tmp = Data;
}
/**
* @brief Set the specified data holding register value for dual channel DAC.
* @param DAC_Align: Specifies the data alignment for dual channel DAC.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignment selected
* @arg DAC_Align_12b_L: 12bit left data alignment selected
* @arg DAC_Align_12b_R: 12bit right data alignment selected
* @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register.
* @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register.
* @note In dual mode, a unique register access is required to write in both
* DAC channels at the same time.
* @retval None
*/
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
{
uint32_t data = 0, tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data1));
assert_param(IS_DAC_DATA(Data2));
/* Calculate and set dual DAC data holding register value */
if (DAC_Align == DAC_Align_8b_R)
{
data = ((uint32_t)Data2 << 8) | Data1;
}
else
{
data = ((uint32_t)Data2 << 16) | Data1;
}
tmp = (uint32_t)DAC_BASE;
tmp += DHR12RD_OFFSET + DAC_Align;
/* Set the dual DAC selected data holding register */
*(__IO uint32_t *)tmp = data;
}
/**
* @brief Returns the last data output value of the selected DAC channel.
* @param DAC_Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @retval The selected DAC channel data output value.
*/
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
tmp = (uint32_t) DAC_BASE ;
tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
/* Returns the DAC channel data output register value */
return (uint16_t) (*(__IO uint32_t*) tmp);
}
/**
* @}
*/
/** @defgroup DAC_Group2 DMA management functions
* @brief DMA management functions
*
@verbatim
===============================================================================
DMA management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified DAC channel DMA request.
* @note When enabled DMA1 is generated when an external trigger (EXTI Line9,
* TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8 but not a software trigger) occurs.
* @param DAC_Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the selected DAC channel DMA request.
* This parameter can be: ENABLE or DISABLE.
* @note The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be
* already configured.
* @note The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be
* already configured.
* @retval None
*/
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DAC channel DMA request */
DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
}
else
{
/* Disable the selected DAC channel DMA request */
DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
}
}
/**
* @}
*/
/** @defgroup DAC_Group3 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
Interrupts and flags management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified DAC interrupts.
* @param DAC_Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
* This parameter can be the following values:
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
* @note The DMA underrun occurs when a second external trigger arrives before the
* acknowledgement for the first external trigger is received (first request).
* @param NewState: new state of the specified DAC interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_DAC_IT(DAC_IT));
if (NewState != DISABLE)
{
/* Enable the selected DAC interrupts */
DAC->CR |= (DAC_IT << DAC_Channel);
}
else
{
/* Disable the selected DAC interrupts */
DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
}
}
/**
* @brief Checks whether the specified DAC flag is set or not.
* @param DAC_Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_FLAG: specifies the flag to check.
* This parameter can be only of the following value:
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
* @note The DMA underrun occurs when a second external trigger arrives before the
* acknowledgement for the first external trigger is received (first request).
* @retval The new state of DAC_FLAG (SET or RESET).
*/
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_FLAG(DAC_FLAG));
/* Check the status of the specified DAC flag */
if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
{
/* DAC_FLAG is set */
bitstatus = SET;
}
else
{
/* DAC_FLAG is reset */
bitstatus = RESET;
}
/* Return the DAC_FLAG status */
return bitstatus;
}
/**
* @brief Clears the DAC channel's pending flags.
* @param DAC_Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_FLAG: specifies the flag to clear.
* This parameter can be of the following value:
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
* @note The DMA underrun occurs when a second external trigger arrives before the
* acknowledgement for the first external trigger is received (first request).
* @retval None
*/
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_FLAG(DAC_FLAG));
/* Clear the selected DAC flags */
DAC->SR = (DAC_FLAG << DAC_Channel);
}
/**
* @brief Checks whether the specified DAC interrupt has occurred or not.
* @param DAC_Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_IT: specifies the DAC interrupt source to check.
* This parameter can be the following values:
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
* @note The DMA underrun occurs when a second external trigger arrives before the
* acknowledgement for the first external trigger is received (first request).
* @retval The new state of DAC_IT (SET or RESET).
*/
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_IT(DAC_IT));
/* Get the DAC_IT enable bit status */
enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
/* Check the status of the specified DAC interrupt */
if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
{
/* DAC_IT is set */
bitstatus = SET;
}
else
{
/* DAC_IT is reset */
bitstatus = RESET;
}
/* Return the DAC_IT status */
return bitstatus;
}
/**
* @brief Clears the DAC channel's interrupt pending bits.
* @param DAC_Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_IT: specifies the DAC interrupt pending bit to clear.
* This parameter can be the following values:
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
* @note The DMA underrun occurs when a second external trigger arrives before the
* acknowledgement for the first external trigger is received (first request).
* @retval None
*/
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_IT(DAC_IT));
/* Clear the selected DAC interrupt pending bits */
DAC->SR = (DAC_IT << DAC_Channel);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_dbgmcu.c Executable file
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/**
******************************************************************************
* @file stm32f4xx_dbgmcu.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides all the DBGMCU firmware functions.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_dbgmcu.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup DBGMCU
* @brief DBGMCU driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DBGMCU_Private_Functions
* @{
*/
/**
* @brief Returns the device revision identifier.
* @param None
* @retval Device revision identifier
*/
uint32_t DBGMCU_GetREVID(void)
{
return(DBGMCU->IDCODE >> 16);
}
/**
* @brief Returns the device identifier.
* @param None
* @retval Device identifier
*/
uint32_t DBGMCU_GetDEVID(void)
{
return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
}
/**
* @brief Configures low power mode behavior when the MCU is in Debug mode.
* @param DBGMCU_Periph: specifies the low power mode.
* This parameter can be any combination of the following values:
* @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
* @arg DBGMCU_STOP: Keep debugger connection during STOP mode
* @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
* @param NewState: new state of the specified low power mode in Debug mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
DBGMCU->CR |= DBGMCU_Periph;
}
else
{
DBGMCU->CR &= ~DBGMCU_Periph;
}
}
/**
* @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
* @param DBGMCU_Periph: specifies the APB1 peripheral.
* This parameter can be any combination of the following values:
* @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
* @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
* @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
* @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
* @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
* @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
* @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
* @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
* @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
* @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped when Core is halted.
* @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
* @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
* @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
* @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
* @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted
* @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted
* @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
DBGMCU->APB1FZ |= DBGMCU_Periph;
}
else
{
DBGMCU->APB1FZ &= ~DBGMCU_Periph;
}
}
/**
* @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
* @param DBGMCU_Periph: specifies the APB2 peripheral.
* This parameter can be any combination of the following values:
* @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
* @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
* @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
* @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
* @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
* @param NewState: new state of the specified peripheral in Debug mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
DBGMCU->APB2FZ |= DBGMCU_Periph;
}
else
{
DBGMCU->APB2FZ &= ~DBGMCU_Periph;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_dcmi.c Executable file
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/**
******************************************************************************
* @file stm32f4xx_dcmi.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the DCMI peripheral:
* - Initialization and Configuration
* - Image capture functions
* - Interrupts and flags management
*
* @verbatim
*
*
* ===================================================================
* How to use this driver
* ===================================================================
*
* The sequence below describes how to use this driver to capture image
* from a camera module connected to the DCMI Interface.
* This sequence does not take into account the configuration of the
* camera module, which should be made before to configure and enable
* the DCMI to capture images.
*
* 1. Enable the clock for the DCMI and associated GPIOs using the following functions:
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE);
* RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
*
* 2. DCMI pins configuration
* - Connect the involved DCMI pins to AF13 using the following function
* GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI);
* - Configure these DCMI pins in alternate function mode by calling the function
* GPIO_Init();
*
* 3. Declare a DCMI_InitTypeDef structure, for example:
* DCMI_InitTypeDef DCMI_InitStructure;
* and fill the DCMI_InitStructure variable with the allowed values
* of the structure member.
*
* 4. Initialize the DCMI interface by calling the function
* DCMI_Init(&DCMI_InitStructure);
*
* 5. Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
* register to the destination memory buffer.
*
* 6. Enable DCMI interface using the function
* DCMI_Cmd(ENABLE);
*
* 7. Start the image capture using the function
* DCMI_CaptureCmd(ENABLE);
*
* 8. At this stage the DCMI interface waits for the first start of frame,
* then a DMA request is generated continuously/once (depending on the
* mode used, Continuous/Snapshot) to transfer the received data into
* the destination memory.
*
* @note If you need to capture only a rectangular window from the received
* image, you have to use the DCMI_CROPConfig() function to configure
* the coordinates and size of the window to be captured, then enable
* the Crop feature using DCMI_CROPCmd(ENABLE);
* In this case, the Crop configuration should be made before to enable
* and start the DCMI interface.
*
* @endverbatim
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_dcmi.h"
#include "stm32f4xx_rcc.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup DCMI
* @brief DCMI driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DCMI_Private_Functions
* @{
*/
/** @defgroup DCMI_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
Initialization and Configuration functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the DCMI registers to their default reset values.
* @param None
* @retval None
*/
void DCMI_DeInit(void)
{
DCMI->CR = 0x0;
DCMI->IER = 0x0;
DCMI->ICR = 0x1F;
DCMI->ESCR = 0x0;
DCMI->ESUR = 0x0;
DCMI->CWSTRTR = 0x0;
DCMI->CWSIZER = 0x0;
}
/**
* @brief Initializes the DCMI according to the specified parameters in the DCMI_InitStruct.
* @param DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure that contains
* the configuration information for the DCMI.
* @retval None
*/
void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct)
{
uint32_t temp = 0x0;
/* Check the parameters */
assert_param(IS_DCMI_CAPTURE_MODE(DCMI_InitStruct->DCMI_CaptureMode));
assert_param(IS_DCMI_SYNCHRO(DCMI_InitStruct->DCMI_SynchroMode));
assert_param(IS_DCMI_PCKPOLARITY(DCMI_InitStruct->DCMI_PCKPolarity));
assert_param(IS_DCMI_VSPOLARITY(DCMI_InitStruct->DCMI_VSPolarity));
assert_param(IS_DCMI_HSPOLARITY(DCMI_InitStruct->DCMI_HSPolarity));
assert_param(IS_DCMI_CAPTURE_RATE(DCMI_InitStruct->DCMI_CaptureRate));
assert_param(IS_DCMI_EXTENDED_DATA(DCMI_InitStruct->DCMI_ExtendedDataMode));
/* The DCMI configuration registers should be programmed correctly before
enabling the CR_ENABLE Bit and the CR_CAPTURE Bit */
DCMI->CR &= ~(DCMI_CR_ENABLE | DCMI_CR_CAPTURE);
/* Reset the old DCMI configuration */
temp = DCMI->CR;
temp &= ~((uint32_t)DCMI_CR_CM | DCMI_CR_ESS | DCMI_CR_PCKPOL |
DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 |
DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1);
/* Sets the new configuration of the DCMI peripheral */
temp |= ((uint32_t)DCMI_InitStruct->DCMI_CaptureMode |
DCMI_InitStruct->DCMI_SynchroMode |
DCMI_InitStruct->DCMI_PCKPolarity |
DCMI_InitStruct->DCMI_VSPolarity |
DCMI_InitStruct->DCMI_HSPolarity |
DCMI_InitStruct->DCMI_CaptureRate |
DCMI_InitStruct->DCMI_ExtendedDataMode);
DCMI->CR = temp;
}
/**
* @brief Fills each DCMI_InitStruct member with its default value.
* @param DCMI_InitStruct : pointer to a DCMI_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct)
{
/* Set the default configuration */
DCMI_InitStruct->DCMI_CaptureMode = DCMI_CaptureMode_Continuous;
DCMI_InitStruct->DCMI_SynchroMode = DCMI_SynchroMode_Hardware;
DCMI_InitStruct->DCMI_PCKPolarity = DCMI_PCKPolarity_Falling;
DCMI_InitStruct->DCMI_VSPolarity = DCMI_VSPolarity_Low;
DCMI_InitStruct->DCMI_HSPolarity = DCMI_HSPolarity_Low;
DCMI_InitStruct->DCMI_CaptureRate = DCMI_CaptureRate_All_Frame;
DCMI_InitStruct->DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b;
}
/**
* @brief Initializes the DCMI peripheral CROP mode according to the specified
* parameters in the DCMI_CROPInitStruct.
* @note This function should be called before to enable and start the DCMI interface.
* @param DCMI_CROPInitStruct: pointer to a DCMI_CROPInitTypeDef structure that
* contains the configuration information for the DCMI peripheral CROP mode.
* @retval None
*/
void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct)
{
/* Sets the CROP window coordinates */
DCMI->CWSTRTR = (uint32_t)((uint32_t)DCMI_CROPInitStruct->DCMI_HorizontalOffsetCount |
((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalStartLine << 16));
/* Sets the CROP window size */
DCMI->CWSIZER = (uint32_t)(DCMI_CROPInitStruct->DCMI_CaptureCount |
((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalLineCount << 16));
}
/**
* @brief Enables or disables the DCMI Crop feature.
* @note This function should be called before to enable and start the DCMI interface.
* @param NewState: new state of the DCMI Crop feature.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DCMI_CROPCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the DCMI Crop feature */
DCMI->CR |= (uint32_t)DCMI_CR_CROP;
}
else
{
/* Disable the DCMI Crop feature */
DCMI->CR &= ~(uint32_t)DCMI_CR_CROP;
}
}
/**
* @brief Sets the embedded synchronization codes
* @param DCMI_CodesInitTypeDef: pointer to a DCMI_CodesInitTypeDef structure that
* contains the embedded synchronization codes for the DCMI peripheral.
* @retval None
*/
void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct)
{
DCMI->ESCR = (uint32_t)(DCMI_CodesInitStruct->DCMI_FrameStartCode |
((uint32_t)DCMI_CodesInitStruct->DCMI_LineStartCode << 8)|
((uint32_t)DCMI_CodesInitStruct->DCMI_LineEndCode << 16)|
((uint32_t)DCMI_CodesInitStruct->DCMI_FrameEndCode << 24));
}
/**
* @brief Enables or disables the DCMI JPEG format.
* @note The Crop and Embedded Synchronization features cannot be used in this mode.
* @param NewState: new state of the DCMI JPEG format.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DCMI_JPEGCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the DCMI JPEG format */
DCMI->CR |= (uint32_t)DCMI_CR_JPEG;
}
else
{
/* Disable the DCMI JPEG format */
DCMI->CR &= ~(uint32_t)DCMI_CR_JPEG;
}
}
/**
* @}
*/
/** @defgroup DCMI_Group2 Image capture functions
* @brief Image capture functions
*
@verbatim
===============================================================================
Image capture functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the DCMI interface.
* @param NewState: new state of the DCMI interface.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DCMI_Cmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the DCMI by setting ENABLE bit */
DCMI->CR |= (uint32_t)DCMI_CR_ENABLE;
}
else
{
/* Disable the DCMI by clearing ENABLE bit */
DCMI->CR &= ~(uint32_t)DCMI_CR_ENABLE;
}
}
/**
* @brief Enables or disables the DCMI Capture.
* @param NewState: new state of the DCMI capture.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DCMI_CaptureCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the DCMI Capture */
DCMI->CR |= (uint32_t)DCMI_CR_CAPTURE;
}
else
{
/* Disable the DCMI Capture */
DCMI->CR &= ~(uint32_t)DCMI_CR_CAPTURE;
}
}
/**
* @brief Reads the data stored in the DR register.
* @param None
* @retval Data register value
*/
uint32_t DCMI_ReadData(void)
{
return DCMI->DR;
}
/**
* @}
*/
/** @defgroup DCMI_Group3 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
Interrupts and flags management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the DCMI interface interrupts.
* @param DCMI_IT: specifies the DCMI interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
* @arg DCMI_IT_OVF: Overflow interrupt mask
* @arg DCMI_IT_ERR: Synchronization error interrupt mask
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask
* @arg DCMI_IT_LINE: Line interrupt mask
* @param NewState: new state of the specified DCMI interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DCMI_CONFIG_IT(DCMI_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the Interrupt sources */
DCMI->IER |= DCMI_IT;
}
else
{
/* Disable the Interrupt sources */
DCMI->IER &= (uint16_t)(~DCMI_IT);
}
}
/**
* @brief Checks whether the DCMI interface flag is set or not.
* @param DCMI_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
* @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask
* @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
* @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
* @arg DCMI_FLAG_LINERI: Line Raw flag mask
* @arg DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask
* @arg DCMI_FLAG_OVFMI: Overflow Masked flag mask
* @arg DCMI_FLAG_ERRMI: Synchronization error Masked flag mask
* @arg DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask
* @arg DCMI_FLAG_LINEMI: Line Masked flag mask
* @arg DCMI_FLAG_HSYNC: HSYNC flag mask
* @arg DCMI_FLAG_VSYNC: VSYNC flag mask
* @arg DCMI_FLAG_FNE: Fifo not empty flag mask
* @retval The new state of DCMI_FLAG (SET or RESET).
*/
FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t dcmireg, tempreg = 0;
/* Check the parameters */
assert_param(IS_DCMI_GET_FLAG(DCMI_FLAG));
/* Get the DCMI register index */
dcmireg = (((uint16_t)DCMI_FLAG) >> 12);
if (dcmireg == 0x01) /* The FLAG is in RISR register */
{
tempreg= DCMI->RISR;
}
else if (dcmireg == 0x02) /* The FLAG is in SR register */
{
tempreg = DCMI->SR;
}
else /* The FLAG is in MISR register */
{
tempreg = DCMI->MISR;
}
if ((tempreg & DCMI_FLAG) != (uint16_t)RESET )
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the DCMI_FLAG status */
return bitstatus;
}
/**
* @brief Clears the DCMI's pending flags.
* @param DCMI_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
* @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask
* @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
* @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
* @arg DCMI_FLAG_LINERI: Line Raw flag mask
* @retval None
*/
void DCMI_ClearFlag(uint16_t DCMI_FLAG)
{
/* Check the parameters */
assert_param(IS_DCMI_CLEAR_FLAG(DCMI_FLAG));
/* Clear the flag by writing in the ICR register 1 in the corresponding
Flag position*/
DCMI->ICR = DCMI_FLAG;
}
/**
* @brief Checks whether the DCMI interrupt has occurred or not.
* @param DCMI_IT: specifies the DCMI interrupt source to check.
* This parameter can be one of the following values:
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
* @arg DCMI_IT_OVF: Overflow interrupt mask
* @arg DCMI_IT_ERR: Synchronization error interrupt mask
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask
* @arg DCMI_IT_LINE: Line interrupt mask
* @retval The new state of DCMI_IT (SET or RESET).
*/
ITStatus DCMI_GetITStatus(uint16_t DCMI_IT)
{
ITStatus bitstatus = RESET;
uint32_t itstatus = 0;
/* Check the parameters */
assert_param(IS_DCMI_GET_IT(DCMI_IT));
itstatus = DCMI->MISR & DCMI_IT; /* Only masked interrupts are checked */
if ((itstatus != (uint16_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the DCMI's interrupt pending bits.
* @param DCMI_IT: specifies the DCMI interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
* @arg DCMI_IT_OVF: Overflow interrupt mask
* @arg DCMI_IT_ERR: Synchronization error interrupt mask
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask
* @arg DCMI_IT_LINE: Line interrupt mask
* @retval None
*/
void DCMI_ClearITPendingBit(uint16_t DCMI_IT)
{
/* Clear the interrupt pending Bit by writing in the ICR register 1 in the
corresponding pending Bit position*/
DCMI->ICR = DCMI_IT;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_exti.c Executable file
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/**
******************************************************************************
* @file stm32f4xx_exti.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the EXTI peripheral:
* - Initialization and Configuration
* - Interrupts and flags management
*
* @verbatim
*
* ===================================================================
* EXTI features
* ===================================================================
*
* External interrupt/event lines are mapped as following:
* 1- All available GPIO pins are connected to the 16 external
* interrupt/event lines from EXTI0 to EXTI15.
* 2- EXTI line 16 is connected to the PVD Output
* 3- EXTI line 17 is connected to the RTC Alarm event
* 4- EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event
* 5- EXTI line 19 is connected to the Ethernet Wakeup event
* 6- EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event
* 7- EXTI line 21 is connected to the RTC Tamper and Time Stamp events
* 8- EXTI line 22 is connected to the RTC Wakeup event
*
* ===================================================================
* How to use this driver
* ===================================================================
*
* In order to use an I/O pin as an external interrupt source, follow
* steps below:
* 1- Configure the I/O in input mode using GPIO_Init()
* 2- Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig()
* 3- Select the mode(interrupt, event) and configure the trigger
* selection (Rising, falling or both) using EXTI_Init()
* 4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
*
* @note SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
* registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
*
* @endverbatim
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_exti.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup EXTI
* @brief EXTI driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup EXTI_Private_Functions
* @{
*/
/** @defgroup EXTI_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
Initialization and Configuration functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the EXTI peripheral registers to their default reset values.
* @param None
* @retval None
*/
void EXTI_DeInit(void)
{
EXTI->IMR = 0x00000000;
EXTI->EMR = 0x00000000;
EXTI->RTSR = 0x00000000;
EXTI->FTSR = 0x00000000;
EXTI->PR = 0x007FFFFF;
}
/**
* @brief Initializes the EXTI peripheral according to the specified
* parameters in the EXTI_InitStruct.
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
* that contains the configuration information for the EXTI peripheral.
* @retval None
*/
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
{
uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
tmp = (uint32_t)EXTI_BASE;
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
{
/* Clear EXTI line configuration */
EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
tmp += EXTI_InitStruct->EXTI_Mode;
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
/* Clear Rising Falling edge configuration */
EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
/* Select the trigger for the selected external interrupts */
if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
{
/* Rising Falling edge */
EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
}
else
{
tmp = (uint32_t)EXTI_BASE;
tmp += EXTI_InitStruct->EXTI_Trigger;
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
}
}
else
{
tmp += EXTI_InitStruct->EXTI_Mode;
/* Disable the selected external lines */
*(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
}
}
/**
* @brief Fills each EXTI_InitStruct member with its reset value.
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
{
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
}
/**
* @brief Generates a Software interrupt on selected EXTI line.
* @param EXTI_Line: specifies the EXTI line on which the software interrupt
* will be generated.
* This parameter can be any combination of EXTI_Linex where x can be (0..22)
* @retval None
*/
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(EXTI_Line));
EXTI->SWIER |= EXTI_Line;
}
/**
* @}
*/
/** @defgroup EXTI_Group2 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
Interrupts and flags management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Checks whether the specified EXTI line flag is set or not.
* @param EXTI_Line: specifies the EXTI line flag to check.
* This parameter can be EXTI_Linex where x can be(0..22)
* @retval The new state of EXTI_Line (SET or RESET).
*/
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the EXTI's line pending flags.
* @param EXTI_Line: specifies the EXTI lines flags to clear.
* This parameter can be any combination of EXTI_Linex where x can be (0..22)
* @retval None
*/
void EXTI_ClearFlag(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(EXTI_Line));
EXTI->PR = EXTI_Line;
}
/**
* @brief Checks whether the specified EXTI line is asserted or not.
* @param EXTI_Line: specifies the EXTI line to check.
* This parameter can be EXTI_Linex where x can be(0..22)
* @retval The new state of EXTI_Line (SET or RESET).
*/
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
/* Check the parameters */
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
enablestatus = EXTI->IMR & EXTI_Line;
if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the EXTI's line pending bits.
* @param EXTI_Line: specifies the EXTI lines to clear.
* This parameter can be any combination of EXTI_Linex where x can be (0..22)
* @retval None
*/
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(EXTI_Line));
EXTI->PR = EXTI_Line;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_flash.c Executable file
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source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_fsmc.c Executable file
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/**
******************************************************************************
* @file stm32f4xx_fsmc.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the FSMC peripheral:
* - Interface with SRAM, PSRAM, NOR and OneNAND memories
* - Interface with NAND memories
* - Interface with 16-bit PC Card compatible memories
* - Interrupts and flags management
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_fsmc.h"
#include "stm32f4xx_rcc.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup FSMC
* @brief FSMC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* --------------------- FSMC registers bit mask ---------------------------- */
/* FSMC BCRx Mask */
#define BCR_MBKEN_SET ((uint32_t)0x00000001)
#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE)
#define BCR_FACCEN_SET ((uint32_t)0x00000040)
/* FSMC PCRx Mask */
#define PCR_PBKEN_SET ((uint32_t)0x00000004)
#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB)
#define PCR_ECCEN_SET ((uint32_t)0x00000040)
#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF)
#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup FSMC_Private_Functions
* @{
*/
/** @defgroup FSMC_Group1 NOR/SRAM Controller functions
* @brief NOR/SRAM Controller functions
*
@verbatim
===============================================================================
NOR/SRAM Controller functions
===============================================================================
The following sequence should be followed to configure the FSMC to interface with
SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank:
1. Enable the clock for the FSMC and associated GPIOs using the following functions:
RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
2. FSMC pins configuration
- Connect the involved FSMC pins to AF12 using the following function
GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
- Configure these FSMC pins in alternate function mode by calling the function
GPIO_Init();
3. Declare a FSMC_NORSRAMInitTypeDef structure, for example:
FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
and fill the FSMC_NORSRAMInitStructure variable with the allowed values of
the structure member.
4. Initialize the NOR/SRAM Controller by calling the function
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
5. Then enable the NOR/SRAM Bank, for example:
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
6. At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank.
@endverbatim
* @{
*/
/**
* @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
* reset values.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
* @retval None
*/
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
{
/* Check the parameter */
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
/* FSMC_Bank1_NORSRAM1 */
if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
{
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
}
/* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
else
{
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
}
FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
}
/**
* @brief Initializes the FSMC NOR/SRAM Banks according to the specified
* parameters in the FSMC_NORSRAMInitStruct.
* @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure
* that contains the configuration information for the FSMC NOR/SRAM
* specified Banks.
* @retval None
*/
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
{
/* Check the parameters */
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
/* Bank1 NOR/SRAM control register configuration */
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
FSMC_NORSRAMInitStruct->FSMC_MemoryType |
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
FSMC_NORSRAMInitStruct->FSMC_WrapMode |
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
{
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET;
}
/* Bank1 NOR/SRAM timing register configuration */
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
/* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
{
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
}
else
{
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
}
}
/**
* @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
* @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure
* which will be initialized.
* @retval None
*/
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
{
/* Reset NOR/SRAM Init structure parameters values */
FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
}
/**
* @brief Enables or disables the specified NOR/SRAM Memory Bank.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
* @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
{
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET;
}
else
{
/* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET;
}
}
/**
* @}
*/
/** @defgroup FSMC_Group2 NAND Controller functions
* @brief NAND Controller functions
*
@verbatim
===============================================================================
NAND Controller functions
===============================================================================
The following sequence should be followed to configure the FSMC to interface with
8-bit or 16-bit NAND memory connected to the NAND Bank:
1. Enable the clock for the FSMC and associated GPIOs using the following functions:
RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
2. FSMC pins configuration
- Connect the involved FSMC pins to AF12 using the following function
GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
- Configure these FSMC pins in alternate function mode by calling the function
GPIO_Init();
3. Declare a FSMC_NANDInitTypeDef structure, for example:
FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
and fill the FSMC_NANDInitStructure variable with the allowed values of
the structure member.
4. Initialize the NAND Controller by calling the function
FSMC_NANDInit(&FSMC_NANDInitStructure);
5. Then enable the NAND Bank, for example:
FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE);
6. At this stage you can read/write from/to the memory connected to the NAND Bank.
@note To enable the Error Correction Code (ECC), you have to use the function
FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE);
and to get the current ECC value you have to use the function
ECCval = FSMC_GetECC(FSMC_Bank3_NAND);
@endverbatim
* @{
*/
/**
* @brief Deinitializes the FSMC NAND Banks registers to their default reset values.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
* @retval None
*/
void FSMC_NANDDeInit(uint32_t FSMC_Bank)
{
/* Check the parameter */
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
if(FSMC_Bank == FSMC_Bank2_NAND)
{
/* Set the FSMC_Bank2 registers to their reset values */
FSMC_Bank2->PCR2 = 0x00000018;
FSMC_Bank2->SR2 = 0x00000040;
FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
FSMC_Bank2->PATT2 = 0xFCFCFCFC;
}
/* FSMC_Bank3_NAND */
else
{
/* Set the FSMC_Bank3 registers to their reset values */
FSMC_Bank3->PCR3 = 0x00000018;
FSMC_Bank3->SR3 = 0x00000040;
FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
FSMC_Bank3->PATT3 = 0xFCFCFCFC;
}
}
/**
* @brief Initializes the FSMC NAND Banks according to the specified parameters
* in the FSMC_NANDInitStruct.
* @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that
* contains the configuration information for the FSMC NAND specified Banks.
* @retval None
*/
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
{
uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
/* Check the parameters */
assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
/* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
PCR_MEMORYTYPE_NAND |
FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
FSMC_NANDInitStruct->FSMC_ECC |
FSMC_NANDInitStruct->FSMC_ECCPageSize |
(FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
(FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
/* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
/* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
{
/* FSMC_Bank2_NAND registers configuration */
FSMC_Bank2->PCR2 = tmppcr;
FSMC_Bank2->PMEM2 = tmppmem;
FSMC_Bank2->PATT2 = tmppatt;
}
else
{
/* FSMC_Bank3_NAND registers configuration */
FSMC_Bank3->PCR3 = tmppcr;
FSMC_Bank3->PMEM3 = tmppmem;
FSMC_Bank3->PATT3 = tmppatt;
}
}
/**
* @brief Fills each FSMC_NANDInitStruct member with its default value.
* @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which
* will be initialized.
* @retval None
*/
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
{
/* Reset NAND Init structure parameters values */
FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
}
/**
* @brief Enables or disables the specified NAND Memory Bank.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
* @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
{
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->PCR2 |= PCR_PBKEN_SET;
}
else
{
FSMC_Bank3->PCR3 |= PCR_PBKEN_SET;
}
}
else
{
/* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET;
}
else
{
FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET;
}
}
}
/**
* @brief Enables or disables the FSMC NAND ECC feature.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
* @param NewState: new state of the FSMC NAND ECC feature.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
{
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->PCR2 |= PCR_ECCEN_SET;
}
else
{
FSMC_Bank3->PCR3 |= PCR_ECCEN_SET;
}
}
else
{
/* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET;
}
else
{
FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET;
}
}
}
/**
* @brief Returns the error correction code register value.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
* @retval The Error Correction Code (ECC) value.
*/
uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
{
uint32_t eccval = 0x00000000;
if(FSMC_Bank == FSMC_Bank2_NAND)
{
/* Get the ECCR2 register value */
eccval = FSMC_Bank2->ECCR2;
}
else
{
/* Get the ECCR3 register value */
eccval = FSMC_Bank3->ECCR3;
}
/* Return the error correction code value */
return(eccval);
}
/**
* @}
*/
/** @defgroup FSMC_Group3 PCCARD Controller functions
* @brief PCCARD Controller functions
*
@verbatim
===============================================================================
PCCARD Controller functions
===============================================================================
The following sequence should be followed to configure the FSMC to interface with
16-bit PC Card compatible memory connected to the PCCARD Bank:
1. Enable the clock for the FSMC and associated GPIOs using the following functions:
RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
2. FSMC pins configuration
- Connect the involved FSMC pins to AF12 using the following function
GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
- Configure these FSMC pins in alternate function mode by calling the function
GPIO_Init();
3. Declare a FSMC_PCCARDInitTypeDef structure, for example:
FSMC_PCCARDInitTypeDef FSMC_PCCARDInitStructure;
and fill the FSMC_PCCARDInitStructure variable with the allowed values of
the structure member.
4. Initialize the PCCARD Controller by calling the function
FSMC_PCCARDInit(&FSMC_PCCARDInitStructure);
5. Then enable the PCCARD Bank:
FSMC_PCCARDCmd(ENABLE);
6. At this stage you can read/write from/to the memory connected to the PCCARD Bank.
@endverbatim
* @{
*/
/**
* @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
* @param None
* @retval None
*/
void FSMC_PCCARDDeInit(void)
{
/* Set the FSMC_Bank4 registers to their reset values */
FSMC_Bank4->PCR4 = 0x00000018;
FSMC_Bank4->SR4 = 0x00000000;
FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
FSMC_Bank4->PATT4 = 0xFCFCFCFC;
FSMC_Bank4->PIO4 = 0xFCFCFCFC;
}
/**
* @brief Initializes the FSMC PCCARD Bank according to the specified parameters
* in the FSMC_PCCARDInitStruct.
* @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure
* that contains the configuration information for the FSMC PCCARD Bank.
* @retval None
*/
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
{
/* Check the parameters */
assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
/* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
FSMC_MemoryDataWidth_16b |
(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
(FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
/* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
/* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
/* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
}
/**
* @brief Fills each FSMC_PCCARDInitStruct member with its default value.
* @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure
* which will be initialized.
* @retval None
*/
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
{
/* Reset PCCARD Init structure parameters values */
FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
}
/**
* @brief Enables or disables the PCCARD Memory Bank.
* @param NewState: new state of the PCCARD Memory Bank.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FSMC_PCCARDCmd(FunctionalState NewState)
{
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
FSMC_Bank4->PCR4 |= PCR_PBKEN_SET;
}
else
{
/* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET;
}
}
/**
* @}
*/
/** @defgroup FSMC_Group4 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
Interrupts and flags management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified FSMC interrupts.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
* @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
* @arg FSMC_IT_Level: Level edge detection interrupt.
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
* @param NewState: new state of the specified FSMC interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
{
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
assert_param(IS_FSMC_IT(FSMC_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected FSMC_Bank2 interrupts */
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->SR2 |= FSMC_IT;
}
/* Enable the selected FSMC_Bank3 interrupts */
else if (FSMC_Bank == FSMC_Bank3_NAND)
{
FSMC_Bank3->SR3 |= FSMC_IT;
}
/* Enable the selected FSMC_Bank4 interrupts */
else
{
FSMC_Bank4->SR4 |= FSMC_IT;
}
}
else
{
/* Disable the selected FSMC_Bank2 interrupts */
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
}
/* Disable the selected FSMC_Bank3 interrupts */
else if (FSMC_Bank == FSMC_Bank3_NAND)
{
FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
}
/* Disable the selected FSMC_Bank4 interrupts */
else
{
FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
}
}
}
/**
* @brief Checks whether the specified FSMC flag is set or not.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
* @param FSMC_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.
* @arg FSMC_FLAG_Level: Level detection Flag.
* @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.
* @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
* @retval The new state of FSMC_FLAG (SET or RESET).
*/
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t tmpsr = 0x00000000;
/* Check the parameters */
assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
if(FSMC_Bank == FSMC_Bank2_NAND)
{
tmpsr = FSMC_Bank2->SR2;
}
else if(FSMC_Bank == FSMC_Bank3_NAND)
{
tmpsr = FSMC_Bank3->SR3;
}
/* FSMC_Bank4_PCCARD*/
else
{
tmpsr = FSMC_Bank4->SR4;
}
/* Get the flag status */
if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/**
* @brief Clears the FSMC's pending flags.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
* @param FSMC_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.
* @arg FSMC_FLAG_Level: Level detection Flag.
* @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.
* @retval None
*/
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
{
/* Check the parameters */
assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->SR2 &= ~FSMC_FLAG;
}
else if(FSMC_Bank == FSMC_Bank3_NAND)
{
FSMC_Bank3->SR3 &= ~FSMC_FLAG;
}
/* FSMC_Bank4_PCCARD*/
else
{
FSMC_Bank4->SR4 &= ~FSMC_FLAG;
}
}
/**
* @brief Checks whether the specified FSMC interrupt has occurred or not.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
* @param FSMC_IT: specifies the FSMC interrupt source to check.
* This parameter can be one of the following values:
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
* @arg FSMC_IT_Level: Level edge detection interrupt.
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
* @retval The new state of FSMC_IT (SET or RESET).
*/
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
{
ITStatus bitstatus = RESET;
uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
/* Check the parameters */
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
assert_param(IS_FSMC_GET_IT(FSMC_IT));
if(FSMC_Bank == FSMC_Bank2_NAND)
{
tmpsr = FSMC_Bank2->SR2;
}
else if(FSMC_Bank == FSMC_Bank3_NAND)
{
tmpsr = FSMC_Bank3->SR3;
}
/* FSMC_Bank4_PCCARD*/
else
{
tmpsr = FSMC_Bank4->SR4;
}
itstatus = tmpsr & FSMC_IT;
itenable = tmpsr & (FSMC_IT >> 3);
if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the FSMC's interrupt pending bits.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
* @param FSMC_IT: specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
* @arg FSMC_IT_Level: Level edge detection interrupt.
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
* @retval None
*/
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
{
/* Check the parameters */
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
assert_param(IS_FSMC_IT(FSMC_IT));
if(FSMC_Bank == FSMC_Bank2_NAND)
{
FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
}
else if(FSMC_Bank == FSMC_Bank3_NAND)
{
FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
}
/* FSMC_Bank4_PCCARD*/
else
{
FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f4xx_gpio.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the GPIO peripheral:
* - Initialization and Configuration
* - GPIO Read and Write
* - GPIO Alternate functions configuration
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Enable the GPIO AHB clock using the following function
* RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
*
* 2. Configure the GPIO pin(s) using GPIO_Init()
* Four possible configuration are available for each pin:
* - Input: Floating, Pull-up, Pull-down.
* - Output: Push-Pull (Pull-up, Pull-down or no Pull)
* Open Drain (Pull-up, Pull-down or no Pull).
* In output mode, the speed is configurable: 2 MHz, 25 MHz,
* 50 MHz or 100 MHz.
* - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)
* Open Drain (Pull-up, Pull-down or no Pull).
* - Analog: required mode when a pin is to be used as ADC channel
* or DAC output.
*
* 3- Peripherals alternate function:
* - For ADC and DAC, configure the desired pin in analog mode using
* GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN;
* - For other peripherals (TIM, USART...):
* - Connect the pin to the desired peripherals' Alternate
* Function (AF) using GPIO_PinAFConfig() function
* - Configure the desired pin in alternate function mode using
* GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
* - Select the type, pull-up/pull-down and output speed via
* GPIO_PuPd, GPIO_OType and GPIO_Speed members
* - Call GPIO_Init() function
*
* 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
*
* 5. To set/reset the level of a pin configured in output mode use
* GPIO_SetBits()/GPIO_ResetBits()
*
* 6. During and just after reset, the alternate functions are not
* active and the GPIO pins are configured in input floating mode
* (except JTAG pins).
*
* 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as
* general-purpose (PC14 and PC15, respectively) when the LSE
* oscillator is off. The LSE has priority over the GPIO function.
*
* 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as
* general-purpose PH0 and PH1, respectively, when the HSE
* oscillator is off. The HSE has priority over the GPIO function.
*
* @endverbatim
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_gpio.h"
#include "stm32f4xx_rcc.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup GPIO
* @brief GPIO driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup GPIO_Private_Functions
* @{
*/
/** @defgroup GPIO_Group1 Initialization and Configuration
* @brief Initialization and Configuration
*
@verbatim
===============================================================================
Initialization and Configuration
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the GPIOx peripheral registers to their default reset values.
* @note By default, The GPIO pins are configured in input floating mode (except JTAG pins).
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
* @retval None
*/
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
if (GPIOx == GPIOA)
{
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE);
}
else if (GPIOx == GPIOB)
{
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE);
}
else if (GPIOx == GPIOC)
{
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE);
}
else if (GPIOx == GPIOD)
{
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE);
}
else if (GPIOx == GPIOE)
{
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE);
}
else if (GPIOx == GPIOF)
{
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE);
}
else if (GPIOx == GPIOG)
{
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE);
}
else if (GPIOx == GPIOH)
{
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);
}
else
{
if (GPIOx == GPIOI)
{
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);
}
}
}
/**
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
{
uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
/* -------------------------Configure the port pins---------------- */
/*-- GPIO Mode Configuration --*/
for (pinpos = 0x00; pinpos < 0x10; pinpos++)
{
pos = ((uint32_t)0x01) << pinpos;
/* Get the port pins position */
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
if (currentpin == pos)
{
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
{
/* Check Speed mode parameters */
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
/* Speed mode configuration */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
/* Check Output mode parameters */
assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
/* Output mode configuration*/
GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
}
/* Pull-up Pull down resistor configuration*/
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
}
}
}
/**
* @brief Fills each GPIO_InitStruct member with its default value.
* @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
* @retval None
*/
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
{
/* Reset GPIO init structure parameters values */
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
}
/**
* @brief Locks GPIO Pins configuration registers.
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be locked.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
__IO uint32_t tmp = 0x00010000;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
tmp |= GPIO_Pin;
/* Set LCKK bit */
GPIOx->LCKR = tmp;
/* Reset LCKK bit */
GPIOx->LCKR = GPIO_Pin;
/* Set LCKK bit */
GPIOx->LCKR = tmp;
/* Read LCKK bit*/
tmp = GPIOx->LCKR;
/* Read LCKK bit*/
tmp = GPIOx->LCKR;
}
/**
* @}
*/
/** @defgroup GPIO_Group2 GPIO Read and Write
* @brief GPIO Read and Write
*
@verbatim
===============================================================================
GPIO Read and Write
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Reads the specified input port pin.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* @retval The input port pin value.
*/
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
/**
* @brief Reads the specified GPIO input data port.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
* @retval GPIO input data port value.
*/
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
return ((uint16_t)GPIOx->IDR);
}
/**
* @brief Reads the specified output data port bit.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* @retval The output port pin value.
*/
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
/**
* @brief Reads the specified GPIO output data port.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
* @retval GPIO output data port value.
*/
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
return ((uint16_t)GPIOx->ODR);
}
/**
* @brief Sets the selected data port bits.
* @note This functions uses GPIOx_BSRR register to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
GPIOx->BSRRL = GPIO_Pin;
}
/**
* @brief Clears the selected data port bits.
* @note This functions uses GPIOx_BSRR register to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
GPIOx->BSRRH = GPIO_Pin;
}
/**
* @brief Sets or clears the selected data port bit.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
* @param BitVal: specifies the value to be written to the selected bit.
* This parameter can be one of the BitAction enum values:
* @arg Bit_RESET: to clear the port pin
* @arg Bit_SET: to set the port pin
* @retval None
*/
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_BIT_ACTION(BitVal));
if (BitVal != Bit_RESET)
{
GPIOx->BSRRL = GPIO_Pin;
}
else
{
GPIOx->BSRRH = GPIO_Pin ;
}
}
/**
* @brief Writes data to the specified GPIO data port.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
* @param PortVal: specifies the value to be written to the port output data register.
* @retval None
*/
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
GPIOx->ODR = PortVal;
}
/**
* @brief Toggles the specified GPIO pins..
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
* @param GPIO_Pin: Specifies the pins to be toggled.
* @retval None
*/
void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
GPIOx->ODR ^= GPIO_Pin;
}
/**
* @}
*/
/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function
* @brief GPIO Alternate functions configuration function
*
@verbatim
===============================================================================
GPIO Alternate functions configuration function
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Changes the mapping of the specified pin.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral.
* @param GPIO_PinSource: specifies the pin for the Alternate function.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
* @param GPIO_AFSelection: selects the pin to used as Alternate function.
* This parameter can be one of the following values:
* @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset)
* @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset)
* @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset)
* @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset)
* @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
* @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1
* @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1
* @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2
* @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2
* @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2
* @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3
* @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3
* @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3
* @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3
* @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4
* @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4
* @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4
* @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
* @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
* @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
* @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7
* @arg GPIO_AF_USART1: Connect USART1 pins to AF7
* @arg GPIO_AF_USART2: Connect USART2 pins to AF7
* @arg GPIO_AF_USART3: Connect USART3 pins to AF7
* @arg GPIO_AF_UART4: Connect UART4 pins to AF8
* @arg GPIO_AF_UART5: Connect UART5 pins to AF8
* @arg GPIO_AF_USART6: Connect USART6 pins to AF8
* @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9
* @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9
* @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9
* @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9
* @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9
* @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
* @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
* @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11
* @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
* @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
* @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
* @arg GPIO_AF_DCMI: Connect DCMI pins to AF13
* @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
* @retval None
*/
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
{
uint32_t temp = 0x00;
uint32_t temp_2 = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
assert_param(IS_GPIO_AF(GPIO_AF));
temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f4xx_hash.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the HASH / HMAC Processor (HASH) peripheral:
* - Initialization and Configuration functions
* - Message Digest generation functions
* - context swapping functions
* - DMA interface function
* - Interrupts and flags management
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* HASH operation :
* ----------------
* 1. Enable the HASH controller clock using
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function.
*
* 2. Initialise the HASH using HASH_Init() function.
*
* 3 . Reset the HASH processor core, so that the HASH will be ready
* to compute he message digest of a new message by using
* HASH_Reset() function.
*
* 4. Enable the HASH controller using the HASH_Cmd() function.
*
* 5. if using DMA for Data input transfer, Activate the DMA Request
* using HASH_DMACmd() function
*
* 6. if DMA is not used for data transfer, use HASH_DataIn() function
* to enter data to IN FIFO.
*
*
* 7. Configure the Number of valid bits in last word of the message
* using HASH_SetLastWordValidBitsNbr() function.
*
* 8. if the message length is not an exact multiple of 512 bits,
* then the function HASH_StartDigest() must be called to
* launch the computation of the final digest.
*
* 9. Once computed, the digest can be read using HASH_GetDigest()
* function.
*
* 10. To control HASH events you can use one of the following
* two methods:
* a- Check on HASH flags using the HASH_GetFlagStatus() function.
* b- Use HASH interrupts through the function HASH_ITConfig() at
* initialization phase and HASH_GetITStatus() function into
* interrupt routines in hashing phase.
* After checking on a flag you should clear it using HASH_ClearFlag()
* function. And after checking on an interrupt event you should
* clear it using HASH_ClearITPendingBit() function.
*
* 11. Save and restore hash processor context using
* HASH_SaveContext() and HASH_RestoreContext() functions.
*
*
*
* HMAC operation :
* ----------------
* The HMAC algorithm is used for message authentication, by
* irreversibly binding the message being processed to a key chosen
* by the user.
* For HMAC specifications, refer to "HMAC: keyed-hashing for message
* authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997"
*
* Basically, the HMAC algorithm consists of two nested hash operations:
* HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)]
* where:
* - "pad" is a sequence of zeroes needed to extend the key to the
* length of the underlying hash function data block (that is
* 512 bits for both the SHA-1 and MD5 hash algorithms)
* - "|" represents the concatenation operator
*
*
* To compute the HMAC, four different phases are required:
*
* 1. Initialise the HASH using HASH_Init() function to do HMAC
* operation.
*
* 2. The key (to be used for the inner hash function) is then given
* to the core. This operation follows the same mechanism as the
* one used to send the message in the hash operation (that is,
* by HASH_DataIn() function and, finally,
* HASH_StartDigest() function.
*
* 3. Once the last word has been entered and computation has started,
* the hash processor elaborates the key. It is then ready to
* accept the message text using the same mechanism as the one
* used to send the message in the hash operation.
*
* 4. After the first hash round, the hash processor returns "ready"
* to indicate that it is ready to receive the key to be used for
* the outer hash function (normally, this key is the same as the
* one used for the inner hash function). When the last word of
* the key is entered and computation starts, the HMAC result is
* made available using HASH_GetDigest() function.
*
*
* @endverbatim
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hash.h"
#include "stm32f4xx_rcc.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup HASH
* @brief HASH driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup HASH_Private_Functions
* @{
*/
/** @defgroup HASH_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
Initialization and Configuration functions
===============================================================================
This section provides functions allowing to
- Initialize the HASH peripheral
- Configure the HASH Processor
- MD5/SHA1,
- HASH/HMAC,
- datatype
- HMAC Key (if mode = HMAC)
- Reset the HASH Processor
@endverbatim
* @{
*/
/**
* @brief Deinitializes the HASH peripheral registers to their default reset values
* @param None
* @retval None
*/
void HASH_DeInit(void)
{
/* Enable HASH reset state */
RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE);
/* Release HASH from reset state */
RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE);
}
/**
* @brief Initializes the HASH peripheral according to the specified parameters
* in the HASH_InitStruct structure.
* @note the hash processor is reset when calling this function so that the
* HASH will be ready to compute the message digest of a new message.
* There is no need to call HASH_Reset() function.
* @param HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains
* the configuration information for the HASH peripheral.
* @note The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only
* if the algorithm mode is HMAC.
* @retval None
*/
void HASH_Init(HASH_InitTypeDef* HASH_InitStruct)
{
/* Check the parameters */
assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection));
assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType));
assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode));
/* Configure the Algorithm used, algorithm mode and the datatype */
HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE);
HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \
HASH_InitStruct->HASH_DataType | \
HASH_InitStruct->HASH_AlgoMode);
/* if algorithm mode is HMAC, set the Key */
if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC)
{
assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType));
HASH->CR &= ~HASH_CR_LKEY;
HASH->CR |= HASH_InitStruct->HASH_HMACKeyType;
}
/* Reset the HASH processor core, so that the HASH will be ready to compute
the message digest of a new message */
HASH->CR |= HASH_CR_INIT;
}
/**
* @brief Fills each HASH_InitStruct member with its default value.
* @param HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will
* be initialized.
* @note The default values set are : Processor mode is HASH, Algorithm selected is SHA1,
* Data type selected is 32b and HMAC Key Type is short key.
* @retval None
*/
void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct)
{
/* Initialize the HASH_AlgoSelection member */
HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
/* Initialize the HASH_AlgoMode member */
HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH;
/* Initialize the HASH_DataType member */
HASH_InitStruct->HASH_DataType = HASH_DataType_32b;
/* Initialize the HASH_HMACKeyType member */
HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
}
/**
* @brief Resets the HASH processor core, so that the HASH will be ready
* to compute the message digest of a new message.
* @note Calling this function will clear the HASH_SR_DCIS (Digest calculation
* completion interrupt status) bit corresponding to HASH_IT_DCI
* interrupt and HASH_FLAG_DCIS flag.
* @param None
* @retval None
*/
void HASH_Reset(void)
{
/* Reset the HASH processor core */
HASH->CR |= HASH_CR_INIT;
}
/**
* @}
*/
/** @defgroup HASH_Group2 Message Digest generation functions
* @brief Message Digest generation functions
*
@verbatim
===============================================================================
Message Digest generation functions
===============================================================================
This section provides functions allowing the generation of message digest:
- Push data in the IN FIFO : using HASH_DataIn()
- Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr()
- set the last word valid bits number using HASH_SetLastWordValidBitsNbr()
- start digest calculation : using HASH_StartDigest()
- Get the Digest message : using HASH_GetDigest()
@endverbatim
* @{
*/
/**
* @brief Configure the Number of valid bits in last word of the message
* @param ValidNumber: Number of valid bits in last word of the message.
* This parameter must be a number between 0 and 0x1F.
* - 0x00: All 32 bits of the last data written are valid
* - 0x01: Only bit [0] of the last data written is valid
* - 0x02: Only bits[1:0] of the last data written are valid
* - 0x03: Only bits[2:0] of the last data written are valid
* - ...
* - 0x1F: Only bits[30:0] of the last data written are valid
* @note The Number of valid bits must be set before to start the message
* digest competition (in Hash and HMAC) and key treatment(in HMAC).
* @retval None
*/
void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber)
{
/* Check the parameters */
assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber));
/* Configure the Number of valid bits in last word of the message */
HASH->STR &= ~(HASH_STR_NBW);
HASH->STR |= ValidNumber;
}
/**
* @brief Writes data in the Data Input FIFO
* @param Data: new data of the message to be processed.
* @retval None
*/
void HASH_DataIn(uint32_t Data)
{
/* Write in the DIN register a new data */
HASH->DIN = Data;
}
/**
* @brief Returns the number of words already pushed into the IN FIFO.
* @param None
* @retval The value of words already pushed into the IN FIFO.
*/
uint8_t HASH_GetInFIFOWordsNbr(void)
{
/* Return the value of NBW bits */
return ((HASH->CR & HASH_CR_NBW) >> 8);
}
/**
* @brief Provides the message digest result.
* @note In MD5 mode, Data[4] filed of HASH_MsgDigest structure is not used
* and is read as zero.
* @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will
* hold the message digest result
* @retval None
*/
void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest)
{
/* Get the data field */
HASH_MessageDigest->Data[0] = HASH->HR[0];
HASH_MessageDigest->Data[1] = HASH->HR[1];
HASH_MessageDigest->Data[2] = HASH->HR[2];
HASH_MessageDigest->Data[3] = HASH->HR[3];
HASH_MessageDigest->Data[4] = HASH->HR[4];
}
/**
* @brief Starts the message padding and calculation of the final message
* @param None
* @retval None
*/
void HASH_StartDigest(void)
{
/* Start the Digest calculation */
HASH->STR |= HASH_STR_DCAL;
}
/**
* @}
*/
/** @defgroup HASH_Group3 Context swapping functions
* @brief Context swapping functions
*
@verbatim
===============================================================================
Context swapping functions
===============================================================================
This section provides functions allowing to save and store HASH Context
It is possible to interrupt a HASH/HMAC process to perform another processing
with a higher priority, and to complete the interrupted process later on, when
the higher priority task is complete. To do so, the context of the interrupted
task must be saved from the HASH registers to memory, and then be restored
from memory to the HASH registers.
1. To save the current context, use HASH_SaveContext() function
2. To restore the saved context, use HASH_RestoreContext() function
@endverbatim
* @{
*/
/**
* @brief Save the Hash peripheral Context.
* @note The context can be saved only when no block is currently being
* processed. So user must wait for DINIS = 1 (the last block has been
* processed and the input FIFO is empty) or NBW != 0 (the FIFO is not
* full and no processing is ongoing).
* @param HASH_ContextSave: pointer to a HASH_Context structure that contains
* the repository for current context.
* @retval None
*/
void HASH_SaveContext(HASH_Context* HASH_ContextSave)
{
uint8_t i = 0;
/* save context registers */
HASH_ContextSave->HASH_IMR = HASH->IMR;
HASH_ContextSave->HASH_STR = HASH->STR;
HASH_ContextSave->HASH_CR = HASH->CR;
for(i=0; i<=50;i++)
{
HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i];
}
}
/**
* @brief Restore the Hash peripheral Context.
* @note After calling this function, user can restart the processing from the
* point where it has been interrupted.
* @param HASH_ContextRestore: pointer to a HASH_Context structure that contains
* the repository for saved context.
* @retval None
*/
void HASH_RestoreContext(HASH_Context* HASH_ContextRestore)
{
uint8_t i = 0;
/* restore context registers */
HASH->IMR = HASH_ContextRestore->HASH_IMR;
HASH->STR = HASH_ContextRestore->HASH_STR;
HASH->CR = HASH_ContextRestore->HASH_CR;
/* Initialize the hash processor */
HASH->CR |= HASH_CR_INIT;
/* continue restoring context registers */
for(i=0; i<=50;i++)
{
HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i];
}
}
/**
* @}
*/
/** @defgroup HASH_Group4 HASH's DMA interface Configuration function
* @brief HASH's DMA interface Configuration function
*
@verbatim
===============================================================================
HASH's DMA interface Configuration function
===============================================================================
This section provides functions allowing to configure the DMA interface for
HASH/ HMAC data input transfer.
When the DMA mode is enabled (using the HASH_DMACmd() function), data can be
sent to the IN FIFO using the DMA peripheral.
@endverbatim
* @{
*/
/**
* @brief Enables or disables the HASH DMA interface.
* @note The DMA is disabled by hardware after the end of transfer.
* @param NewState: new state of the selected HASH DMA transfer request.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void HASH_DMACmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the HASH DMA request */
HASH->CR |= HASH_CR_DMAE;
}
else
{
/* Disable the HASH DMA request */
HASH->CR &= ~HASH_CR_DMAE;
}
}
/**
* @}
*/
/** @defgroup HASH_Group5 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
Interrupts and flags management functions
===============================================================================
This section provides functions allowing to configure the HASH Interrupts and
to get the status and clear flags and Interrupts pending bits.
The HASH provides 2 Interrupts sources and 5 Flags:
Flags :
----------
1. HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO
which means that a new block (512 bit) can be entered
into the input buffer.
2. HASH_FLAG_DCIS : set when Digest calculation is complete
3. HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or
a transfer is ongoing.
This Flag is cleared only by hardware.
4. HASH_FLAG_BUSY : set when The hash core is processing a block of data
This Flag is cleared only by hardware.
5. HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that
the Data IN FIFO contains at least one word of data.
This Flag is cleared only by hardware.
Interrupts :
------------
1. HASH_IT_DINI : if enabled, this interrupt source is pending when 16
locations are free in the Data IN FIFO which means that
a new block (512 bit) can be entered into the input buffer.
This interrupt source is cleared using
HASH_ClearITPendingBit(HASH_IT_DINI) function.
2. HASH_IT_DCI : if enabled, this interrupt source is pending when Digest
calculation is complete.
This interrupt source is cleared using
HASH_ClearITPendingBit(HASH_IT_DCI) function.
Managing the HASH controller events :
------------------------------------
The user should identify which mode will be used in his application to manage
the HASH controller events: Polling mode or Interrupt mode.
1. In the Polling Mode it is advised to use the following functions:
- HASH_GetFlagStatus() : to check if flags events occur.
- HASH_ClearFlag() : to clear the flags events.
2. In the Interrupt Mode it is advised to use the following functions:
- HASH_ITConfig() : to enable or disable the interrupt source.
- HASH_GetITStatus() : to check if Interrupt occurs.
- HASH_ClearITPendingBit() : to clear the Interrupt pending Bit
(corresponding Flag).
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified HASH interrupts.
* @param HASH_IT: specifies the HASH interrupt source to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg HASH_IT_DINI: Data Input interrupt
* @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
* @param NewState: new state of the specified HASH interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_HASH_IT(HASH_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected HASH interrupt */
HASH->IMR |= HASH_IT;
}
else
{
/* Disable the selected HASH interrupt */
HASH->IMR &= (uint8_t) ~HASH_IT;
}
}
/**
* @brief Checks whether the specified HASH flag is set or not.
* @param HASH_FLAG: specifies the HASH flag to check.
* This parameter can be one of the following values:
* @arg HASH_FLAG_DINIS: Data input interrupt status flag
* @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag
* @arg HASH_FLAG_BUSY: Busy flag
* @arg HASH_FLAG_DMAS: DMAS Status flag
* @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag
* @retval The new state of HASH_FLAG (SET or RESET)
*/
FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t tempreg = 0;
/* Check the parameters */
assert_param(IS_HASH_GET_FLAG(HASH_FLAG));
/* check if the FLAG is in CR register */
if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint16_t)RESET )
{
tempreg = HASH->CR;
}
else /* The FLAG is in SR register */
{
tempreg = HASH->SR;
}
/* Check the status of the specified HASH flag */
if ((tempreg & HASH_FLAG) != (uint16_t)RESET)
{
/* HASH is set */
bitstatus = SET;
}
else
{
/* HASH_FLAG is reset */
bitstatus = RESET;
}
/* Return the HASH_FLAG status */
return bitstatus;
}
/**
* @brief Clears the HASH flags.
* @param HASH_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg HASH_FLAG_DINIS: Data Input Flag
* @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag
* @retval None
*/
void HASH_ClearFlag(uint16_t HASH_FLAG)
{
/* Check the parameters */
assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG));
/* Clear the selected HASH flags */
HASH->SR = ~(uint32_t)HASH_FLAG;
}
/**
* @brief Checks whether the specified HASH interrupt has occurred or not.
* @param HASH_IT: specifies the HASH interrupt source to check.
* This parameter can be one of the following values:
* @arg HASH_IT_DINI: Data Input interrupt
* @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
* @retval The new state of HASH_IT (SET or RESET).
*/
ITStatus HASH_GetITStatus(uint8_t HASH_IT)
{
ITStatus bitstatus = RESET;
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_HASH_GET_IT(HASH_IT));
/* Check the status of the specified HASH interrupt */
tmpreg = HASH->SR;
if (((HASH->IMR & tmpreg) & HASH_IT) != RESET)
{
/* HASH_IT is set */
bitstatus = SET;
}
else
{
/* HASH_IT is reset */
bitstatus = RESET;
}
/* Return the HASH_IT status */
return bitstatus;
}
/**
* @brief Clears the HASH interrupt pending bit(s).
* @param HASH_IT: specifies the HASH interrupt pending bit(s) to clear.
* This parameter can be any combination of the following values:
* @arg HASH_IT_DINI: Data Input interrupt
* @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
* @retval None
*/
void HASH_ClearITPendingBit(uint8_t HASH_IT)
{
/* Check the parameters */
assert_param(IS_HASH_IT(HASH_IT));
/* Clear the selected HASH interrupt pending bit */
HASH->SR = (uint8_t)~HASH_IT;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

314
source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_hash_md5.c Executable file
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/**
******************************************************************************
* @file stm32f4xx_hash_md5.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides high level functions to compute the HASH MD5 and
* HMAC MD5 Digest of an input message.
* It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
* peripheral.
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Enable The HASH controller clock using
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function.
*
* 2. Calculate the HASH MD5 Digest using HASH_MD5() function.
*
* 3. Calculate the HMAC MD5 Digest using HMAC_MD5() function.
*
* @endverbatim
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hash.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup HASH
* @brief HASH driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define MD5BUSY_TIMEOUT ((uint32_t) 0x00010000)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup HASH_Private_Functions
* @{
*/
/** @defgroup HASH_Group7 High Level MD5 functions
* @brief High Level MD5 Hash and HMAC functions
*
@verbatim
===============================================================================
High Level MD5 Hash and HMAC functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Compute the HASH MD5 digest.
* @param Input: pointer to the Input buffer to be treated.
* @param Ilen: length of the Input buffer.
* @param Output: the returned digest
* @retval An ErrorStatus enumeration value:
* - SUCCESS: digest computation done
* - ERROR: digest computation failed
*/
ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16])
{
HASH_InitTypeDef MD5_HASH_InitStructure;
HASH_MsgDigest MD5_MessageDigest;
__IO uint16_t nbvalidbitsdata = 0;
uint32_t i = 0;
__IO uint32_t counter = 0;
uint32_t busystatus = 0;
ErrorStatus status = SUCCESS;
uint32_t inputaddr = (uint32_t)Input;
uint32_t outputaddr = (uint32_t)Output;
/* Number of valid bits in last word of the Input data */
nbvalidbitsdata = 8 * (Ilen % 4);
/* HASH peripheral initialization */
HASH_DeInit();
/* HASH Configuration */
MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5;
MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;
MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
HASH_Init(&MD5_HASH_InitStructure);
/* Configure the number of valid bits in last word of the data */
HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
/* Write the Input block in the IN FIFO */
for(i=0; i<Ilen; i+=4)
{
HASH_DataIn(*(uint32_t*)inputaddr);
inputaddr+=4;
}
/* Start the HASH processor */
HASH_StartDigest();
/* wait until the Busy flag is RESET */
do
{
busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
counter++;
}while ((counter != MD5BUSY_TIMEOUT) && (busystatus != RESET));
if (busystatus != RESET)
{
status = ERROR;
}
else
{
/* Read the message digest */
HASH_GetDigest(&MD5_MessageDigest);
*(uint32_t*)(outputaddr) = __REV(MD5_MessageDigest.Data[0]);
outputaddr+=4;
*(uint32_t*)(outputaddr) = __REV(MD5_MessageDigest.Data[1]);
outputaddr+=4;
*(uint32_t*)(outputaddr) = __REV(MD5_MessageDigest.Data[2]);
outputaddr+=4;
*(uint32_t*)(outputaddr) = __REV(MD5_MessageDigest.Data[3]);
}
return status;
}
/**
* @brief Compute the HMAC MD5 digest.
* @param Key: pointer to the Key used for HMAC.
* @param Keylen: length of the Key used for HMAC.
* @param Input: pointer to the Input buffer to be treated.
* @param Ilen: length of the Input buffer.
* @param Output: the returned digest
* @retval An ErrorStatus enumeration value:
* - SUCCESS: digest computation done
* - ERROR: digest computation failed
*/
ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen, uint8_t *Input,
uint32_t Ilen, uint8_t Output[16])
{
HASH_InitTypeDef MD5_HASH_InitStructure;
HASH_MsgDigest MD5_MessageDigest;
__IO uint16_t nbvalidbitsdata = 0;
__IO uint16_t nbvalidbitskey = 0;
uint32_t i = 0;
__IO uint32_t counter = 0;
uint32_t busystatus = 0;
ErrorStatus status = SUCCESS;
uint32_t keyaddr = (uint32_t)Key;
uint32_t inputaddr = (uint32_t)Input;
uint32_t outputaddr = (uint32_t)Output;
/* Number of valid bits in last word of the Input data */
nbvalidbitsdata = 8 * (Ilen % 4);
/* Number of valid bits in last word of the Key */
nbvalidbitskey = 8 * (Keylen % 4);
/* HASH peripheral initialization */
HASH_DeInit();
/* HASH Configuration */
MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5;
MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HMAC;
MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
if(Keylen > 64)
{
/* HMAC long Key */
MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey;
}
else
{
/* HMAC short Key */
MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
}
HASH_Init(&MD5_HASH_InitStructure);
/* Configure the number of valid bits in last word of the Key */
HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
/* Write the Key */
for(i=0; i<Keylen; i+=4)
{
HASH_DataIn(*(uint32_t*)keyaddr);
keyaddr+=4;
}
/* Start the HASH processor */
HASH_StartDigest();
/* wait until the Busy flag is RESET */
do
{
busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
counter++;
}while ((counter != MD5BUSY_TIMEOUT) && (busystatus != RESET));
if (busystatus != RESET)
{
status = ERROR;
}
else
{
/* Configure the number of valid bits in last word of the Input data */
HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
/* Write the Input block in the IN FIFO */
for(i=0; i<Ilen; i+=4)
{
HASH_DataIn(*(uint32_t*)inputaddr);
inputaddr+=4;
}
/* Start the HASH processor */
HASH_StartDigest();
/* wait until the Busy flag is RESET */
counter =0;
do
{
busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
counter++;
}while ((counter != MD5BUSY_TIMEOUT) && (busystatus != RESET));
if (busystatus != RESET)
{
status = ERROR;
}
else
{
/* Configure the number of valid bits in last word of the Key */
HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
/* Write the Key */
keyaddr = (uint32_t)Key;
for(i=0; i<Keylen; i+=4)
{
HASH_DataIn(*(uint32_t*)keyaddr);
keyaddr+=4;
}
/* Start the HASH processor */
HASH_StartDigest();
/* wait until the Busy flag is RESET */
counter =0;
do
{
busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
counter++;
}while ((counter != MD5BUSY_TIMEOUT) && (busystatus != RESET));
if (busystatus != RESET)
{
status = ERROR;
}
else
{
/* Read the message digest */
HASH_GetDigest(&MD5_MessageDigest);
*(uint32_t*)(outputaddr) = __REV(MD5_MessageDigest.Data[0]);
outputaddr+=4;
*(uint32_t*)(outputaddr) = __REV(MD5_MessageDigest.Data[1]);
outputaddr+=4;
*(uint32_t*)(outputaddr) = __REV(MD5_MessageDigest.Data[2]);
outputaddr+=4;
*(uint32_t*)(outputaddr) = __REV(MD5_MessageDigest.Data[3]);
}
}
}
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

317
source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_hash_sha1.c Executable file
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/**
******************************************************************************
* @file stm32f4xx_hash_sha1.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides high level functions to compute the HASH SHA1 and
* HMAC SHA1 Digest of an input message.
* It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
* peripheral.
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Enable The HASH controller clock using
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function.
*
* 2. Calculate the HASH SHA1 Digest using HASH_SHA1() function.
*
* 3. Calculate the HMAC SHA1 Digest using HMAC_SHA1() function.
*
* @endverbatim
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hash.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup HASH
* @brief HASH driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define SHA1BUSY_TIMEOUT ((uint32_t) 0x00010000)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup HASH_Private_Functions
* @{
*/
/** @defgroup HASH_Group6 High Level SHA1 functions
* @brief High Level SHA1 Hash and HMAC functions
*
@verbatim
===============================================================================
High Level SHA1 Hash and HMAC functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Compute the HASH SHA1 digest.
* @param Input: pointer to the Input buffer to be treated.
* @param Ilen: length of the Input buffer.
* @param Output: the returned digest
* @retval An ErrorStatus enumeration value:
* - SUCCESS: digest computation done
* - ERROR: digest computation failed
*/
ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20])
{
HASH_InitTypeDef SHA1_HASH_InitStructure;
HASH_MsgDigest SHA1_MessageDigest;
__IO uint16_t nbvalidbitsdata = 0;
uint32_t i = 0;
__IO uint32_t counter = 0;
uint32_t busystatus = 0;
ErrorStatus status = SUCCESS;
uint32_t inputaddr = (uint32_t)Input;
uint32_t outputaddr = (uint32_t)Output;
/* Number of valid bits in last word of the Input data */
nbvalidbitsdata = 8 * (Ilen % 4);
/* HASH peripheral initialization */
HASH_DeInit();
/* HASH Configuration */
SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;
SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
HASH_Init(&SHA1_HASH_InitStructure);
/* Configure the number of valid bits in last word of the data */
HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
/* Write the Input block in the IN FIFO */
for(i=0; i<Ilen; i+=4)
{
HASH_DataIn(*(uint32_t*)inputaddr);
inputaddr+=4;
}
/* Start the HASH processor */
HASH_StartDigest();
/* wait until the Busy flag is RESET */
do
{
busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
counter++;
}while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
if (busystatus != RESET)
{
status = ERROR;
}
else
{
/* Read the message digest */
HASH_GetDigest(&SHA1_MessageDigest);
*(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[0]);
outputaddr+=4;
*(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[1]);
outputaddr+=4;
*(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[2]);
outputaddr+=4;
*(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[3]);
outputaddr+=4;
*(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[4]);
}
return status;
}
/**
* @brief Compute the HMAC SHA1 digest.
* @param Key: pointer to the Key used for HMAC.
* @param Keylen: length of the Key used for HMAC.
* @param Input: pointer to the Input buffer to be treated.
* @param Ilen: length of the Input buffer.
* @param Output: the returned digest
* @retval An ErrorStatus enumeration value:
* - SUCCESS: digest computation done
* - ERROR: digest computation failed
*/
ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen, uint8_t *Input,
uint32_t Ilen, uint8_t Output[20])
{
HASH_InitTypeDef SHA1_HASH_InitStructure;
HASH_MsgDigest SHA1_MessageDigest;
__IO uint16_t nbvalidbitsdata = 0;
__IO uint16_t nbvalidbitskey = 0;
uint32_t i = 0;
__IO uint32_t counter = 0;
uint32_t busystatus = 0;
ErrorStatus status = SUCCESS;
uint32_t keyaddr = (uint32_t)Key;
uint32_t inputaddr = (uint32_t)Input;
uint32_t outputaddr = (uint32_t)Output;
/* Number of valid bits in last word of the Input data */
nbvalidbitsdata = 8 * (Ilen % 4);
/* Number of valid bits in last word of the Key */
nbvalidbitskey = 8 * (Keylen % 4);
/* HASH peripheral initialization */
HASH_DeInit();
/* HASH Configuration */
SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HMAC;
SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
if(Keylen > 64)
{
/* HMAC long Key */
SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey;
}
else
{
/* HMAC short Key */
SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
}
HASH_Init(&SHA1_HASH_InitStructure);
/* Configure the number of valid bits in last word of the Key */
HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
/* Write the Key */
for(i=0; i<Keylen; i+=4)
{
HASH_DataIn(*(uint32_t*)keyaddr);
keyaddr+=4;
}
/* Start the HASH processor */
HASH_StartDigest();
/* wait until the Busy flag is RESET */
do
{
busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
counter++;
}while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
if (busystatus != RESET)
{
status = ERROR;
}
else
{
/* Configure the number of valid bits in last word of the Input data */
HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
/* Write the Input block in the IN FIFO */
for(i=0; i<Ilen; i+=4)
{
HASH_DataIn(*(uint32_t*)inputaddr);
inputaddr+=4;
}
/* Start the HASH processor */
HASH_StartDigest();
/* wait until the Busy flag is RESET */
counter =0;
do
{
busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
counter++;
}while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
if (busystatus != RESET)
{
status = ERROR;
}
else
{
/* Configure the number of valid bits in last word of the Key */
HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
/* Write the Key */
keyaddr = (uint32_t)Key;
for(i=0; i<Keylen; i+=4)
{
HASH_DataIn(*(uint32_t*)keyaddr);
keyaddr+=4;
}
/* Start the HASH processor */
HASH_StartDigest();
/* wait until the Busy flag is RESET */
counter =0;
do
{
busystatus = HASH_GetFlagStatus(HASH_FLAG_BUSY);
counter++;
}while ((counter != SHA1BUSY_TIMEOUT) && (busystatus != RESET));
if (busystatus != RESET)
{
status = ERROR;
}
else
{
/* Read the message digest */
HASH_GetDigest(&SHA1_MessageDigest);
*(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[0]);
outputaddr+=4;
*(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[1]);
outputaddr+=4;
*(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[2]);
outputaddr+=4;
*(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[3]);
outputaddr+=4;
*(uint32_t*)(outputaddr) = __REV(SHA1_MessageDigest.Data[4]);
}
}
}
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_i2c.c Executable file
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263
source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_iwdg.c Executable file
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/**
******************************************************************************
* @file stm32f4xx_iwdg.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Independent watchdog (IWDG) peripheral:
* - Prescaler and Counter configuration
* - IWDG activation
* - Flag management
*
* @verbatim
*
* ===================================================================
* IWDG features
* ===================================================================
*
* The IWDG can be started by either software or hardware (configurable
* through option byte).
*
* The IWDG is clocked by its own dedicated low-speed clock (LSI) and
* thus stays active even if the main clock fails.
* Once the IWDG is started, the LSI is forced ON and cannot be disabled
* (LSI cannot be disabled too), and the counter starts counting down from
* the reset value of 0xFFF. When it reaches the end of count value (0x000)
* a system reset is generated.
* The IWDG counter should be reloaded at regular intervals to prevent
* an MCU reset.
*
* The IWDG is implemented in the VDD voltage domain that is still functional
* in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
*
* IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
* reset occurs.
*
* Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
* The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
* devices provide the capability to measure the LSI frequency (LSI clock
* connected internally to TIM5 CH4 input capture). The measured value
* can be used to have an IWDG timeout with an acceptable accuracy.
* For more information, please refer to the STM32F4xx Reference manual
*
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Enable write access to IWDG_PR and IWDG_RLR registers using
* IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function
*
* 2. Configure the IWDG prescaler using IWDG_SetPrescaler() function
*
* 3. Configure the IWDG counter value using IWDG_SetReload() function.
* This value will be loaded in the IWDG counter each time the counter
* is reloaded, then the IWDG will start counting down from this value.
*
* 4. Start the IWDG using IWDG_Enable() function, when the IWDG is used
* in software mode (no need to enable the LSI, it will be enabled
* by hardware)
*
* 5. Then the application program must reload the IWDG counter at regular
* intervals during normal operation to prevent an MCU reset, using
* IWDG_ReloadCounter() function.
*
* @endverbatim
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_iwdg.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup IWDG
* @brief IWDG driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* KR register bit mask */
#define KR_KEY_RELOAD ((uint16_t)0xAAAA)
#define KR_KEY_ENABLE ((uint16_t)0xCCCC)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup IWDG_Private_Functions
* @{
*/
/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
* @brief Prescaler and Counter configuration functions
*
@verbatim
===============================================================================
Prescaler and Counter configuration functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
* @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
* This parameter can be one of the following values:
* @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
* @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
* @retval None
*/
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
{
/* Check the parameters */
assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
IWDG->KR = IWDG_WriteAccess;
}
/**
* @brief Sets IWDG Prescaler value.
* @param IWDG_Prescaler: specifies the IWDG Prescaler value.
* This parameter can be one of the following values:
* @arg IWDG_Prescaler_4: IWDG prescaler set to 4
* @arg IWDG_Prescaler_8: IWDG prescaler set to 8
* @arg IWDG_Prescaler_16: IWDG prescaler set to 16
* @arg IWDG_Prescaler_32: IWDG prescaler set to 32
* @arg IWDG_Prescaler_64: IWDG prescaler set to 64
* @arg IWDG_Prescaler_128: IWDG prescaler set to 128
* @arg IWDG_Prescaler_256: IWDG prescaler set to 256
* @retval None
*/
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
{
/* Check the parameters */
assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
IWDG->PR = IWDG_Prescaler;
}
/**
* @brief Sets IWDG Reload value.
* @param Reload: specifies the IWDG Reload value.
* This parameter must be a number between 0 and 0x0FFF.
* @retval None
*/
void IWDG_SetReload(uint16_t Reload)
{
/* Check the parameters */
assert_param(IS_IWDG_RELOAD(Reload));
IWDG->RLR = Reload;
}
/**
* @brief Reloads IWDG counter with value defined in the reload register
* (write access to IWDG_PR and IWDG_RLR registers disabled).
* @param None
* @retval None
*/
void IWDG_ReloadCounter(void)
{
IWDG->KR = KR_KEY_RELOAD;
}
/**
* @}
*/
/** @defgroup IWDG_Group2 IWDG activation function
* @brief IWDG activation function
*
@verbatim
===============================================================================
IWDG activation function
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
* @param None
* @retval None
*/
void IWDG_Enable(void)
{
IWDG->KR = KR_KEY_ENABLE;
}
/**
* @}
*/
/** @defgroup IWDG_Group3 Flag management function
* @brief Flag management function
*
@verbatim
===============================================================================
Flag management function
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Checks whether the specified IWDG flag is set or not.
* @param IWDG_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg IWDG_FLAG_PVU: Prescaler Value Update on going
* @arg IWDG_FLAG_RVU: Reload Value Update on going
* @retval The new state of IWDG_FLAG (SET or RESET).
*/
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_IWDG_FLAG(IWDG_FLAG));
if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_pwr.c Executable file
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/**
******************************************************************************
* @file stm32f4xx_pwr.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
* - Backup Domain Access
* - PVD configuration
* - WakeUp pin configuration
* - Main and Backup Regulators configuration
* - FLASH Power Down configuration
* - Low Power modes configuration
* - Flags management
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_pwr.h"
#include "stm32f4xx_rcc.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup PWR
* @brief PWR driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* --------- PWR registers bit address in the alias region ---------- */
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
/* --- CR Register ---*/
/* Alias word address of DBP bit */
#define CR_OFFSET (PWR_OFFSET + 0x00)
#define DBP_BitNumber 0x08
#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
/* Alias word address of PVDE bit */
#define PVDE_BitNumber 0x04
#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
/* Alias word address of FPDS bit */
#define FPDS_BitNumber 0x09
#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
/* Alias word address of PMODE bit */
#define PMODE_BitNumber 0x0E
#define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
/* --- CSR Register ---*/
/* Alias word address of EWUP bit */
#define CSR_OFFSET (PWR_OFFSET + 0x04)
#define EWUP_BitNumber 0x08
#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
/* Alias word address of BRE bit */
#define BRE_BitNumber 0x09
#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
/* ------------------ PWR registers bit mask ------------------------ */
/* CR register bit mask */
#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup PWR_Private_Functions
* @{
*/
/** @defgroup PWR_Group1 Backup Domain Access function
* @brief Backup Domain Access function
*
@verbatim
===============================================================================
Backup Domain Access function
===============================================================================
After reset, the backup domain (RTC registers, RTC backup data
registers and backup SRAM) is protected against possible unwanted
write accesses.
To enable access to the RTC Domain and RTC registers, proceed as follows:
- Enable the Power Controller (PWR) APB1 interface clock using the
RCC_APB1PeriphClockCmd() function.
- Enable access to RTC domain using the PWR_BackupAccessCmd() function.
@endverbatim
* @{
*/
/**
* @brief Deinitializes the PWR peripheral registers to their default reset values.
* @param None
* @retval None
*/
void PWR_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
}
/**
* @brief Enables or disables access to the backup domain (RTC registers, RTC
* backup data registers and backup SRAM).
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @param NewState: new state of the access to the backup domain.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_BackupAccessCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
}
/**
* @}
*/
/** @defgroup PWR_Group2 PVD configuration functions
* @brief PVD configuration functions
*
@verbatim
===============================================================================
PVD configuration functions
===============================================================================
- The PVD is used to monitor the VDD power supply by comparing it to a threshold
selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
- A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the
PVD threshold. This event is internally connected to the EXTI line16
and can generate an interrupt if enabled through the EXTI registers.
- The PVD is stopped in Standby mode.
@endverbatim
* @{
*/
/**
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
* @param PWR_PVDLevel: specifies the PVD detection level
* This parameter can be one of the following values:
* @arg PWR_PVDLevel_0: PVD detection level set to 2.0V
* @arg PWR_PVDLevel_1: PVD detection level set to 2.2V
* @arg PWR_PVDLevel_2: PVD detection level set to 2.3V
* @arg PWR_PVDLevel_3: PVD detection level set to 2.5V
* @arg PWR_PVDLevel_4: PVD detection level set to 2.7V
* @arg PWR_PVDLevel_5: PVD detection level set to 2.8V
* @arg PWR_PVDLevel_6: PVD detection level set to 2.9V
* @arg PWR_PVDLevel_7: PVD detection level set to 3.0V
* @note Refer to the electrical characteristics of you device datasheet for more details.
* @retval None
*/
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
tmpreg = PWR->CR;
/* Clear PLS[7:5] bits */
tmpreg &= CR_PLS_MASK;
/* Set PLS[7:5] bits according to PWR_PVDLevel value */
tmpreg |= PWR_PVDLevel;
/* Store the new value */
PWR->CR = tmpreg;
}
/**
* @brief Enables or disables the Power Voltage Detector(PVD).
* @param NewState: new state of the PVD.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_PVDCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
}
/**
* @}
*/
/** @defgroup PWR_Group3 WakeUp pin configuration functions
* @brief WakeUp pin configuration functions
*
@verbatim
===============================================================================
WakeUp pin configuration functions
===============================================================================
- WakeUp pin is used to wakeup the system from Standby mode. This pin is
forced in input pull down configuration and is active on rising edges.
- There is only one WakeUp pin: WakeUp Pin 1 on PA.00.
@endverbatim
* @{
*/
/**
* @brief Enables or disables the WakeUp Pin functionality.
* @param NewState: new state of the WakeUp Pin functionality.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_WakeUpPinCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
}
/**
* @}
*/
/** @defgroup PWR_Group4 Main and Backup Regulators configuration functions
* @brief Main and Backup Regulators configuration functions
*
@verbatim
===============================================================================
Main and Backup Regulators configuration functions
===============================================================================
- The backup domain includes 4 Kbytes of backup SRAM accessible only from the
CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained
even in Standby or VBAT mode when the low power backup regulator is enabled.
It can be considered as an internal EEPROM when VBAT is always present.
You can use the PWR_BackupRegulatorCmd() function to enable the low power
backup regulator and use the PWR_GetFlagStatus(PWR_FLAG_BRR) to check if it is
ready or not.
- When the backup domain is supplied by VDD (analog switch connected to VDD)
the backup SRAM is powered from VDD which replaces the VBAT power supply to
save battery life.
- The backup SRAM is not mass erased by an tamper event. It is read protected
to prevent confidential data, such as cryptographic private key, from being
accessed. The backup SRAM can be erased only through the Flash interface when
a protection level change from level 1 to level 0 is requested.
Refer to the description of Read protection (RDP) in the Flash programming manual.
- The main internal regulator can be configured to have a tradeoff between performance
and power consumption when the device does not operate at the maximum frequency.
This is done through PWR_MainRegulatorModeConfig() function which configure VOS bit
in PWR_CR register:
- When this bit is set (Regulator voltage output Scale 1 mode selected) the System
frequency can go up to 168 MHz.
- When this bit is reset (Regulator voltage output Scale 2 mode selected) the System
frequency can go up to 144 MHz.
Refer to the datasheets for more details.
@endverbatim
* @{
*/
/**
* @brief Enables or disables the Backup Regulator.
* @param NewState: new state of the Backup Regulator.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_BackupRegulatorCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;
}
/**
* @brief Configures the main internal regulator output voltage.
* @param PWR_Regulator_Voltage: specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption when the device does
* not operate at the maximum frequency (refer to the datasheets for more details).
* This parameter can be one of the following values:
* @arg PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode,
* System frequency up to 168 MHz.
* @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode,
* System frequency up to 144 MHz.
* @retval None
*/
void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
{
/* Check the parameters */
assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage));
if (PWR_Regulator_Voltage == PWR_Regulator_Voltage_Scale2)
{
PWR->CR &= ~PWR_Regulator_Voltage_Scale1;
}
else
{
PWR->CR |= PWR_Regulator_Voltage_Scale1;
}
}
/**
* @}
*/
/** @defgroup PWR_Group5 FLASH Power Down configuration functions
* @brief FLASH Power Down configuration functions
*
@verbatim
===============================================================================
FLASH Power Down configuration functions
===============================================================================
- By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd()
function, the Flash memory also enters power down mode when the device enters
Stop mode. When the Flash memory is in power down mode, an additional startup
delay is incurred when waking up from Stop mode.
@endverbatim
* @{
*/
/**
* @brief Enables or disables the Flash Power Down in STOP mode.
* @param NewState: new state of the Flash power mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_FlashPowerDownCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState;
}
/**
* @}
*/
/** @defgroup PWR_Group6 Low Power modes configuration functions
* @brief Low Power modes configuration functions
*
@verbatim
===============================================================================
Low Power modes configuration functions
===============================================================================
The devices feature 3 low-power modes:
- Sleep mode: Cortex-M4 core stopped, peripherals kept running.
- Stop mode: all clocks are stopped, regulator running, regulator in low power mode
- Standby mode: 1.2V domain powered off.
Sleep mode
===========
- Entry:
- The Sleep mode is entered by using the __WFI() or __WFE() functions.
- Exit:
- Any peripheral interrupt acknowledged by the nested vectored interrupt
controller (NVIC) can wake up the device from Sleep mode.
Stop mode
==========
In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
and the HSE RC oscillators are disabled. Internal SRAM and register contents
are preserved.
The voltage regulator can be configured either in normal or low-power mode.
To minimize the consumption In Stop mode, FLASH can be powered off before
entering the Stop mode. It can be switched on again by software after exiting
the Stop mode using the PWR_FlashPowerDownCmd() function.
- Entry:
- The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,)
function with regulator in LowPower or with Regulator ON.
- Exit:
- Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
Standby mode
============
The Standby mode allows to achieve the lowest power consumption. It is based
on the Cortex-M4 deepsleep mode, with the voltage regulator disabled.
The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
the HSE oscillator are also switched off. SRAM and register contents are lost
except for the RTC registers, RTC backup registers, backup SRAM and Standby
circuitry.
The voltage regulator is OFF.
- Entry:
- The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
- Exit:
- WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
Auto-wakeup (AWU) from low-power mode
=====================================
The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
Wakeup event, a tamper event, a time-stamp event, or a comparator event,
without depending on an external interrupt (Auto-wakeup mode).
- RTC auto-wakeup (AWU) from the Stop mode
----------------------------------------
- To wake up from the Stop mode with an RTC alarm event, it is necessary to:
- Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
or Event modes) using the EXTI_Init() function.
- Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
- Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
and RTC_AlarmCmd() functions.
- To wake up from the Stop mode with an RTC Tamper or time stamp event, it
is necessary to:
- Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt
or Event modes) using the EXTI_Init() function.
- Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
function
- Configure the RTC to detect the tamper or time stamp event using the
RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
functions.
- To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
- Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt
or Event modes) using the EXTI_Init() function.
- Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
- Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
- RTC auto-wakeup (AWU) from the Standby mode
-------------------------------------------
- To wake up from the Standby mode with an RTC alarm event, it is necessary to:
- Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
- Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
and RTC_AlarmCmd() functions.
- To wake up from the Standby mode with an RTC Tamper or time stamp event, it
is necessary to:
- Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
function
- Configure the RTC to detect the tamper or time stamp event using the
RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
functions.
- To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
- Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
- Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
@endverbatim
* @{
*/
/**
* @brief Enters STOP mode.
*
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
* the HSI RC oscillator is selected as system clock.
* @note When the voltage regulator operates in low power mode, an additional
* startup delay is incurred when waking up from Stop mode.
* By keeping the internal regulator ON during Stop mode, the consumption
* is higher although the startup time is reduced.
*
* @param PWR_Regulator: specifies the regulator state in STOP mode.
* This parameter can be one of the following values:
* @arg PWR_Regulator_ON: STOP mode with regulator ON
* @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
* @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
* @retval None
*/
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(PWR_Regulator));
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
/* Select the regulator state in STOP mode ---------------------------------*/
tmpreg = PWR->CR;
/* Clear PDDS and LPDSR bits */
tmpreg &= CR_DS_MASK;
/* Set LPDSR bit according to PWR_Regulator value */
tmpreg |= PWR_Regulator;
/* Store the new value */
PWR->CR = tmpreg;
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* Select STOP mode entry --------------------------------------------------*/
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__WFE();
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
}
/**
* @brief Enters STANDBY mode.
* @note In Standby mode, all I/O pins are high impedance except for:
* - Reset pad (still available)
* - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
* Alarm out, or RTC clock calibration out.
* - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
* - WKUP pin 1 (PA0) if enabled.
* @param None
* @retval None
*/
void PWR_EnterSTANDBYMode(void)
{
/* Clear Wakeup flag */
PWR->CR |= PWR_CR_CWUF;
/* Select STANDBY mode */
PWR->CR |= PWR_CR_PDDS;
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM )
__force_stores();
#endif
/* Request Wait For Interrupt */
__WFI();
}
/**
* @}
*/
/** @defgroup PWR_Group7 Flags management functions
* @brief Flags management functions
*
@verbatim
===============================================================================
Flags management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Checks whether the specified PWR flag is set or not.
* @param PWR_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
* was received from the WKUP pin or from the RTC alarm (Alarm A
* or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
* An additional wakeup event is detected if the WKUP pin is enabled
* (by setting the EWUP bit) when the WKUP pin level is already high.
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
* resumed from StandBy mode.
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
* by the PWR_PVDCmd() function. The PVD is stopped by Standby mode
* For this reason, this bit is equal to 0 after Standby or reset
* until the PVDE bit is set.
* @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
* when the device wakes up from Standby mode or by a system reset
* or power reset.
* @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
* scaling output selection is ready.
* @retval The new state of PWR_FLAG (SET or RESET).
*/
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/**
* @brief Clears the PWR's pending flags.
* @param PWR_FLAG: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag
* @arg PWR_FLAG_SB: StandBy flag
* @retval None
*/
void PWR_ClearFlag(uint32_t PWR_FLAG)
{
/* Check the parameters */
assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
PWR->CR |= PWR_FLAG << 2;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_rcc.c Executable file
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source/firmware/arch/stm32f4xx/lib/stdperiph/src/stm32f4xx_rng.c Executable file
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/**
******************************************************************************
* @file stm32f4xx_rng.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
* - Initialization and Configuration
* - Get 32 bit Random number
* - Interrupts and flags management
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Enable The RNG controller clock using
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function.
*
* 2. Activate the RNG peripheral using RNG_Cmd() function.
*
* 3. Wait until the 32 bit Random number Generator contains a valid
* random data (using polling/interrupt mode). For more details,
* refer to "Interrupts and flags management functions" module
* description.
*
* 4. Get the 32 bit Random number using RNG_GetRandomNumber() function
*
* 5. To get another 32 bit Random number, go to step 3.
*
*
*
* @endverbatim
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_rng.h"
#include "stm32f4xx_rcc.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup RNG
* @brief RNG driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup RNG_Private_Functions
* @{
*/
/** @defgroup RNG_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
Initialization and Configuration functions
===============================================================================
This section provides functions allowing to
- Initialize the RNG peripheral
- Enable or disable the RNG peripheral
@endverbatim
* @{
*/
/**
* @brief Deinitializes the RNG peripheral registers to their default reset values.
* @param None
* @retval None
*/
void RNG_DeInit(void)
{
/* Enable RNG reset state */
RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE);
/* Release RNG from reset state */
RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE);
}
/**
* @brief Enables or disables the RNG peripheral.
* @param NewState: new state of the RNG peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void RNG_Cmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the RNG */
RNG->CR |= RNG_CR_RNGEN;
}
else
{
/* Disable the RNG */
RNG->CR &= ~RNG_CR_RNGEN;
}
}
/**
* @}
*/
/** @defgroup RNG_Group2 Get 32 bit Random number function
* @brief Get 32 bit Random number function
*
@verbatim
===============================================================================
Get 32 bit Random number function
===============================================================================
This section provides a function allowing to get the 32 bit Random number
@note Before to call this function you have to wait till DRDY flag is set,
using RNG_GetFlagStatus(RNG_FLAG_DRDY) function.
@endverbatim
* @{
*/
/**
* @brief Returns a 32-bit random number.
*
* @note Before to call this function you have to wait till DRDY (data ready)
* flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function.
* @note Each time the the Random number data is read (using RNG_GetRandomNumber()
* function), the RNG_FLAG_DRDY flag is automatically cleared.
* @note In the case of a seed error, the generation of random numbers is
* interrupted for as long as the SECS bit is '1'. If a number is
* available in the RNG_DR register, it must not be used because it may
* not have enough entropy. In this case, it is recommended to clear the
* SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable
* and enable the RNG peripheral (using RNG_Cmd() function) to
* reinitialize and restart the RNG.
* @note In the case of a clock error, the RNG is no more able to generate
* random numbers because the PLL48CLK clock is not correct. User have
* to check that the clock controller is correctly configured to provide
* the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS)
* function) . The clock error has no impact on the previously generated
* random numbers, and the RNG_DR register contents can be used.
*
* @param None
* @retval 32-bit random number.
*/
uint32_t RNG_GetRandomNumber(void)
{
/* Return the 32 bit random number from the DR register */
return RNG->DR;
}
/**
* @}
*/
/** @defgroup RNG_Group3 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
Interrupts and flags management functions
===============================================================================
This section provides functions allowing to configure the RNG Interrupts and
to get the status and clear flags and Interrupts pending bits.
The RNG provides 3 Interrupts sources and 3 Flags:
Flags :
----------
1. RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid
random data. it is cleared by reading the valid data
(using RNG_GetRandomNumber() function).
2. RNG_FLAG_CECS : In the case of a seed error detection.
3. RNG_FLAG_SECS : In the case of a clock error detection.
Interrupts :
------------
if enabled, an RNG interrupt is pending :
1. In the case of the RNG_DR register contains valid random data.
This interrupt source is cleared once the RNG_DR register has been read
(using RNG_GetRandomNumber() function) until a new valid value is
computed.
or
2. In the case of a seed error : One of the following faulty sequences has
been detected:
- More than 64 consecutive bits at the same value (0 or 1)
- More than 32 consecutive alternance of 0 and 1 (0101010101...01)
This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI)
function.
or
3. In the case of a clock error : the PLL48CLK (RNG peripheral clock source)
was not correctly detected (fPLL48CLK< fHCLK/16).
This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_CEI)
function.
@note In this case, User have to check that the clock controller is
correctly configured to provide the RNG clock.
Managing the RNG controller events :
------------------------------------
The user should identify which mode will be used in his application to manage
the RNG controller events: Polling mode or Interrupt mode.
1. In the Polling Mode it is advised to use the following functions:
- RNG_GetFlagStatus() : to check if flags events occur.
- RNG_ClearFlag() : to clear the flags events.
@note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only
by reading the Random number data.
2. In the Interrupt Mode it is advised to use the following functions:
- RNG_ITConfig() : to enable or disable the interrupt source.
- RNG_GetITStatus() : to check if Interrupt occurs.
- RNG_ClearITPendingBit() : to clear the Interrupt pending Bit
(corresponding Flag).
@endverbatim
* @{
*/
/**
* @brief Enables or disables the RNG interrupt.
* @note The RNG provides 3 interrupt sources,
* - Computed data is ready event (DRDY), and
* - Seed error Interrupt (SEI) and
* - Clock error Interrupt (CEI),
* all these interrupts sources are enabled by setting the IE bit in
* CR register. However, each interrupt have its specific status bit
* (see RNG_GetITStatus() function) and clear bit except the DRDY event
* (see RNG_ClearITPendingBit() function).
* @param NewState: new state of the RNG interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void RNG_ITConfig(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the RNG interrupt */
RNG->CR |= RNG_CR_IE;
}
else
{
/* Disable the RNG interrupt */
RNG->CR &= ~RNG_CR_IE;
}
}
/**
* @brief Checks whether the specified RNG flag is set or not.
* @param RNG_FLAG: specifies the RNG flag to check.
* This parameter can be one of the following values:
* @arg RNG_FLAG_DRDY: Data Ready flag.
* @arg RNG_FLAG_CECS: Clock Error Current flag.
* @arg RNG_FLAG_SECS: Seed Error Current flag.
* @retval The new state of RNG_FLAG (SET or RESET).
*/
FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_RNG_GET_FLAG(RNG_FLAG));
/* Check the status of the specified RNG flag */
if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET)
{
/* RNG_FLAG is set */
bitstatus = SET;
}
else
{
/* RNG_FLAG is reset */
bitstatus = RESET;
}
/* Return the RNG_FLAG status */
return bitstatus;
}
/**
* @brief Clears the RNG flags.
* @param RNG_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg RNG_FLAG_CECS: Clock Error Current flag.
* @arg RNG_FLAG_SECS: Seed Error Current flag.
* @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function.
* This flag is cleared only by reading the Random number data (using
* RNG_GetRandomNumber() function).
* @retval None
*/
void RNG_ClearFlag(uint8_t RNG_FLAG)
{
/* Check the parameters */
assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG));
/* Clear the selected RNG flags */
RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4);
}
/**
* @brief Checks whether the specified RNG interrupt has occurred or not.
* @param RNG_IT: specifies the RNG interrupt source to check.
* This parameter can be one of the following values:
* @arg RNG_IT_CEI: Clock Error Interrupt.
* @arg RNG_IT_SEI: Seed Error Interrupt.
* @retval The new state of RNG_IT (SET or RESET).
*/
ITStatus RNG_GetITStatus(uint8_t RNG_IT)
{
ITStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_RNG_GET_IT(RNG_IT));
/* Check the status of the specified RNG interrupt */
if ((RNG->SR & RNG_IT) != (uint8_t)RESET)
{
/* RNG_IT is set */
bitstatus = SET;
}
else
{
/* RNG_IT is reset */
bitstatus = RESET;
}
/* Return the RNG_IT status */
return bitstatus;
}
/**
* @brief Clears the RNG interrupt pending bit(s).
* @param RNG_IT: specifies the RNG interrupt pending bit(s) to clear.
* This parameter can be any combination of the following values:
* @arg RNG_IT_CEI: Clock Error Interrupt.
* @arg RNG_IT_SEI: Seed Error Interrupt.
* @retval None
*/
void RNG_ClearITPendingBit(uint8_t RNG_IT)
{
/* Check the parameters */
assert_param(IS_RNG_IT(RNG_IT));
/* Clear the selected RNG interrupt pending bit */
RNG->SR = (uint8_t)~RNG_IT;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f4xx_syscfg.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the SYSCFG peripheral.
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
*
* This driver provides functions for:
*
* 1. Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()
*
* 2. Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig()
*
* 3. Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig()
*
* @note SYSCFG APB clock must be enabled to get write access to SYSCFG registers,
* using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
*
* @endverbatim
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_syscfg.h"
#include "stm32f4xx_rcc.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup SYSCFG
* @brief SYSCFG driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ------------ RCC registers bit address in the alias region ----------- */
#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
/* --- PMC Register ---*/
/* Alias word address of MII_RMII_SEL bit */
#define PMC_OFFSET (SYSCFG_OFFSET + 0x04)
#define MII_RMII_SEL_BitNumber ((uint8_t)0x17)
#define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
/* --- CMPCR Register ---*/
/* Alias word address of CMP_PD bit */
#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20)
#define CMP_PD_BitNumber ((uint8_t)0x00)
#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4))
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SYSCFG_Private_Functions
* @{
*/
/**
* @brief Deinitializes the Alternate Functions (remap and EXTI configuration)
* registers to their default reset values.
* @param None
* @retval None
*/
void SYSCFG_DeInit(void)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);
}
/**
* @brief Changes the mapping of the specified pin.
* @param SYSCFG_Memory: selects the memory remapping.
* This parameter can be one of the following values:
* @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000
* @retval None
*/
void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
{
/* Check the parameters */
assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));
SYSCFG->MEMRMP = SYSCFG_MemoryRemap;
}
/**
* @brief Selects the GPIO pin used as EXTI Line.
* @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for
* EXTI lines where x can be (A..I).
* @param EXTI_PinSourcex: specifies the EXTI line to be configured.
* This parameter can be EXTI_PinSourcex where x can be (0..15, except
* for EXTI_PortSourceGPIOI x can be (0..11).
* @retval None
*/
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
{
uint32_t tmp = 0x00;
/* Check the parameters */
assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
}
/**
* @brief Selects the ETHERNET media interface
* @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode.
* This parameter can be one of the following values:
* @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected
* @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected
* @retval None
*/
void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface)
{
assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface));
/* Configure MII_RMII selection bit */
*(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface;
}
/**
* @brief Enables or disables the I/O Compensation Cell.
* @note The I/O compensation cell can be used only when the device supply
* voltage ranges from 2.4 to 3.6 V.
* @param NewState: new state of the I/O Compensation Cell.
* This parameter can be one of the following values:
* @arg ENABLE: I/O compensation cell enabled
* @arg DISABLE: I/O compensation cell power-down mode
* @retval None
*/
void SYSCFG_CompensationCellCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState;
}
/**
* @brief Checks whether the I/O Compensation Cell ready flag is set or not.
* @param None
* @retval The new state of the I/O Compensation Cell ready flag (SET or RESET)
*/
FlagStatus SYSCFG_GetCompensationCellStatus(void)
{
FlagStatus bitstatus = RESET;
if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f4xx_wwdg.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Window watchdog (WWDG) peripheral:
* - Prescaler, Refresh window and Counter configuration
* - WWDG activation
* - Interrupts and flags management
*
* @verbatim
*
* ===================================================================
* WWDG features
* ===================================================================
*
* Once enabled the WWDG generates a system reset on expiry of a programmed
* time period, unless the program refreshes the counter (downcounter)
* before to reach 0x3F value (i.e. a reset is generated when the counter
* value rolls over from 0x40 to 0x3F).
* An MCU reset is also generated if the counter value is refreshed
* before the counter has reached the refresh window value. This
* implies that the counter must be refreshed in a limited window.
*
* Once enabled the WWDG cannot be disabled except by a system reset.
*
* WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
* reset occurs.
*
* The WWDG counter input clock is derived from the APB clock divided
* by a programmable prescaler.
*
* WWDG counter clock = PCLK1 / Prescaler
* WWDG timeout = (WWDG counter clock) * (counter value)
*
* Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function
*
* 2. Configure the WWDG prescaler using WWDG_SetPrescaler() function
*
* 3. Configure the WWDG refresh window using WWDG_SetWindowValue() function
*
* 4. Set the WWDG counter value and start it using WWDG_Enable() function.
* When the WWDG is enabled the counter value should be configured to
* a value greater than 0x40 to prevent generating an immediate reset.
*
* 5. Optionally you can enable the Early wakeup interrupt which is
* generated when the counter reach 0x40.
* Once enabled this interrupt cannot be disabled except by a system reset.
*
* 6. Then the application program must refresh the WWDG counter at regular
* intervals during normal operation to prevent an MCU reset, using
* WWDG_SetCounter() function. This operation must occur only when
* the counter value is lower than the refresh window value,
* programmed using WWDG_SetWindowValue().
*
* @endverbatim
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_wwdg.h"
#include "stm32f4xx_rcc.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup WWDG
* @brief WWDG driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ----------- WWDG registers bit address in the alias region ----------- */
#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
/* Alias word address of EWI bit */
#define CFR_OFFSET (WWDG_OFFSET + 0x04)
#define EWI_BitNumber 0x09
#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
/* --------------------- WWDG registers bit mask ------------------------ */
/* CFR register bit mask */
#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)
#define CFR_W_MASK ((uint32_t)0xFFFFFF80)
#define BIT_MASK ((uint8_t)0x7F)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup WWDG_Private_Functions
* @{
*/
/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
* @brief Prescaler, Refresh window and Counter configuration functions
*
@verbatim
===============================================================================
Prescaler, Refresh window and Counter configuration functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the WWDG peripheral registers to their default reset values.
* @param None
* @retval None
*/
void WWDG_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
}
/**
* @brief Sets the WWDG Prescaler.
* @param WWDG_Prescaler: specifies the WWDG Prescaler.
* This parameter can be one of the following values:
* @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
* @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
* @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
* @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
* @retval None
*/
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
/* Clear WDGTB[1:0] bits */
tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
/* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
tmpreg |= WWDG_Prescaler;
/* Store the new value */
WWDG->CFR = tmpreg;
}
/**
* @brief Sets the WWDG window value.
* @param WindowValue: specifies the window value to be compared to the downcounter.
* This parameter value must be lower than 0x80.
* @retval None
*/
void WWDG_SetWindowValue(uint8_t WindowValue)
{
__IO uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
/* Clear W[6:0] bits */
tmpreg = WWDG->CFR & CFR_W_MASK;
/* Set W[6:0] bits according to WindowValue value */
tmpreg |= WindowValue & (uint32_t) BIT_MASK;
/* Store the new value */
WWDG->CFR = tmpreg;
}
/**
* @brief Enables the WWDG Early Wakeup interrupt(EWI).
* @note Once enabled this interrupt cannot be disabled except by a system reset.
* @param None
* @retval None
*/
void WWDG_EnableIT(void)
{
*(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
}
/**
* @brief Sets the WWDG counter value.
* @param Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F (to prevent generating
* an immediate reset)
* @retval None
*/
void WWDG_SetCounter(uint8_t Counter)
{
/* Check the parameters */
assert_param(IS_WWDG_COUNTER(Counter));
/* Write to T[6:0] bits to configure the counter value, no need to do
a read-modify-write; writing a 0 to WDGA bit does nothing */
WWDG->CR = Counter & BIT_MASK;
}
/**
* @}
*/
/** @defgroup WWDG_Group2 WWDG activation functions
* @brief WWDG activation functions
*
@verbatim
===============================================================================
WWDG activation function
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables WWDG and load the counter value.
* @param Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F (to prevent generating
* an immediate reset)
* @retval None
*/
void WWDG_Enable(uint8_t Counter)
{
/* Check the parameters */
assert_param(IS_WWDG_COUNTER(Counter));
WWDG->CR = WWDG_CR_WDGA | Counter;
}
/**
* @}
*/
/** @defgroup WWDG_Group3 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
Interrupts and flags management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Checks whether the Early Wakeup interrupt flag is set or not.
* @param None
* @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
*/
FlagStatus WWDG_GetFlagStatus(void)
{
FlagStatus bitstatus = RESET;
if ((WWDG->SR) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears Early Wakeup interrupt flag.
* @param None
* @retval None
*/
void WWDG_ClearFlag(void)
{
WWDG->SR = (uint32_t)RESET;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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source/firmware/arch/stm32f4xx/lib/stdperiph/src/system_stm32f4xx.c Executable file
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/**
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V1.0.0
* @date 19-September-2011
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F4xx devices,
* and is generated by the clock configuration tool
* stm32f4xx_Clock_Configuration_V1.0.0.xls
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* and Divider factors, AHB/APBx prescalers and Flash settings),
* depending on the configuration made in the clock xls tool.
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (16 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. If the system clock source selected by user fails to startup, the SystemInit()
* function will do nothing and HSI still used as system clock source. User can
* add some code to deal with this issue inside the SetSysClock() function.
*
* 4. The default value of HSE crystal is set to 8 MHz, refer to "HSE_VALUE" define
* in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
* through PLL, and you are using different crystal you have to adapt the HSE
* value to your own configuration.
*
* 5. This file configures the system clock as follows:
*=============================================================================
*=============================================================================
* Supported STM32F4xx device revision | Rev A
*-----------------------------------------------------------------------------
* System Clock source | PLL (HSE)
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 168000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 168000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 4
*-----------------------------------------------------------------------------
* APB2 Prescaler | 2
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 8000000
*-----------------------------------------------------------------------------
* PLL_M | 8
*-----------------------------------------------------------------------------
* PLL_N | 336
*-----------------------------------------------------------------------------
* PLL_P | 2
*-----------------------------------------------------------------------------
* PLL_Q | 7
*-----------------------------------------------------------------------------
* PLLI2S_N | NA
*-----------------------------------------------------------------------------
* PLLI2S_R | NA
*-----------------------------------------------------------------------------
* I2S input clock | NA
*-----------------------------------------------------------------------------
* VDD(V) | 3.3
*-----------------------------------------------------------------------------
* High Performance mode | Enabled
*-----------------------------------------------------------------------------
* Flash Latency(WS) | 5
*-----------------------------------------------------------------------------
* Prefetch Buffer | OFF
*-----------------------------------------------------------------------------
* Instruction cache | ON
*-----------------------------------------------------------------------------
* Data cache | ON
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Enabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f4xx_system
* @{
*/
/** @addtogroup STM32F4xx_System_Private_Includes
* @{
*/
#include "stm32f4xx.h"
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Defines
* @{
*/
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM324xG_EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
#define PLL_M 8
#define PLL_N 336
/* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 2
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 7
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Variables
* @{
*/
uint32_t SystemCoreClock = 168000000;
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
* @{
*/
static void SetSysClock(void);
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings ----------------------------------*/
SetSysClock();
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings
* @Note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
static void SetSysClock(void)
{
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable high performance mode, System frequency up to 168 MHz */
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_PMODE;
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
/* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
/* Enable the main PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till the main PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
/* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= RCC_CFGR_SW_PLL;
/* Wait till the main PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
/**
* @brief Setup the external memory controller. Called in startup_stm32f4xx.s
* before jump to __main
* @param None
* @retval None
*/
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
* This function configures the external SRAM mounted on STM324xG_EVAL board
* This SRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
/*-- GPIOs Configuration -----------------------------------------------------*/
/*
+-------------------+--------------------+------------------+------------------+
+ SRAM pins assignment +
+-------------------+--------------------+------------------+------------------+
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
| PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
| PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
| PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
| PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
| PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
| PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+
| PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 |
| PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 |
| PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+
| PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 |
| | PE15 <-> FSMC_D12 |
+-------------------+--------------------+
*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR = 0x00000078;
/* Connect PDx pins to FSMC Alternate function */
GPIOD->AFR[0] = 0x00cc00cc;
GPIOD->AFR[1] = 0xcc0ccccc;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xaaaa0a0a;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xffff0f0f;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FSMC Alternate function */
GPIOE->AFR[0] = 0xc00cc0cc;
GPIOE->AFR[1] = 0xcccccccc;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xaaaa828a;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xffffc3cf;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FSMC Alternate function */
GPIOF->AFR[0] = 0x00cccccc;
GPIOF->AFR[1] = 0xcccc0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xaa000aaa;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xff000fff;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FSMC Alternate function */
GPIOG->AFR[0] = 0x00cccccc;
GPIOG->AFR[1] = 0x000000c0;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00080aaa;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000c0fff;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/*-- FSMC Configuration ------------------------------------------------------*/
/* Enable the FSMC interface clock */
RCC->AHB3ENR = 0x00000001;
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001015;
FSMC_Bank1->BTCR[3] = 0x00010603;//0x00010400;
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
/*
Bank1_SRAM2 is configured as follow:
p.FSMC_AddressSetupTime = 3;//0;
p.FSMC_AddressHoldTime = 0;
p.FSMC_DataSetupTime = 6;//4;
p.FSMC_BusTurnAroundDuration = 1;
p.FSMC_CLKDivision = 0;
p.FSMC_DataLatency = 0;
p.FSMC_AccessMode = FSMC_AccessMode_A;
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
*/
}
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/