1005 lines
39 KiB
C
Executable File
1005 lines
39 KiB
C
Executable File
/**
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******************************************************************************
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* @file stm32f4xx_sdio.c
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* @author MCD Application Team
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* @version V1.0.0
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* @date 30-September-2011
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* @brief This file provides firmware functions to manage the following
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* functionalities of the Secure digital input/output interface (SDIO)
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* peripheral:
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* - Initialization and Configuration
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* - Command path state machine (CPSM) management
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* - Data path state machine (DPSM) management
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* - SDIO IO Cards mode management
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* - CE-ATA mode management
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* - DMA transfers management
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* - Interrupts and flags management
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*
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* @verbatim
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*
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*
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* ===================================================================
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* How to use this driver
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* ===================================================================
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* 1. The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output
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* of PLL (PLL48CLK). Before to start working with SDIO peripheral
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* make sure that the PLL is well configured.
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* The SDIO peripheral uses two clock signals:
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* - SDIO adapter clock (SDIOCLK = 48 MHz)
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* - APB2 bus clock (PCLK2)
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* PCLK2 and SDIO_CK clock frequencies must respect the following condition:
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* Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))
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*
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* 2. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE).
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*
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* 3. According to the SDIO mode, enable the GPIO clocks using
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* RCC_AHB1PeriphClockCmd() function.
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* The I/O can be one of the following configurations:
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* - 1-bit data length: SDIO_CMD, SDIO_CK and D0.
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* - 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0].
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* - 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0].
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*
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* 4. Peripheral's alternate function:
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* - Connect the pin to the desired peripherals' Alternate
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* Function (AF) using GPIO_PinAFConfig() function
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* - Configure the desired pin in alternate function by:
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* GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
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* - Select the type, pull-up/pull-down and output speed via
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* GPIO_PuPd, GPIO_OType and GPIO_Speed members
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* - Call GPIO_Init() function
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*
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* 5. Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide,
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* hardware, flow control and the Clock Divider using the SDIO_Init()
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* function.
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*
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* 6. Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON)
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* function.
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*
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* 7. Enable the clock using the SDIO_ClockCmd() function.
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*
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* 8. Enable the NVIC and the corresponding interrupt using the function
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* SDIO_ITConfig() if you need to use interrupt mode.
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*
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* 9. When using the DMA mode
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* - Configure the DMA using DMA_Init() function
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* - Active the needed channel Request using SDIO_DMACmd() function
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*
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* 10. Enable the DMA using the DMA_Cmd() function, when using DMA mode.
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*
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* 11. To control the CPSM (Command Path State Machine) and send
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* commands to the card use the SDIO_SendCommand(),
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* SDIO_GetCommandResponse() and SDIO_GetResponse() functions.
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* First, user has to fill the command structure (pointer to
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* SDIO_CmdInitTypeDef) according to the selected command to be sent.
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* The parameters that should be filled are:
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* - Command Argument
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* - Command Index
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* - Command Response type
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* - Command Wait
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* - CPSM Status (Enable or Disable)
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*
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* To check if the command is well received, read the SDIO_CMDRESP
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* register using the SDIO_GetCommandResponse().
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* The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
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* SDIO_GetResponse() function.
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*
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* 12. To control the DPSM (Data Path State Machine) and send/receive
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* data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
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* SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions.
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*
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* Read Operations
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* ---------------
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* a) First, user has to fill the data structure (pointer to
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* SDIO_DataInitTypeDef) according to the selected data type to
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* be received.
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* The parameters that should be filled are:
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* - Data TimeOut
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* - Data Length
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* - Data Block size
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* - Data Transfer direction: should be from card (To SDIO)
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* - Data Transfer mode
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* - DPSM Status (Enable or Disable)
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*
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* b) Configure the SDIO resources to receive the data from the card
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* according to selected transfer mode (Refer to Step 8, 9 and 10).
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*
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* c) Send the selected Read command (refer to step 11).
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*
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* d) Use the SDIO flags/interrupts to check the transfer status.
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*
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* Write Operations
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* ---------------
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* a) First, user has to fill the data structure (pointer to
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* SDIO_DataInitTypeDef) according to the selected data type to
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* be received.
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* The parameters that should be filled are:
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* - Data TimeOut
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* - Data Length
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* - Data Block size
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* - Data Transfer direction: should be to card (To CARD)
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* - Data Transfer mode
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* - DPSM Status (Enable or Disable)
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*
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* b) Configure the SDIO resources to send the data to the card
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* according to selected transfer mode (Refer to Step 8, 9 and 10).
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*
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* c) Send the selected Write command (refer to step 11).
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*
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* d) Use the SDIO flags/interrupts to check the transfer status.
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*
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*
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* @endverbatim
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*
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*
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******************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_sdio.h"
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#include "stm32f4xx_rcc.h"
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/** @addtogroup STM32F4xx_StdPeriph_Driver
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* @{
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*/
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/** @defgroup SDIO
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* @brief SDIO driver modules
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* ------------ SDIO registers bit address in the alias region ----------- */
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#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
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/* --- CLKCR Register ---*/
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/* Alias word address of CLKEN bit */
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#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
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#define CLKEN_BitNumber 0x08
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#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
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/* --- CMD Register ---*/
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/* Alias word address of SDIOSUSPEND bit */
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#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
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#define SDIOSUSPEND_BitNumber 0x0B
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#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
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/* Alias word address of ENCMDCOMPL bit */
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#define ENCMDCOMPL_BitNumber 0x0C
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#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
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/* Alias word address of NIEN bit */
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#define NIEN_BitNumber 0x0D
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#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
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/* Alias word address of ATACMD bit */
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#define ATACMD_BitNumber 0x0E
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#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
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/* --- DCTRL Register ---*/
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/* Alias word address of DMAEN bit */
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#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
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#define DMAEN_BitNumber 0x03
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#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
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/* Alias word address of RWSTART bit */
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#define RWSTART_BitNumber 0x08
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#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
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/* Alias word address of RWSTOP bit */
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#define RWSTOP_BitNumber 0x09
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#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
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/* Alias word address of RWMOD bit */
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#define RWMOD_BitNumber 0x0A
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#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
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/* Alias word address of SDIOEN bit */
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#define SDIOEN_BitNumber 0x0B
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#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
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/* ---------------------- SDIO registers bit mask ------------------------ */
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/* --- CLKCR Register ---*/
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/* CLKCR register clear mask */
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#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
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/* --- PWRCTRL Register ---*/
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/* SDIO PWRCTRL Mask */
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#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
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/* --- DCTRL Register ---*/
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/* SDIO DCTRL Clear Mask */
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#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
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/* --- CMD Register ---*/
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/* CMD Register clear mask */
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#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
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/* SDIO RESP Registers Address */
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#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup SDIO_Private_Functions
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* @{
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*/
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/** @defgroup SDIO_Group1 Initialization and Configuration functions
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* @brief Initialization and Configuration functions
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*
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@verbatim
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===============================================================================
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Initialization and Configuration functions
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===============================================================================
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@endverbatim
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* @{
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*/
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/**
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* @brief Deinitializes the SDIO peripheral registers to their default reset values.
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* @param None
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* @retval None
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*/
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void SDIO_DeInit(void)
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{
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE);
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE);
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}
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/**
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* @brief Initializes the SDIO peripheral according to the specified
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* parameters in the SDIO_InitStruct.
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* @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
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* that contains the configuration information for the SDIO peripheral.
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* @retval None
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*/
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void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
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{
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uint32_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
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assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
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assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
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assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
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assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
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/*---------------------------- SDIO CLKCR Configuration ------------------------*/
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/* Get the SDIO CLKCR value */
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tmpreg = SDIO->CLKCR;
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/* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
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tmpreg &= CLKCR_CLEAR_MASK;
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/* Set CLKDIV bits according to SDIO_ClockDiv value */
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/* Set PWRSAV bit according to SDIO_ClockPowerSave value */
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/* Set BYPASS bit according to SDIO_ClockBypass value */
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/* Set WIDBUS bits according to SDIO_BusWide value */
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/* Set NEGEDGE bits according to SDIO_ClockEdge value */
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/* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
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tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
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SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
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SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
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/* Write to SDIO CLKCR */
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SDIO->CLKCR = tmpreg;
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}
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/**
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* @brief Fills each SDIO_InitStruct member with its default value.
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* @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
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* will be initialized.
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* @retval None
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*/
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void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
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{
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/* SDIO_InitStruct members default value */
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SDIO_InitStruct->SDIO_ClockDiv = 0x00;
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SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
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SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
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SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
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SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
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SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
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}
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/**
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* @brief Enables or disables the SDIO Clock.
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* @param NewState: new state of the SDIO Clock.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void SDIO_ClockCmd(FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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*(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
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}
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/**
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* @brief Sets the power status of the controller.
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* @param SDIO_PowerState: new state of the Power state.
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* This parameter can be one of the following values:
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* @arg SDIO_PowerState_OFF: SDIO Power OFF
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* @arg SDIO_PowerState_ON: SDIO Power ON
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* @retval None
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*/
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void SDIO_SetPowerState(uint32_t SDIO_PowerState)
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{
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/* Check the parameters */
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assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
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SDIO->POWER = SDIO_PowerState;
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}
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/**
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* @brief Gets the power status of the controller.
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* @param None
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* @retval Power status of the controller. The returned value can be one of the
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* following values:
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* - 0x00: Power OFF
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* - 0x02: Power UP
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* - 0x03: Power ON
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*/
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uint32_t SDIO_GetPowerState(void)
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{
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return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
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}
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/**
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* @}
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*/
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/** @defgroup SDIO_Group2 Command path state machine (CPSM) management functions
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* @brief Command path state machine (CPSM) management functions
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*
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@verbatim
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===============================================================================
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Command path state machine (CPSM) management functions
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===============================================================================
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This section provide functions allowing to program and read the Command path
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state machine (CPSM).
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@endverbatim
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* @{
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*/
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/**
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* @brief Initializes the SDIO Command according to the specified
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* parameters in the SDIO_CmdInitStruct and send the command.
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* @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
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* structure that contains the configuration information for the SDIO
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* command.
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* @retval None
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*/
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void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
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{
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uint32_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
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assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
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assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
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assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
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/*---------------------------- SDIO ARG Configuration ------------------------*/
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/* Set the SDIO Argument value */
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SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
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/*---------------------------- SDIO CMD Configuration ------------------------*/
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/* Get the SDIO CMD value */
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tmpreg = SDIO->CMD;
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/* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
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tmpreg &= CMD_CLEAR_MASK;
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/* Set CMDINDEX bits according to SDIO_CmdIndex value */
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/* Set WAITRESP bits according to SDIO_Response value */
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/* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
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/* Set CPSMEN bits according to SDIO_CPSM value */
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tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
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| SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
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/* Write to SDIO CMD */
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SDIO->CMD = tmpreg;
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}
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/**
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* @brief Fills each SDIO_CmdInitStruct member with its default value.
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* @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
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* structure which will be initialized.
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* @retval None
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*/
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void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
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{
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/* SDIO_CmdInitStruct members default value */
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SDIO_CmdInitStruct->SDIO_Argument = 0x00;
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SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
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SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
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SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
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SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
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}
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/**
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* @brief Returns command index of last command for which response received.
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* @param None
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* @retval Returns the command index of the last command response received.
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*/
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uint8_t SDIO_GetCommandResponse(void)
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{
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return (uint8_t)(SDIO->RESPCMD);
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}
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/**
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* @brief Returns response received from the card for the last command.
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* @param SDIO_RESP: Specifies the SDIO response register.
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* This parameter can be one of the following values:
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* @arg SDIO_RESP1: Response Register 1
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* @arg SDIO_RESP2: Response Register 2
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* @arg SDIO_RESP3: Response Register 3
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* @arg SDIO_RESP4: Response Register 4
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* @retval The Corresponding response register value.
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*/
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uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
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{
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__IO uint32_t tmp = 0;
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/* Check the parameters */
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assert_param(IS_SDIO_RESP(SDIO_RESP));
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tmp = SDIO_RESP_ADDR + SDIO_RESP;
|
|
|
|
return (*(__IO uint32_t *) tmp);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup SDIO_Group3 Data path state machine (DPSM) management functions
|
|
* @brief Data path state machine (DPSM) management functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
Data path state machine (DPSM) management functions
|
|
===============================================================================
|
|
|
|
This section provide functions allowing to program and read the Data path
|
|
state machine (DPSM).
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Initializes the SDIO data path according to the specified
|
|
* parameters in the SDIO_DataInitStruct.
|
|
* @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure
|
|
* that contains the configuration information for the SDIO command.
|
|
* @retval None
|
|
*/
|
|
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
|
|
{
|
|
uint32_t tmpreg = 0;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
|
|
assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
|
|
assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
|
|
assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
|
|
assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
|
|
|
|
/*---------------------------- SDIO DTIMER Configuration ---------------------*/
|
|
/* Set the SDIO Data TimeOut value */
|
|
SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
|
|
|
|
/*---------------------------- SDIO DLEN Configuration -----------------------*/
|
|
/* Set the SDIO DataLength value */
|
|
SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
|
|
|
|
/*---------------------------- SDIO DCTRL Configuration ----------------------*/
|
|
/* Get the SDIO DCTRL value */
|
|
tmpreg = SDIO->DCTRL;
|
|
/* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
|
|
tmpreg &= DCTRL_CLEAR_MASK;
|
|
/* Set DEN bit according to SDIO_DPSM value */
|
|
/* Set DTMODE bit according to SDIO_TransferMode value */
|
|
/* Set DTDIR bit according to SDIO_TransferDir value */
|
|
/* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
|
|
tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
|
|
| SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
|
|
|
|
/* Write to SDIO DCTRL */
|
|
SDIO->DCTRL = tmpreg;
|
|
}
|
|
|
|
/**
|
|
* @brief Fills each SDIO_DataInitStruct member with its default value.
|
|
* @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure
|
|
* which will be initialized.
|
|
* @retval None
|
|
*/
|
|
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
|
|
{
|
|
/* SDIO_DataInitStruct members default value */
|
|
SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
|
|
SDIO_DataInitStruct->SDIO_DataLength = 0x00;
|
|
SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
|
|
SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
|
|
SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
|
|
SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns number of remaining data bytes to be transferred.
|
|
* @param None
|
|
* @retval Number of remaining data bytes to be transferred
|
|
*/
|
|
uint32_t SDIO_GetDataCounter(void)
|
|
{
|
|
return SDIO->DCOUNT;
|
|
}
|
|
|
|
/**
|
|
* @brief Read one data word from Rx FIFO.
|
|
* @param None
|
|
* @retval Data received
|
|
*/
|
|
uint32_t SDIO_ReadData(void)
|
|
{
|
|
return SDIO->FIFO;
|
|
}
|
|
|
|
/**
|
|
* @brief Write one data word to Tx FIFO.
|
|
* @param Data: 32-bit data word to write.
|
|
* @retval None
|
|
*/
|
|
void SDIO_WriteData(uint32_t Data)
|
|
{
|
|
SDIO->FIFO = Data;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the number of words left to be written to or read from FIFO.
|
|
* @param None
|
|
* @retval Remaining number of words.
|
|
*/
|
|
uint32_t SDIO_GetFIFOCount(void)
|
|
{
|
|
return SDIO->FIFOCNT;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup SDIO_Group4 SDIO IO Cards mode management functions
|
|
* @brief SDIO IO Cards mode management functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
SDIO IO Cards mode management functions
|
|
===============================================================================
|
|
|
|
This section provide functions allowing to program and read the SDIO IO Cards.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Starts the SD I/O Read Wait operation.
|
|
* @param NewState: new state of the Start SDIO Read Wait operation.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void SDIO_StartSDIOReadWait(FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
*(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
|
|
}
|
|
|
|
/**
|
|
* @brief Stops the SD I/O Read Wait operation.
|
|
* @param NewState: new state of the Stop SDIO Read Wait operation.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void SDIO_StopSDIOReadWait(FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
*(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
|
|
}
|
|
|
|
/**
|
|
* @brief Sets one of the two options of inserting read wait interval.
|
|
* @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
|
|
* This parameter can be:
|
|
* @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
|
|
* @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
|
|
* @retval None
|
|
*/
|
|
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
|
|
|
|
*(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the SD I/O Mode Operation.
|
|
* @param NewState: new state of SDIO specific operation.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void SDIO_SetSDIOOperation(FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
*(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the SD I/O Mode suspend command sending.
|
|
* @param NewState: new state of the SD I/O Mode suspend command.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup SDIO_Group5 CE-ATA mode management functions
|
|
* @brief CE-ATA mode management functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
CE-ATA mode management functions
|
|
===============================================================================
|
|
|
|
This section provide functions allowing to program and read the CE-ATA card.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enables or disables the command completion signal.
|
|
* @param NewState: new state of command completion signal.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void SDIO_CommandCompletionCmd(FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the CE-ATA interrupt.
|
|
* @param NewState: new state of CE-ATA interrupt.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void SDIO_CEATAITCmd(FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
|
|
}
|
|
|
|
/**
|
|
* @brief Sends CE-ATA command (CMD61).
|
|
* @param NewState: new state of CE-ATA command.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void SDIO_SendCEATACmd(FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
*(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup SDIO_Group6 DMA transfers management functions
|
|
* @brief DMA transfers management functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
DMA transfers management functions
|
|
===============================================================================
|
|
|
|
This section provide functions allowing to program SDIO DMA transfer.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enables or disables the SDIO DMA request.
|
|
* @param NewState: new state of the selected SDIO DMA request.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void SDIO_DMACmd(FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
*(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup SDIO_Group7 Interrupts and flags management functions
|
|
* @brief Interrupts and flags management functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
Interrupts and flags management functions
|
|
===============================================================================
|
|
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enables or disables the SDIO interrupts.
|
|
* @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
|
|
* This parameter can be one or a combination of the following values:
|
|
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
|
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
|
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
|
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
|
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
|
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
|
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
|
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
|
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
|
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
|
* bus mode interrupt
|
|
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
|
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
|
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
|
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
|
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
|
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
|
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
|
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
|
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
|
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
|
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
|
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
|
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
|
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
|
|
* @param NewState: new state of the specified SDIO interrupts.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_SDIO_IT(SDIO_IT));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
if (NewState != DISABLE)
|
|
{
|
|
/* Enable the SDIO interrupts */
|
|
SDIO->MASK |= SDIO_IT;
|
|
}
|
|
else
|
|
{
|
|
/* Disable the SDIO interrupts */
|
|
SDIO->MASK &= ~SDIO_IT;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Checks whether the specified SDIO flag is set or not.
|
|
* @param SDIO_FLAG: specifies the flag to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
|
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
|
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
|
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
|
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
|
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
|
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
|
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
|
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
|
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
|
|
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
|
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
|
|
* @arg SDIO_FLAG_TXACT: Data transmit in progress
|
|
* @arg SDIO_FLAG_RXACT: Data receive in progress
|
|
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
|
|
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
|
|
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
|
|
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
|
|
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
|
|
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
|
|
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
|
|
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
|
|
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
|
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
|
|
* @retval The new state of SDIO_FLAG (SET or RESET).
|
|
*/
|
|
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
|
|
{
|
|
FlagStatus bitstatus = RESET;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_SDIO_FLAG(SDIO_FLAG));
|
|
|
|
if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
|
|
{
|
|
bitstatus = SET;
|
|
}
|
|
else
|
|
{
|
|
bitstatus = RESET;
|
|
}
|
|
return bitstatus;
|
|
}
|
|
|
|
/**
|
|
* @brief Clears the SDIO's pending flags.
|
|
* @param SDIO_FLAG: specifies the flag to clear.
|
|
* This parameter can be one or a combination of the following values:
|
|
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
|
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
|
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
|
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
|
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
|
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
|
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
|
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
|
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
|
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
|
|
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
|
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
|
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
|
|
* @retval None
|
|
*/
|
|
void SDIO_ClearFlag(uint32_t SDIO_FLAG)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
|
|
|
|
SDIO->ICR = SDIO_FLAG;
|
|
}
|
|
|
|
/**
|
|
* @brief Checks whether the specified SDIO interrupt has occurred or not.
|
|
* @param SDIO_IT: specifies the SDIO interrupt source to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
|
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
|
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
|
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
|
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
|
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
|
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
|
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
|
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
|
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
|
* bus mode interrupt
|
|
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
|
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
|
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
|
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
|
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
|
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
|
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
|
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
|
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
|
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
|
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
|
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
|
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
|
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
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* @retval The new state of SDIO_IT (SET or RESET).
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*/
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|
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
|
|
{
|
|
ITStatus bitstatus = RESET;
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|
|
|
/* Check the parameters */
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|
assert_param(IS_SDIO_GET_IT(SDIO_IT));
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|
if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
|
|
{
|
|
bitstatus = SET;
|
|
}
|
|
else
|
|
{
|
|
bitstatus = RESET;
|
|
}
|
|
return bitstatus;
|
|
}
|
|
|
|
/**
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|
* @brief Clears the SDIO's interrupt pending bits.
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|
* @param SDIO_IT: specifies the interrupt pending bit to clear.
|
|
* This parameter can be one or a combination of the following values:
|
|
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
|
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
|
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
|
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
|
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
|
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
|
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
|
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
|
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
|
|
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
|
* bus mode interrupt
|
|
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
|
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
|
|
* @retval None
|
|
*/
|
|
void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
|
|
|
|
SDIO->ICR = SDIO_IT;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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