335 lines
14 KiB
C
Executable File
335 lines
14 KiB
C
Executable File
/**
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******************************************************************************
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* @file stm32f4xx_flash.h
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* @author MCD Application Team
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* @version V1.0.0
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* @date 30-September-2011
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* @brief This file contains all the functions prototypes for the FLASH
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* firmware library.
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******************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F4xx_FLASH_H
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#define __STM32F4xx_FLASH_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx.h"
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/** @addtogroup STM32F4xx_StdPeriph_Driver
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* @{
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*/
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/** @addtogroup FLASH
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/**
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* @brief FLASH Status
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*/
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typedef enum
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{
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FLASH_BUSY = 1,
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FLASH_ERROR_PGS,
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FLASH_ERROR_PGP,
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FLASH_ERROR_PGA,
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FLASH_ERROR_WRP,
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FLASH_ERROR_PROGRAM,
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FLASH_ERROR_OPERATION,
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FLASH_COMPLETE
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}FLASH_Status;
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup FLASH_Exported_Constants
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* @{
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*/
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/** @defgroup Flash_Latency
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* @{
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*/
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#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
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#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */
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#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */
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#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */
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#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */
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#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */
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#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */
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#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */
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#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
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((LATENCY) == FLASH_Latency_1) || \
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((LATENCY) == FLASH_Latency_2) || \
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((LATENCY) == FLASH_Latency_3) || \
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((LATENCY) == FLASH_Latency_4) || \
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((LATENCY) == FLASH_Latency_5) || \
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((LATENCY) == FLASH_Latency_6) || \
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((LATENCY) == FLASH_Latency_7))
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/**
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* @}
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*/
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/** @defgroup FLASH_Voltage_Range
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* @{
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*/
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#define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */
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#define VoltageRange_2 ((uint8_t)0x01) /*!<Device operating range: 2.1V to 2.7V */
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#define VoltageRange_3 ((uint8_t)0x02) /*!<Device operating range: 2.7V to 3.6V */
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#define VoltageRange_4 ((uint8_t)0x03) /*!<Device operating range: 2.7V to 3.6V + External Vpp */
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#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VoltageRange_1) || \
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((RANGE) == VoltageRange_2) || \
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((RANGE) == VoltageRange_3) || \
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((RANGE) == VoltageRange_4))
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/**
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* @}
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*/
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/** @defgroup FLASH_Sectors
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* @{
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*/
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#define FLASH_Sector_0 ((uint16_t)0x0000) /*!< Sector Number 0 */
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#define FLASH_Sector_1 ((uint16_t)0x0008) /*!< Sector Number 1 */
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#define FLASH_Sector_2 ((uint16_t)0x0010) /*!< Sector Number 2 */
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#define FLASH_Sector_3 ((uint16_t)0x0018) /*!< Sector Number 3 */
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#define FLASH_Sector_4 ((uint16_t)0x0020) /*!< Sector Number 4 */
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#define FLASH_Sector_5 ((uint16_t)0x0028) /*!< Sector Number 5 */
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#define FLASH_Sector_6 ((uint16_t)0x0030) /*!< Sector Number 6 */
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#define FLASH_Sector_7 ((uint16_t)0x0038) /*!< Sector Number 7 */
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#define FLASH_Sector_8 ((uint16_t)0x0040) /*!< Sector Number 8 */
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#define FLASH_Sector_9 ((uint16_t)0x0048) /*!< Sector Number 9 */
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#define FLASH_Sector_10 ((uint16_t)0x0050) /*!< Sector Number 10 */
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#define FLASH_Sector_11 ((uint16_t)0x0058) /*!< Sector Number 11 */
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#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0) || ((SECTOR) == FLASH_Sector_1) ||\
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((SECTOR) == FLASH_Sector_2) || ((SECTOR) == FLASH_Sector_3) ||\
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((SECTOR) == FLASH_Sector_4) || ((SECTOR) == FLASH_Sector_5) ||\
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((SECTOR) == FLASH_Sector_6) || ((SECTOR) == FLASH_Sector_7) ||\
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((SECTOR) == FLASH_Sector_8) || ((SECTOR) == FLASH_Sector_9) ||\
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((SECTOR) == FLASH_Sector_10) || ((SECTOR) == FLASH_Sector_11))
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#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\
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(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
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/**
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* @}
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*/
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/** @defgroup Option_Bytes_Write_Protection
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* @{
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*/
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#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
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#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
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#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
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#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
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#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
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#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
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#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
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#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
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#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
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#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
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#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
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#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
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#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
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#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
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/**
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* @}
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*/
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/** @defgroup FLASH_Option_Bytes_Read_Protection
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* @{
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*/
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#define OB_RDP_Level_0 ((uint8_t)0xAA)
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#define OB_RDP_Level_1 ((uint8_t)0x55)
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/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2
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it's no more possible to go back to level 1 or 0 */
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#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
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((LEVEL) == OB_RDP_Level_1))/*||\
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((LEVEL) == OB_RDP_Level_2))*/
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/**
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* @}
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*/
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/** @defgroup FLASH_Option_Bytes_IWatchdog
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* @{
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*/
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#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */
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#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
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#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
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/**
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* @}
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*/
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/** @defgroup FLASH_Option_Bytes_nRST_STOP
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* @{
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*/
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#define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
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#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
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#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
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/**
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* @}
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*/
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/** @defgroup FLASH_Option_Bytes_nRST_STDBY
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* @{
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*/
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#define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
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#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
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#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
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/**
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* @}
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*/
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/** @defgroup FLASH_BOR_Reset_Level
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* @{
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*/
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#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */
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#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */
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#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */
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#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */
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#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
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((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
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/**
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* @}
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*/
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/** @defgroup FLASH_Interrupts
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* @{
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*/
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#define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */
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#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */
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#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000))
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/**
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* @}
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*/
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/** @defgroup FLASH_Flags
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* @{
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*/
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#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */
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#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */
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#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
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#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */
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#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */
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#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */
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#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */
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#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF0C) == 0x00000000) && ((FLAG) != 0x00000000))
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#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \
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((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \
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((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \
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((FLAG) == FLASH_FLAG_BSY))
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/**
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* @}
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*/
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/** @defgroup FLASH_Program_Parallelism
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* @{
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*/
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#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000)
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#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100)
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#define FLASH_PSIZE_WORD ((uint32_t)0x00000200)
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#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300)
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#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF)
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/**
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* @}
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*/
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/** @defgroup FLASH_Keys
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* @{
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*/
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#define RDP_KEY ((uint16_t)0x00A5)
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#define FLASH_KEY1 ((uint32_t)0x45670123)
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#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
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#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B)
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#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F)
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/**
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* @}
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*/
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/**
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* @brief ACR register byte 0 (Bits[8:0]) base address
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*/
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#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
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/**
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* @brief OPTCR register byte 3 (Bits[24:16]) base address
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*/
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#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14)
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#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
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#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16)
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/* FLASH Interface configuration functions ************************************/
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void FLASH_SetLatency(uint32_t FLASH_Latency);
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void FLASH_PrefetchBufferCmd(FunctionalState NewState);
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void FLASH_InstructionCacheCmd(FunctionalState NewState);
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void FLASH_DataCacheCmd(FunctionalState NewState);
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void FLASH_InstructionCacheReset(void);
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void FLASH_DataCacheReset(void);
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/* FLASH Memory Programming functions *****************************************/
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void FLASH_Unlock(void);
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void FLASH_Lock(void);
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FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);
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FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);
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FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);
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FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
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FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
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FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
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/* Option Bytes Programming functions *****************************************/
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void FLASH_OB_Unlock(void);
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void FLASH_OB_Lock(void);
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void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
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void FLASH_OB_RDPConfig(uint8_t OB_RDP);
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void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
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void FLASH_OB_BORConfig(uint8_t OB_BOR);
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FLASH_Status FLASH_OB_Launch(void);
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uint8_t FLASH_OB_GetUser(void);
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uint16_t FLASH_OB_GetWRP(void);
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FlagStatus FLASH_OB_GetRDP(void);
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uint8_t FLASH_OB_GetBOR(void);
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/* Interrupts and flags management functions **********************************/
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void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
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FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
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void FLASH_ClearFlag(uint32_t FLASH_FLAG);
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FLASH_Status FLASH_GetStatus(void);
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FLASH_Status FLASH_WaitForLastOperation(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32F4xx_FLASH_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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