sam354xplaintedpro: Add uart tx ecample

Signed-off-by: Thomas Klaehn <thomas.klaehn@perinet.io>

.gitignore

@@ -1 +1,2 @@
 /target
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Cargo.toml

@@ -6,7 +6,7 @@ edition = "2021"
 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
 
 [dependencies]
-atsame54_xpro = { git = "https://github.com/atsamd-rs/atsamd"}
+atsame54_xpro = { version = "0.4.0" }
 # atsamd-hal = { version = "0.14.0", features = ["same54p"] }
 # cortex-m = { version = "0.7.4" }
 # cortex-m-rt = { version = "0.6.15" }

src/main.rs

@@ -15,7 +15,15 @@ use hal::delay::Delay;
 use hal::pac::{CorePeripherals, Peripherals};
 use hal::prelude::*;
 
-use hal::watchdog::{Watchdog, WatchdogTimeout};
+use hal::watchdog::{ Watchdog, WatchdogTimeout };
+
+use bsp::hal::sercom::{
+    v2::{
+        uart, uart::BaudMode, uart::Oversampling
+        }
+    };
+use embedded_hal::serial::Write;
+
 
 #[entry]
 fn main() -> ! {
@@ -34,6 +42,18 @@ fn main() -> ! {
     let pins = Pins::new(peripherals.PORT);
     let mut led = pins.pc18.into_mode::<ReadableOutput>();
 
+    let gclk0 = clocks.gclk0();
+    let clock = &clocks.sercom2_core(&gclk0).unwrap();
+    let pads = uart::Pads::default().rx(pins.pb24).tx(pins.pb25);
+    let mut uart_cfg = uart::Config::new(&peripherals.MCLK, peripherals.SERCOM2, pads, clock.freq());
+    uart_cfg.set_baud(115200.hz(), BaudMode::Arithmetic(Oversampling::Bits8));
+    let uart = uart_cfg.enable();
+
+    let (_, mut tx) = uart.split();
+
+    let s_off: &str = "off\r\n";
+    let s_on: &str = "on\r\n";
+
     let mut wdt = Watchdog::new(peripherals.WDT);
     wdt.start(WatchdogTimeout::Cycles256 as u8);
 
@@ -41,8 +61,14 @@ fn main() -> ! {
         delay.delay_ms(200u8);
         wdt.feed();
         led.set_high().unwrap();
+        for b in s_off.bytes() {
+            nb::block!(tx.write(b)).unwrap();
+        }
             delay.delay_ms(200u8);
         wdt.feed();
         led.set_low().unwrap();
+        for b in s_on.bytes() {
+            nb::block!(tx.write(b)).unwrap();
+        }
     }
 }