#include <assert.h>

#include "platform/nrf52/InterruptHandler.h"
#include "platform/nrf52/InterruptGuardian.h"

#include "platform/nrf52/spi.h"

extern "C" {
    #include "nrf52.h"
    #include "nrf52_bitfields.h"

    NRF_GPIO_Type *const GPIO_REGS = reinterpret_cast<NRF_GPIO_Type *>(NRF_P0_BASE);
    NRF_SPIM_Type *SPIM_REGS = reinterpret_cast<NRF_SPIM_Type *>(NRF_SPIM0_BASE);
}

using namespace pinetime::platform::nrf52;

Spi::Spi(uint32_t instance, uint32_t sck, uint32_t mosi, uint32_t miso, pinetime::interfaces::GpioInterface & cs)
    : InterruptHandler(InterruptGuardian::Nrf52IrqN::SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQ)
    , chip_select(cs)
    , xfer_active(false)
{
    assert(instance < 3);

    // sck pin
    GPIO_REGS->OUTCLR = 1UL << sck;
    GPIO_REGS->PIN_CNF[mosi] = GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos
                             | GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos
                             | GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos
                             | GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos
                             | GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos;
    // mosi pin
    GPIO_REGS->OUTCLR = 1UL << mosi;
    GPIO_REGS->PIN_CNF[mosi] = GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos
                             | GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos
                             | GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos
                             | GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos
                             | GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos;
    // miso pin
    GPIO_REGS->PIN_CNF[miso] = GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos
                             | GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos
                             | GPIO_PIN_CNF_PULL_Pulldown << GPIO_PIN_CNF_PULL_Pos
                             | GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos
                             | GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos;
    // ss already configured by gpio driver

    IRQn_Type irq = SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn;
    if(instance == 2) {
        SPIM_REGS = reinterpret_cast<NRF_SPIM_Type *>(NRF_SPIM2_BASE);
        irq = SPIM2_SPIS2_SPI2_IRQn;
    } else if(instance == 1) {
        SPIM_REGS = reinterpret_cast<NRF_SPIM_Type *>(NRF_SPIM1_BASE);
        irq = SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn;
    } else {
        SPIM_REGS = reinterpret_cast<NRF_SPIM_Type *>(NRF_SPIM0_BASE);
        irq = SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn;
    }

    this->chip_select.set();

    SPIM_REGS->ENABLE = 0;
    SPIM_REGS->PSEL.SCK = sck;
    SPIM_REGS->PSEL.MOSI = mosi;
    SPIM_REGS->PSEL.MISO = miso;
    SPIM_REGS->FREQUENCY = SPI_FREQUENCY_FREQUENCY_M8;

    SPIM_REGS->CONFIG = (0x03 << 1); //Sample on trailing edge of clock, shift serial data on leading edge, SCK polarity Active low
    SPIM_REGS->EVENTS_ENDRX = 0;
    SPIM_REGS->EVENTS_ENDTX = 0;
    SPIM_REGS->EVENTS_END = 0;

    SPIM_REGS->INTENSET = (1 << 1)      // Stopped
                        | (1 << 6)      // End
                        | (1 << 19);    // Started

    SPIM_REGS->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);

    NVIC_SetPriority(irq, 2);
    NVIC_EnableIRQ(irq);
}

Spi::~Spi()
{
    SPIM_REGS->ENABLE = 0;
}

void Spi::send(const uint8_t * buffer, uint32_t len)
{
    this->chip_select.clear();
    this->xfer_active = true;

    SPIM_REGS->TXD.PTR = reinterpret_cast<uint32_t>(buffer);
    SPIM_REGS->TXD.MAXCNT = len;
    SPIM_REGS->TXD.LIST = 0;

    SPIM_REGS->RXD.PTR = 0;
    SPIM_REGS->RXD.MAXCNT = 0;
    SPIM_REGS->RXD.LIST = 0;

    SPIM_REGS->EVENTS_END = 0;

    SPIM_REGS->TASKS_START = 1;

    // FIXME: LOW POWER???
    while(this->xfer_active);

    this->chip_select.set();
}

void Spi::recv(uint8_t * buffer, uint32_t len)
{
    // FIXME: not implemented yet
}

void Spi::handle()
{
    if((SPIM_REGS->INTENSET & (1 << 6)) && (SPIM_REGS->EVENTS_END == 1)) {
        SPIM_REGS->EVENTS_END = 0;
        this->xfer_active = false;
    }

    if((SPIM_REGS->INTENSET & (1 << 19)) && (SPIM_REGS->EVENTS_STARTED == 1)) {
        SPIM_REGS->EVENTS_STARTED = 0;
    }

    if((SPIM_REGS->INTENSET & (1 << 1)) && (SPIM_REGS->EVENTS_STOPPED == 1)) {
        SPIM_REGS->EVENTS_STOPPED = 0;
        this->xfer_active = false;
    }
}
