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multi-app based on nrf52sdk

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This commit is contained in:
Thomas Klaehn
2020-03-12 15:30:53 +01:00
parent df2d84dee1
commit 3a31e2bcb9
18 changed files with 3567 additions and 595 deletions
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100
include/platform/narf52/narf52.h
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#ifndef __PLATFORM_NARF52_NARF52_H__
#define __PLATFORM_NARF52_NARF52_H__
#include <stdint.h>
typedef enum {
/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
and No Match */
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
related Fault */
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* =========================================== nrf52 Specific Interrupt Numbers ============================================ */
POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
RADIO_IRQn = 1, /*!< 1 RADIO */
UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */
NFCT_IRQn = 5, /*!< 5 NFCT */
GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
SAADC_IRQn = 7, /*!< 7 SAADC */
TIMER0_IRQn = 8, /*!< 8 TIMER0 */
TIMER1_IRQn = 9, /*!< 9 TIMER1 */
TIMER2_IRQn = 10, /*!< 10 TIMER2 */
RTC0_IRQn = 11, /*!< 11 RTC0 */
TEMP_IRQn = 12, /*!< 12 TEMP */
RNG_IRQn = 13, /*!< 13 RNG */
ECB_IRQn = 14, /*!< 14 ECB */
CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
WDT_IRQn = 16, /*!< 16 WDT */
RTC1_IRQn = 17, /*!< 17 RTC1 */
QDEC_IRQn = 18, /*!< 18 QDEC */
COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */
SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */
SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */
SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */
SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */
SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */
SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */
TIMER3_IRQn = 26, /*!< 26 TIMER3 */
TIMER4_IRQn = 27, /*!< 27 TIMER4 */
PWM0_IRQn = 28, /*!< 28 PWM0 */
PDM_IRQn = 29, /*!< 29 PDM */
MWU_IRQn = 32, /*!< 32 MWU */
PWM1_IRQn = 33, /*!< 33 PWM1 */
PWM2_IRQn = 34, /*!< 34 PWM2 */
SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */
RTC2_IRQn = 36, /*!< 36 RTC2 */
I2S_IRQn = 37, /*!< 37 I2S */
FPU_IRQn = 38 /*!< 38 FPU */
} IRQn_Type;
/* =========================================================================================================================== */
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
#define __DSP_PRESENT 0 /*!< DSP present or not */
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __MPU_PRESENT 1 /*!< MPU present */
#define __FPU_PRESENT 1 /*!< FPU present */
#include "core_cm4.h"
struct narf52_gpio_type { /*!< (@ 0x50000000) P0 Structure */
__IM uint32_t RESERVED[321];
__IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */
__IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */
__IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */
__IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */
__IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */
__IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */
__IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */
__IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that
have met the criteria set in the PIN_CNF[n].SENSE
registers */
__IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour
and LDETECT mode */
__IM uint32_t RESERVED1[118];
__IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[0]: Configuration of GPIO
pins */
}; /*!< Size = 1920 (0x780) */
#define NARF_P0_BASE 0x50000000UL
#endif

131
include/platform/narf52/narf52_dk.h
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#ifndef __PLATFORM_NARF52_NARF52_DK_H
#define __PLATFORM_NARF52_NARF52_DK_H
#include "gpio.h"
#include "narf52_gpio.h"
#include "driver.h"
// LEDs
const struct narf52_gpio narf_led_1 = {
.pin_number = 17,
.dir = NARF_GPIO_DIR_OUT,
.input = NARF_GPIO_PIN_INPUT_DISCONNECT,
.pull = NARF_GPIO_PIN_NOPULL,
.drive = NARF_GPIO_PIN_S0S1,
.sense = NARF_GPIO_PIN_NOSENSE,
};
const struct driver led_1 = {
.name = "LED_1",
.fp = &gpio_fp,
.dev = (void *)&narf_led_1,
};
const struct narf52_gpio narf_led_2 = {
.pin_number = 18,
.dir = NARF_GPIO_DIR_OUT,
.input = NARF_GPIO_PIN_INPUT_DISCONNECT,
.pull = NARF_GPIO_PIN_NOPULL,
.drive = NARF_GPIO_PIN_S0S1,
.sense = NARF_GPIO_PIN_NOSENSE,
};
const struct driver led_2 = {
.name = "LED_2",
.fp = &gpio_fp,
.dev = (void *)&narf_led_2,
};
const struct narf52_gpio narf_led_3 = {
.pin_number = 19,
.dir = NARF_GPIO_DIR_OUT,
.input = NARF_GPIO_PIN_INPUT_DISCONNECT,
.pull = NARF_GPIO_PIN_NOPULL,
.drive = NARF_GPIO_PIN_S0S1,
.sense = NARF_GPIO_PIN_NOSENSE,
};
const struct driver led_3 = {
.name = "LED_3",
.fp = &gpio_fp,
.dev = (void *)&narf_led_3,
};
const struct narf52_gpio narf_led_4 = {
.pin_number = 20,
.dir = NARF_GPIO_DIR_OUT,
.input = NARF_GPIO_PIN_INPUT_DISCONNECT,
.pull = NARF_GPIO_PIN_NOPULL,
.drive = NARF_GPIO_PIN_S0S1,
.sense = NARF_GPIO_PIN_NOSENSE,
};
const struct driver led_4 = {
.name = "LED_4",
.fp = &gpio_fp,
.dev = (void *)&narf_led_4,
};
// BUTTONs
const struct narf52_gpio narf_button_1 = {
.pin_number = 13,
.dir = NARF_GPIO_DIR_IN,
.input = NARF_GPIO_PIN_INPUT_CONNECT,
.pull = NARF_GPIO_PIN_PULLUP,
.drive = NARF_GPIO_PIN_S0S1,
.sense = NARF_GPIO_PIN_NOSENSE,
};
const struct driver button_1 = {
.name = "BUTTON_1",
.fp = &gpio_fp,
.dev = (void *)&narf_button_1,
};
const struct narf52_gpio narf_button_2 = {
.pin_number = 14,
.dir = NARF_GPIO_DIR_IN,
.input = NARF_GPIO_PIN_INPUT_CONNECT,
.pull = NARF_GPIO_PIN_PULLUP,
.drive = NARF_GPIO_PIN_S0S1,
.sense = NARF_GPIO_PIN_NOSENSE,
};
const struct driver button_2 = {
.name = "BUTTON_2",
.fp = &gpio_fp,
.dev = (void *)&narf_button_2,
};
const struct narf52_gpio narf_button_3 = {
.pin_number = 15,
.dir = NARF_GPIO_DIR_IN,
.input = NARF_GPIO_PIN_INPUT_CONNECT,
.pull = NARF_GPIO_PIN_PULLUP,
.drive = NARF_GPIO_PIN_S0S1,
.sense = NARF_GPIO_PIN_NOSENSE,
};
const struct driver button_3 = {
.name = "BUTTON_3",
.fp = &gpio_fp,
.dev = (void *)&narf_button_3,
};
const struct narf52_gpio narf_button_4 = {
.pin_number = 16,
.dir = NARF_GPIO_DIR_IN,
.input = NARF_GPIO_PIN_INPUT_CONNECT,
.pull = NARF_GPIO_PIN_PULLUP,
.drive = NARF_GPIO_PIN_S0S1,
.sense = NARF_GPIO_PIN_NOSENSE,
};
const struct driver button_4 = {
.name = "BUTTON_4",
.fp = &gpio_fp,
.dev = (void *)&narf_button_4,
};
#endif

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include/platform/narf52/narf52_gpio.h
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#ifndef __PLATFORM_NARF52_NARF52_GPIO_H__
#define __PLATFORM_NARF52_NARF52_GPIO_H__
#include <stdint.h>
enum narf52_gpio_direction {
NARF_GPIO_DIR_IN = 0,
NARF_GPIO_DIR_OUT
};
enum narf52_gpio_pin_input {
NARF_GPIO_PIN_INPUT_CONNECT = 0, ///< Connect input buffer.
NARF_GPIO_PIN_INPUT_DISCONNECT ///< Disconnect input buffer.
};
enum narf52_gpio_pin_pull {
NARF_GPIO_PIN_NOPULL = 0, ///< Pin pull-up resistor disabled.
NARF_GPIO_PIN_PULLDOWN = 1, ///< Pin pull-down resistor enabled.
NARF_GPIO_PIN_PULLUP = 3 ///< Pin pull-up resistor enabled.
};
enum narf52_gpio_pin_drive {
NARF_GPIO_PIN_S0S1 = 0, ///< !< Standard '0', standard '1'.
NARF_GPIO_PIN_H0S1 = 1, ///< !< High-drive '0', standard '1'.
NARF_GPIO_PIN_S0H1 = 2, ///< !< Standard '0', high-drive '1'.
NARF_GPIO_PIN_H0H1 = 3, ///< !< High drive '0', high-drive '1'.
NARF_GPIO_PIN_D0S1 = 4, ///< !< Disconnect '0' standard '1'.
NARF_GPIO_PIN_D0H1 = 5, ///< !< Disconnect '0', high-drive '1'.
NARF_GPIO_PIN_S0D1 = 6, ///< !< Standard '0', disconnect '1'.
NARF_GPIO_PIN_H0D1 = 7 ///< !< High-drive '0', disconnect '1'.
};
enum narf52_gpio_pin_sense {
NARF_GPIO_PIN_NOSENSE = 0, ///< Pin sense level disabled.
NARF_GPIO_PIN_SENSE_LOW = 1, ///< Pin sense low level.
NARF_GPIO_PIN_SENSE_HIGH = 2 ///< Pin sense high level.
};
struct narf52_gpio {
uint32_t pin_number;
enum narf52_gpio_direction dir;
enum narf52_gpio_pin_input input;
enum narf52_gpio_pin_pull pull;
enum narf52_gpio_pin_drive drive;
enum narf52_gpio_pin_sense sense;
};
#endif