#ifndef __PINETIME_PLATFORM_NRF52_INTERRUPTGUARDIAN_H__ #define __PINETIME_PLATFORM_NRF52_INTERRUPTGUARDIAN_H__ #include extern "C" { #include "nrf52.h" } namespace pinetime::platform::nrf52 { class InterruptGuardian { public: InterruptGuardian(); enum Nrf52IrqN { POWER_CLOCK_IRQn, //!< 0 POWER_CLOCK RADIO_IRQn, //!< 1 RADIO UARTE0_UART0_IRQn, //!< 2 UARTE0_UART0 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, //!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, //!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 NFCT_IRQn, //!< 5 NFCT GPIOTE_IRQn, //!< 6 GPIOTE SAADC_IRQn, //!< 7 SAADC TIMER0_IRQn, //!< 8 TIMER0 TIMER1_IRQn, //!< 9 TIMER1 TIMER2_IRQn, //!< 10 TIMER2 RTC0_IRQn, //!< 11 RTC0 TEMP_IRQn, //!< 12 TEMP RNG_IRQn, //!< 13 RNG ECB_IRQn, //!< 14 ECB CCM_AAR_IRQn, //!< 15 CCM_AAR WDT_IRQn, //!< 16 WDT RTC1_IRQn, //!< 17 RTC1 QDEC_IRQn, //!< 18 QDEC COMP_LPCOMP_IRQn, //!< 19 COMP_LPCOMP SWI0_EGU0_IRQn, //!< 20 SWI0_EGU0 SWI1_EGU1_IRQn, //!< 21 SWI1_EGU1 SWI2_EGU2_IRQn, //!< 22 SWI2_EGU2 SWI3_EGU3_IRQn, //!< 23 SWI3_EGU3 SWI4_EGU4_IRQn, //!< 24 SWI4_EGU4 SWI5_EGU5_IRQn, //!< 25 SWI5_EGU5 TIMER3_IRQn, //!< 26 TIMER3 TIMER4_IRQn, //!< 27 TIMER4 PWM0_IRQn, //!< 28 PWM0 PDM_IRQn, //!< 29 PDM MWU_IRQn, //!< 32 MWU PWM1_IRQn, //!< 33 PWM1 PWM2_IRQn, //!< 34 PWM2 SPIM2_SPIS2_SPI2_IRQn, //!< 35 SPIM2_SPIS2_SPI2 RTC2_IRQn, //!< 36 RTC2 I2S_IRQn, //!< 37 I2S FPU_IRQn //!< 38 FPU }; private: enum { NRF52_HANDLER_COUNT = FPU_IRQn + 1, }; public: void register_handler(Nrf52IrqN irq_nr, InterruptHandler &); static InterruptGuardian instance; std::array nrf52_vector; }; } #endif