83 lines
3.8 KiB
C++
83 lines
3.8 KiB
C++
#ifndef __PINETIME_PLATFORM_NRF52_INTERRUPTGUARDIAN_H__
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#define __PINETIME_PLATFORM_NRF52_INTERRUPTGUARDIAN_H__
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#include <array>
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extern "C" {
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#include "nrf52.h"
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}
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namespace pinetime::platform::nrf52 {
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class InterruptGuardian
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{
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public:
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InterruptGuardian();
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enum Nrf52IrqN {
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// CM4 interrupts
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RESET_IRQ = 0, //!< -15 Reset Vector, invoked on Power up and warm reset
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NON_MASKABLE_INT_IRQ, //!< -14 Non maskable Interrupt, cannot be stopped or preempted
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HARD_FAULT_IRQ, //!< -13 Hard Fault, all classes of Fault
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MEMORY_MANAGEMENT_IRQ, //!< -12 Memory Management, MPU mismatch, including Access Violation and No Match
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BUS_FAULT_IRQ, //!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault
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USAGE_FAULT_IRQ, //!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition
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SV_CALL_IRQ, //!< -5 System Service Call via SVC instruction
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DEBUG_MONITOR_IRQ, //!< -4 Debug Monitor
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PEND_SV_IRQ, //!< -2 Pendable request for system service
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SYS_TICK_IRQ, //!< -1 System Tick Timer
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// nrf52 interrupts
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POWER_CLOCK_IRQn, //!< 0 POWER_CLOCK
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RADIO_IRQn, //!< 1 RADIO
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UARTE0_UART0_IRQn, //!< 2 UARTE0_UART0
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SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, //!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0
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SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, //!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1
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NFCT_IRQn, //!< 5 NFCT
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GPIOTE_IRQn, //!< 6 GPIOTE
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SAADC_IRQn, //!< 7 SAADC
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TIMER0_IRQn, //!< 8 TIMER0
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TIMER1_IRQn, //!< 9 TIMER1
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TIMER2_IRQn, //!< 10 TIMER2
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RTC0_IRQn, //!< 11 RTC0
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TEMP_IRQn, //!< 12 TEMP
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RNG_IRQn, //!< 13 RNG
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ECB_IRQn, //!< 14 ECB
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CCM_AAR_IRQn, //!< 15 CCM_AAR
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WDT_IRQn, //!< 16 WDT
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RTC1_IRQn, //!< 17 RTC1
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QDEC_IRQn, //!< 18 QDEC
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COMP_LPCOMP_IRQn, //!< 19 COMP_LPCOMP
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SWI0_EGU0_IRQn, //!< 20 SWI0_EGU0
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SWI1_EGU1_IRQn, //!< 21 SWI1_EGU1
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SWI2_EGU2_IRQn, //!< 22 SWI2_EGU2
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SWI3_EGU3_IRQn, //!< 23 SWI3_EGU3
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SWI4_EGU4_IRQn, //!< 24 SWI4_EGU4
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SWI5_EGU5_IRQn, //!< 25 SWI5_EGU5
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TIMER3_IRQn, //!< 26 TIMER3
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TIMER4_IRQn, //!< 27 TIMER4
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PWM0_IRQn, //!< 28 PWM0
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PDM_IRQn, //!< 29 PDM
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MWU_IRQn, //!< 32 MWU
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PWM1_IRQn, //!< 33 PWM1
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PWM2_IRQn, //!< 34 PWM2
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SPIM2_SPIS2_SPI2_IRQn, //!< 35 SPIM2_SPIS2_SPI2
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RTC2_IRQn, //!< 36 RTC2
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I2S_IRQn, //!< 37 I2S
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FPU_IRQn //!< 38 FPU
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};
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enum {
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NRF52_HANDLER_COUNT = FPU_IRQn + 1,
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};
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void register_handler(Nrf52IrqN irq_nr, InterruptHandler &);
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static InterruptGuardian instance;
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std::array<InterruptHandler *, NRF52_HANDLER_COUNT> nrf52_vector;
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};
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}
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#endif
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