546 lines
21 KiB
C
546 lines
21 KiB
C
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/**
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******************************************************************************
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* @file stm32g0xx_hal_pwr.c
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* @author MCD Application Team
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* @brief PWR HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of the Power Controller (PWR) peripheral:
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* + Initialization/de-initialization functions
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* + Peripheral Control functions
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2018 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32g0xx_hal.h"
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/** @addtogroup STM32G0xx_HAL_Driver
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* @{
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*/
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/** @addtogroup PWR
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* @{
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*/
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#ifdef HAL_PWR_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @defgroup PWR_Private_Defines PWR Private Defines
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* @{
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*/
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup PWR_Exported_Functions PWR Exported Functions
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* @{
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*/
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/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and de-initialization functions
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*
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@verbatim
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===============================================================================
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##### Initialization and de-initialization functions #####
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===============================================================================
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[..]
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@endverbatim
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* @{
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*/
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/**
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* @brief Deinitialize the HAL PWR peripheral registers to their default reset
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values.
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* @retval None
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*/
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void HAL_PWR_DeInit(void)
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{
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__HAL_RCC_PWR_FORCE_RESET();
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__HAL_RCC_PWR_RELEASE_RESET();
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}
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/**
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* @}
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*/
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/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
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* @brief Low Power modes configuration functions
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*
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@verbatim
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===============================================================================
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##### Peripheral Control functions #####
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===============================================================================
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[..]
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*** WakeUp pin configuration ***
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================================
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[..]
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(+) WakeUp pins are used to wakeup the system from Standby mode or
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Shutdown mode. WakeUp pins polarity can be set to configure event
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detection on high level (rising edge) or low level (falling edge).
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*** Low Power mode configuration ***
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=====================================
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[..]
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The devices feature 7 low-power modes:
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(+) Low-power run mode: core and peripherals are running at low frequency.
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Regulator is in low power mode.
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(+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running,
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regulator is main mode.
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(+) Low-power Sleep mode: Cortex-M0+ core stopped, peripherals kept running
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and regulator in low power mode.
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(+) Stop 0 mode: all clocks are stopped except LSI and LSE, regulator is
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main mode.
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(+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator
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off, low power regulator on.
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(+) Standby mode: all clocks are stopped except LSI and LSE, regulator is
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disable.
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(+) Shutdown mode: all clocks are stopped except LSE, regulator is
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disable.
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*** Low-power run mode ***
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==========================
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[..]
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(+) Entry: (from main run mode)
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(++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after
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having decreased the system clock below 2 MHz.
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(+) Exit:
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(++) clear LPR bit then wait for REGLPF bit to be reset with
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HAL_PWREx_DisableLowPowerRunMode() API. Only then can the
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system clock frequency be increased above 2 MHz.
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*** Sleep mode / Low-power sleep mode ***
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=========================================
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[..]
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(+) Entry:
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The Sleep & Low-power Sleep modes are entered through
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HAL_PWR_EnterSLEEPMode() API specifying whether or not the regulator
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is forced to low-power mode and if exit is interrupt or event
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triggered.
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(++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
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(++) PWR_LOWPOWERREGULATOR_ON: Low-power Sleep mode (regulator in low
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power mode). In this case, the system clock frequency must have
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been decreased below 2 MHz beforehand.
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(++) PWR_SLEEPENTRY_WFI: Core enters sleep mode with WFI instruction
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(++) PWR_SLEEPENTRY_WFE: Core enters sleep mode with WFE instruction
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(+) WFI Exit:
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(++) Any interrupt enabled in nested vectored interrupt controller (NVIC)
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(+) WFE Exit:
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(++) Any wakeup event if cortex is configured with SEVONPEND = 0
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(++) Interrupt even when disabled in NVIC if cortex is configured with
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SEVONPEND = 1
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[..] When exiting the Low-power Sleep mode by issuing an interrupt or a wakeup event,
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the MCU is in Low-power Run mode.
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*** Stop 0 & Stop 1 modes ***
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=============================
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[..]
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(+) Entry:
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The Stop modes are entered through the following APIs:
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(++) HAL_PWR_EnterSTOPMode() with following settings:
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(+++) PWR_MAINREGULATOR_ON to enter STOP0 mode.
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(+++) PWR_LOWPOWERREGULATOR_ON to enter STOP1 mode.
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(+) Exit (interrupt or event-triggered, specified when entering STOP mode):
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(++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
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(++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
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(+) WFI Exit:
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(++) Any EXTI line (internal or external) configured in interrupt mode
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with corresponding interrupt enable in NVIC
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(+) WFE Exit:
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(++) Any EXTI line (internal or external) configured in event mode if
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cortex is configured with SEVONPEND = 0
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(++) Any EXTI line configured in interrupt mode (even if the
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corresponding EXTI Interrupt vector is disabled in the NVIC) if
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cortex is configured with SEVONPEND = 0. The interrupt source can
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be external interrupts or peripherals with wakeup capability.
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[..] When exiting Stop, the MCU is either in Run mode or in Low-power Run mode
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depending on the LPR bit setting.
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*** Standby mode ***
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====================
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[..] In Standby mode, it is possible to keep backup SRAM content (defined as
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full SRAM) keeping low power regulator on. This is achievable by setting
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Ram retention bit calling HAL_PWREx_EnableSRAMRetention API. This increases
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power consumption.
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Its also possible to define I/O states using APIs:
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HAL_PWREx_EnableGPIOPullUp, HAL_PWREx_EnableGPIOPullDown &
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HAL_PWREx_EnablePullUpPullDownConfig
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(+) Entry:
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(++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API, by
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setting SLEEPDEEP in Cortex control register.
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(+) Exit:
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(++) WKUP pin edge detection, RTC event (wakeup, alarm, timestamp),
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tamper event (internal & external), LSE CSS detection, reset on
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NRST pin, IWDG reset & BOR reset.
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[..] Exiting Standby generates a power reset: Cortex is reset and execute
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Reset handler vector, all registers in the Vcore domain are set to
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their reset value. Registers outside the VCORE domain (RTC, WKUP, IWDG,
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and Standby/Shutdown modes control) are not impacted.
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*** Shutdown mode ***
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======================
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[..]
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In Shutdown mode,
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voltage regulator is disabled, all clocks are off except LSE, RRS bit is
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cleared. SRAM and registers contents are lost except for backup domain
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registers.
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(+) Entry:
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(++) The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API,
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by setting SLEEPDEEP in Cortex control register.
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(+) Exit:
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(++) WKUP pin edge detection, RTC event (wakeup, alarm, timestamp),
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tamper event (internal & external), LSE CSS detection, reset on
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NRST pin.
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[..] Exiting Shutdown generates a brown out reset: Cortex is reset and execute
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Reset handler vector, all registers are set to their reset value but ones
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in backup domain.
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@endverbatim
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* @{
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*/
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/**
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* @brief Enable access to the backup domain
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* (RTC & TAMP registers, backup registers, RCC BDCR register).
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* @note After reset, the backup domain is protected against
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* possible unwanted write accesses. All RTC & TAMP registers (backup
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* registers included) and RCC BDCR register are concerned.
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* @retval None
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*/
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void HAL_PWR_EnableBkUpAccess(void)
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{
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SET_BIT(PWR->CR1, PWR_CR1_DBP);
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}
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/**
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* @brief Disable access to the backup domain
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* @retval None
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*/
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void HAL_PWR_DisableBkUpAccess(void)
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{
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CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
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}
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/**
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* @brief Enable the WakeUp PINx functionality.
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* @param WakeUpPinPolarity Specifies which Wake-Up pin to enable.
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* This parameter can be one of the following legacy values which set
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* the default polarity i.e. detection on high level (rising edge):
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* @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3(*),
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* PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5(*),PWR_WAKEUP_PIN6
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* or one of the following value where the user can explicitly specify
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* the enabled pin and the chosen polarity:
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* @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
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* @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
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* @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW (*)
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* @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
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* @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW (*)
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* @arg @ref PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
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* @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
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* @note (*) availability depends on devices
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* @retval None
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*/
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void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
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{
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assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
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/* Specifies the Wake-Up pin polarity for the event detection
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(rising or falling edge) */
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MODIFY_REG(PWR->CR4, (PWR_CR4_WP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
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/* Enable wake-up pin */
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SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
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}
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/**
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* @brief Disable the WakeUp PINx functionality.
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* @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
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* This parameter can be one of the following values:
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* @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2,PWR_WAKEUP_PIN3(*),
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* PWR_WAKEUP_PIN4,PWR_WAKEUP_PIN5(*),PWR_WAKEUP_PIN6
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* @note (*) availability depends on devices
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* @retval None
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*/
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void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
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{
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assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
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CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
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}
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/**
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* @brief Enter Sleep or Low-power Sleep mode.
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* @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as
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* in Run mode.
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* @param Regulator Specifies the regulator state in Sleep/Low-power Sleep
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* mode. This parameter can be one of the following values:
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* @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
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* @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator
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* in low-power mode)
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* @note Low-power Sleep mode is entered from Low-power Run mode only. In
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* case Regulator parameter is set to Low Power but MCU is in Run mode,
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* we will first enter in Low-power Run mode. Therefore, user should
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* take care that HCLK frequency is less than 2 MHz.
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* @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode.
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* To switch back to Run mode, user must call
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* HAL_PWREx_DisableLowPowerRunMode() API.
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* @param SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE
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* instruction. This parameter can be one of the following values:
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* @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep
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* mode with WFI instruction
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* @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep
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* mode with WFE instruction
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* @note When WFI entry is used, tick interrupt have to be disabled if not
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* desired as the interrupt wake up source.
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* @retval None
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*/
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void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
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{
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/* Check the parameters */
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assert_param(IS_PWR_REGULATOR(Regulator));
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assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
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/* Set Regulator parameter */
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if(Regulator != PWR_MAINREGULATOR_ON)
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{
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/* If in run mode, first move to low-power run mode.
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The system clock frequency must be below 2 MHz at this point. */
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if((PWR->SR2 & PWR_SR2_REGLPF) == 0x00u)
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{
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HAL_PWREx_EnableLowPowerRunMode();
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}
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}
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else
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{
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/* If in low-power run mode at this point, exit it */
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if((PWR->SR2 & PWR_SR2_REGLPF) != 0x00u)
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{
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if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
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{
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return ;
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}
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}
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}
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/* Clear SLEEPDEEP bit of Cortex System Control Register */
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CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
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/* Select SLEEP mode entry -------------------------------------------------*/
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||
|
|
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
||
|
|
{
|
||
|
|
/* Request Wait For Interrupt */
|
||
|
|
__WFI();
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Request Wait For Event */
|
||
|
|
__SEV();
|
||
|
|
__WFE();
|
||
|
|
__WFE();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enter Stop mode
|
||
|
|
* @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with
|
||
|
|
* legacy code running on devices where only "Stop mode" is mentioned
|
||
|
|
* with main or low power regulator ON.
|
||
|
|
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||
|
|
* @note All clocks in the VCORE domain are stopped; the PLL, the HSI and the
|
||
|
|
* HSE oscillators are disabled. Some peripherals with the wakeup
|
||
|
|
* capability can switch on the HSI to receive a frame, and switch off
|
||
|
|
* the HSI after receiving the frame if it is not a wakeup frame.
|
||
|
|
* SRAM and register contents are preserved.
|
||
|
|
* The BOR is available.
|
||
|
|
* The voltage regulator can be configured either in normal (Stop 0) or
|
||
|
|
* low-power mode (Stop 1).
|
||
|
|
* @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a
|
||
|
|
* wakeup event, the HSI RC oscillator is selected as system clock
|
||
|
|
* @note When the voltage regulator operates in low power mode (Stop 1),
|
||
|
|
* an additional startup delay is incurred when waking up. By keeping
|
||
|
|
* the internal regulator ON during Stop mode (Stop 0), the consumption
|
||
|
|
* is higher although the startup time is reduced.
|
||
|
|
* @param Regulator Specifies the regulator state in Stop mode
|
||
|
|
* This parameter can be one of the following values:
|
||
|
|
* @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
|
||
|
|
* @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power
|
||
|
|
* regulator ON)
|
||
|
|
* @param STOPEntry Specifies Stop 0 or Stop 1 mode is entered with WFI or
|
||
|
|
* WFE instruction. This parameter can be one of the following values:
|
||
|
|
* @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI
|
||
|
|
* instruction.
|
||
|
|
* @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE
|
||
|
|
* instruction.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
||
|
|
{
|
||
|
|
/* Check the parameters */
|
||
|
|
assert_param(IS_PWR_REGULATOR(Regulator));
|
||
|
|
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
||
|
|
|
||
|
|
if (Regulator != PWR_MAINREGULATOR_ON)
|
||
|
|
{
|
||
|
|
/* Stop mode with Low-Power Regulator */
|
||
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP1);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Stop mode with Main Regulator */
|
||
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP0);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
|
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
|
|
|
||
|
|
/* Select Stop mode entry --------------------------------------------------*/
|
||
|
|
if(STOPEntry == PWR_STOPENTRY_WFI)
|
||
|
|
{
|
||
|
|
/* Request Wait For Interrupt */
|
||
|
|
__WFI();
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Request Wait For Event */
|
||
|
|
__SEV();
|
||
|
|
__WFE();
|
||
|
|
__WFE();
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enter Standby mode.
|
||
|
|
* @note In Standby mode, the PLL, the HSI and the HSE oscillators are
|
||
|
|
* switched off. The voltage regulator is disabled. SRAM and register
|
||
|
|
* contents are lost except for registers in the Backup domain and
|
||
|
|
* Standby circuitry. BOR is available.
|
||
|
|
* @note The I/Os can be configured either with a pull-up or pull-down or can
|
||
|
|
* be kept in analog state.
|
||
|
|
* HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown()
|
||
|
|
* respectively enable Pull Up and PullDown state.
|
||
|
|
* HAL_PWREx_DisableGPIOPullUp() & HAL_PWREx_DisableGPIOPullDown()
|
||
|
|
* disable the same. These states are effective in Standby mode only if
|
||
|
|
* APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
|
||
|
|
* @note Sram content can be kept setting RRS through HAL_PWREx_EnableSRAMRetention()
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_EnterSTANDBYMode(void)
|
||
|
|
{
|
||
|
|
/* Set Stand-by mode */
|
||
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STANDBY);
|
||
|
|
|
||
|
|
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||
|
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||
|
|
|
||
|
|
/* This option is used to ensure that store operations are completed */
|
||
|
|
#if defined ( __CC_ARM)
|
||
|
|
__force_stores();
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Request Wait For Interrupt */
|
||
|
|
__WFI();
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable Sleep-On-Exit Cortex feature
|
||
|
|
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the
|
||
|
|
* processor enters SLEEP or DEEPSLEEP mode when an interruption
|
||
|
|
* handling is over returning to thread mode. Setting this bit is
|
||
|
|
* useful when the processor is expected to run only on interruptions
|
||
|
|
* handling.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_EnableSleepOnExit(void)
|
||
|
|
{
|
||
|
|
/* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||
|
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disable Sleep-On-Exit Cortex feature
|
||
|
|
* @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the
|
||
|
|
* processor enters SLEEP or DEEPSLEEP mode when an interruption
|
||
|
|
* handling is over.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_DisableSleepOnExit(void)
|
||
|
|
{
|
||
|
|
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable Cortex Sev On Pending feature.
|
||
|
|
* @note Set SEVONPEND bit of SCR register. When this bit is set, enabled
|
||
|
|
* events and all interrupts, including disabled ones can wakeup
|
||
|
|
* processor from WFE.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_EnableSEVOnPend(void)
|
||
|
|
{
|
||
|
|
/* Set SEVONPEND bit of Cortex System Control Register */
|
||
|
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disable Cortex Sev On Pending feature.
|
||
|
|
* @note Clear SEVONPEND bit of SCR register. When this bit is clear, only
|
||
|
|
* enable interrupts or events can wakeup processor from WFE
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void HAL_PWR_DisableSEVOnPend(void)
|
||
|
|
{
|
||
|
|
/* Clear SEVONPEND bit of Cortex System Control Register */
|
||
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
#endif /* HAL_PWR_MODULE_ENABLED */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|