1350 lines
91 KiB
C
1350 lines
91 KiB
C
//*****************************************************************************
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//
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// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//*****************************************************************************
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#ifndef __HW_GPIO_H__
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#define __HW_GPIO_H__
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//*****************************************************************************
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//
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// The following are defines for the GPIO register offsets.
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//
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//*****************************************************************************
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#define GPIO_O_GPIO_DATA 0x00000000 // 0x4000 5000 0x4000 6000 0x4000
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// 7000 0x4002 4000 GPIO Data
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// (GPIODATA)@@ offset 0x000 The
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// GPIODATA register is the data
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// register. In software control
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// mode@@ values written in the
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// GPIODATA register are transferred
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// onto the GPIO port pins if the
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// respective pins have been
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// configured as outputs through the
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// GPIO Direction (GPIODIR) register
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// (see page 653). In order to write
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// to GPIODATA@@ the corresponding
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// bits in the mask@@ resulting from
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// the address bus bits [9:2]@@ must
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// be set. Otherwise@@ the bit
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// values remain unchanged by the
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// write. Similarly@@ the values
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// read from this register are
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// determined for each bit by the
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// mask bit derived from the address
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// used to access the data
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// register@@ bits [9:2]. Bits that
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// are set in the address mask cause
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// the corresponding bits in
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// GPIODATA to be read@@ and bits
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// that are clear in the address
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// mask cause the corresponding bits
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// in GPIODATA to be read as 0@@
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// regardless of their value. A read
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// from GPIODATA returns the last
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// bit value written if the
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// respective pins are configured as
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// outputs@@ or it returns the value
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// on the corresponding input pin
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// when these are configured as
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// inputs. All bits are cleared by a
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// reset.
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#define GPIO_O_GPIO_DIR 0x00000400 // 0x4000 5400 0x4000 6400 0x4000
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// 7400 0x4002 4400 GPIO Direction
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// (GPIODIR)@@ offset 0x400 The
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// GPIODIR register is the data
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// direction register. Setting a bit
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// in the GPIODIR register
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// configures the corresponding pin
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// to be an output@@ while clearing
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// a bit configures the
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// corresponding pin to be an input.
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// All bits are cleared by a reset@@
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// meaning all GPIO pins are inputs
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// by default.
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#define GPIO_O_GPIO_IS 0x00000404 // 0x4000 5404 0x4000 6404 0x4000
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// 7404 0x4002 4404 GPIO Interrupt
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// Sense (GPIOIS)@@ offset 0x404 The
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// GPIOIS register is the interrupt
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// sense register. Setting a bit in
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// the GPIOIS register configures
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// the corresponding pin to detect
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// levels@@ while clearing a bit
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// configures the corresponding pin
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// to detect edges. All bits are
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// cleared by a reset.
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#define GPIO_O_GPIO_IBE 0x00000408 // 0x4000 5408 0x4000 6408 0x4000
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// 7408 0x4002 4408 GPIO Interrupt
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// Both Edges (GPIOIBE)@@ offset
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// 0x408 The GPIOIBE register allows
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// both edges to cause interrupts.
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// When the corresponding bit in the
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// GPIO Interrupt Sense (GPIOIS)
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// register is set to detect edges@@
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// setting a bit in the GPIOIBE
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// register configures the
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// corresponding pin to detect both
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// rising and falling edges@@
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// regardless of the corresponding
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// bit in the GPIO Interrupt Event
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// (GPIOIEV) register . Clearing a
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// bit configures the pin to be
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// controlled by the GPIOIEV
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// register. All bits are cleared by
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// a reset.
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#define GPIO_O_GPIO_IEV 0x0000040C // 0x4000 540C 0x4000 640C 0x4000
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// 740C 0x4002 440C GPIO Interrupt
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// Event (GPIOIEV)@@ offset 0x40C
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// The GPIOIEV register is the
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// interrupt event register. Setting
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// a bit in the GPIOIEV register
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// configures the corresponding pin
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// to detect rising edges or high
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// levels@@ depending on the
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// corresponding bit value in the
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// GPIO Interrupt Sense (GPIOIS)
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// register . Clearing a bit
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// configures the pin to detect
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// falling edges or low levels@@
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// depending on the corresponding
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// bit value in the GPIOIS register.
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// All bits are cleared by a reset.
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#define GPIO_O_GPIO_IM 0x00000410 // 0x4000 5410 0x4000 6410 0x4000
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// 7410 0x4002 4410 GPIO Interrupt
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// Mask (GPIOIM)@@ offset 0x410 The
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// GPIOIM register is the interrupt
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// mask register. Setting a bit in
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// the GPIOIM register allows
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// interrupts that are generated by
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// the corresponding pin to be sent
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// to the interrupt controller on
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// the combined interrupt signal.
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// Clearing a bit prevents an
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// interrupt on the corresponding
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// pin from being sent to the
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// interrupt controller. All bits
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// are cleared by a reset.
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#define GPIO_O_GPIO_RIS 0x00000414 // 0x4000 5414 0x4000 6414 0x4000
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// 7414 0x4002 4414 GPIO Raw
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// Interrupt Status (GPIORIS)@@
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// offset 0x414 The GPIORIS register
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// is the raw interrupt status
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// register. A bit in this register
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// is set when an interrupt
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// condition occurs on the
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// corresponding GPIO pin. If the
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// corresponding bit in the GPIO
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// Interrupt Mask (GPIOIM) register
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// is set@@ the interrupt is sent to
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// the interrupt controller. Bits
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// read as zero indicate that
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// corresponding input pins have not
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// initiated an interrupt. A bit in
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// this register can be cleared by
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// writing a 1 to the corresponding
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// bit in the GPIO Interrupt Clear
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// (GPIOICR) register.
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#define GPIO_O_GPIO_MIS 0x00000418 // 0x4000 5418 0x4000 6418 0x4000
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// 7418 0x4002 4418 GPIO Masked
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// Interrupt Status (GPIOMIS)@@
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// offset 0x418 The GPIOMIS register
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// is the masked interrupt status
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// register. If a bit is set in this
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// register@@ the corresponding
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// interrupt has triggered an
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// interrupt to the interrupt
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// controller. If a bit is clear@@
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// either no interrupt has been
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// generated@@ or the interrupt is
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// masked. If no port pin@@ other
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// than the one that is being used
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// as an ADC trigger@@ is being used
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// to generate interrupts@@ the
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// appropriate Interrupt Set Enable
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// (ENn) register can disable the
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// interrupts for the port@@ and the
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// ADC interrupt can be used to read
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// back the converted data.
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// Otherwise@@ the port interrupt
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// handler must ignore and clear
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// interrupts on the port pin and
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// wait for the ADC interrupt@@ or
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// the ADC interrupt must be
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// disabled in the EN0 register and
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// the port interrupt handler must
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// poll the ADC registers until the
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// conversion is completed. If no
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// port pin@@ other than the one
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// that is being used as an ADC
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// trigger@@ is being used to
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// generate interrupts@@ the
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// appropriate Interrupt Set Enable
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// (ENn) register can disable the
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// interrupts for the port@@ and the
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// ADC interrupt can be used to read
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// back the converted data.
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// Otherwise@@ the port interrupt
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// handler must ignore and clear
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// interrupts on the port pin and
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// wait for the ADC interrupt@@ or
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// the ADC interrupt must be
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// disabled in the EN0 register and
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// the port interrupt handler must
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// poll the ADC registers until the
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// conversion is completed. Note
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// that if the Port B GPIOADCCTL
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// register is cleared@@ PB4 can
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// still be used as an external
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// trigger for the ADC. This is a
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// legacy mode which allows code
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// written for previous Stellaris
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// devices to operate on this
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// microcontroller. GPIOMIS is the
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// state of the interrupt after
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// masking.
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#define GPIO_O_GPIO_ICR 0x0000041C // 0x4000 541C 0x4000 641C 0x4000
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// 741C 0x4002 441C GPIO Interrupt
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// Clear (GPIOICR)@@ offset 0x41C
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// The GPIOICR register is the
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// interrupt clear register. Writing
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// a 1 to a bit in this register
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// clears the corresponding
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// interrupt bit in the GPIORIS and
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// GPIOMIS registers. Writing a 0
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// has no effect.
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#define GPIO_O_GPIO_AFSEL 0x00000420 // 0x4000 5420 0x4000 6420 0x4000
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// 7420 0x4002 4420 GPIO Alternate
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// Function Select (GPIOAFSEL)@@
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// offset 0x420 The GPIOAFSEL
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// register is the mode control
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// select register. If a bit is
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// clear@@ the pin is used as a GPIO
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// and is controlled by the GPIO
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// registers. Setting a bit in this
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// register configures the
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// corresponding GPIO line to be
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// controlled by an associated
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// peripheral. Several possible
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// peripheral functions are
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// multiplexed on each GPIO. The
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// GPIO Port Control (GPIOPCTL)
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// register is used to select one of
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// the possible functions.
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#define GPIO_O_GPIO_DR2R 0x00000500 // 0x4000 5500 0x4000 6500 0x4000
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// 7500 0x4002 4500 GPIO 2-mA Drive
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// Select (GPIODR2R)@@ offset 0x500
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// The GPIODR2R register is the 2-mA
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// drive control register. Each GPIO
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// signal in the port can be
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// individually configured without
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// affecting the other pads. When
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// setting the DRV2 bit for a GPIO
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// signal@@ the corresponding DRV4
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// bit in the GPIODR4R register and
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// DRV8 bit in the GPIODR8R register
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// are automatically cleared by
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// hardware. By default@@ all GPIO
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// pins have 2-mA drive.
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#define GPIO_O_GPIO_DR4R 0x00000504 // 0x4000 5504 0x4000 6504 0x4000
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// 7504 0x4002 4504 GPIO 4-mA Drive
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// Select (GPIODR4R)@@ offset 0x504
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// The GPIODR4R register is the 4-mA
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// drive control register. Each GPIO
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// signal in the port can be
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// individually configured without
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// affecting the other pads. When
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// setting the DRV4 bit for a GPIO
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// signal@@ the corresponding DRV2
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// bit in the GPIODR2R register and
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// DRV8 bit in the GPIODR8R register
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// are automatically cleared by
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// hardware.
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#define GPIO_O_GPIO_DR8R 0x00000508 // 0x4000 5508 0x4000 6508 0x4000
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// 7508 0x4002 4508 GPIO 8-mA Drive
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// Select (GPIODR8R)@@ offset 0x508
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// The GPIODR8R register is the 8-mA
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// drive control register. Each GPIO
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// signal in the port can be
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// individually configured without
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// affecting the other pads. When
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// setting the DRV8 bit for a GPIO
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// signal@@ the corresponding DRV2
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// bit in the GPIODR2R register and
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// DRV4 bit in the GPIODR4R register
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// are automatically cleared by
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// hardware. The 8-mA setting is
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// also used for high-current
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// operation. Note: There is no
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// configuration difference between
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// 8-mA and high-current operation.
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// The additional current capacity
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// results from a shift in the
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// VOH/VOL levels.
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#define GPIO_O_GPIO_ODR 0x0000050C // 0x4000 550C 0x4000 650C 0x4000
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// 750C 0x4002 450C GPIO Open Drain
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// Select (GPIOODR)@@ offset 0x50C
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// The GPIOODR register is the open
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// drain control register. Setting a
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// bit in this register enables the
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// open-drain configuration of the
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// corresponding GPIO pad. When
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// open-drain mode is enabled@@ the
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// corresponding bit should also be
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// set in the GPIO Digital Input
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// Enable (GPIODEN) register .
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// Corresponding bits in the drive
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// strength and slew rate control
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// registers (GPIODR2R@@ GPIODR4R@@
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// GPIODR8R@@ and GPIOSLR) can be
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// set to achieve the desired rise
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// and fall times. The GPIO acts as
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// an open-drain input if the
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// corresponding bit in the GPIODIR
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// register is cleared. If open
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// drain is selected while the GPIO
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// is configured as an input@@ the
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// GPIO will remain an input and the
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// open-drain selection has no
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// effect until the GPIO is changed
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// to an output. When using the I2C
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// module@@ in addition to
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// configuring the pin to open
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// drain@@ the GPIO Alternate
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// Function Select (GPIOAFSEL)
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// register bits for the I2C clock
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// and data pins should be set
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#define GPIO_O_GPIO_PUR 0x00000510 // 0x4000 5510 0x4000 6510 0x4000
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// 7510 0x4002 4510 GPIO Pull-Up
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// Select (GPIOPUR)@@ offset 0x510
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// The GPIOPUR register is the
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// pull-up control register. When a
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// bit is set@@ a weak pull-up
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// resistor on the corresponding
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// GPIO signal is enabled. Setting a
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// bit in GPIOPUR automatically
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// clears the corresponding bit in
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// the GPIO Pull-Down Select
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// (GPIOPDR) register . Write access
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// to this register is protected
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// with the GPIOCR register. Bits in
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// GPIOCR that are cleared prevent
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// writes to the equivalent bit in
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// this register.
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#define GPIO_O_GPIO_PDR 0x00000514 // 0x4000 5514 0x4000 6514 0x4000
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// 7514 0x4002 4514 GPIO Pull-Down
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// Select (GPIOPDR)@@ offset 0x514
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// The GPIOPDR register is the
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// pull-down control register. When
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// a bit is set@@ a weak pull-down
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// resistor on the corresponding
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// GPIO signal is enabled. Setting a
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// bit in GPIOPDR automatically
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// clears the corresponding bit in
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// the GPIO Pull-Up Select (GPIOPUR)
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// register
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#define GPIO_O_GPIO_SLR 0x00000518 // 0x4000 5518 0x4000 6518 0x4000
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// 7518 0x4002 4518 The GPIOSLR
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// register is the slew rate control
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// register. Slew rate control is
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// only available when using the
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// 8-mA drive strength option via
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// the GPIO 8-mA Drive Select
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// (GPIODR8R) register
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#define GPIO_O_GPIO_DEN 0x0000051C // 0x4000 551C 0x4000 651C 0x4000
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// 751C 0x4002 451C GPIO Digital
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// Enable (GPIODEN)@@ offset 0x51C
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// Note: Pins configured as digital
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// inputs are Schmitt-triggered. The
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// GPIODEN register is the digital
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// enable register. By default@@ all
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// GPIO signals except those listed
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// below are configured out of reset
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// to be undriven (tristate). Their
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// digital function is disabled;
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// they do not drive a logic value
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// on the pin and they do not allow
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// the pin voltage into the GPIO
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// receiver. To use the pin as a
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// digital input or output (either
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// GPIO or alternate function)@@ the
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// corresponding GPIODEN bit must be
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// set.
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#define GPIO_O_GPIO_LOCK 0x00000520 // 0x4000 5520 0x4000 6520 0x4000
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// 7520 0x4002 4520 GPIO Lock
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// (GPIOLOCK)@@ offset 0x520 The
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// GPIOLOCK register enables write
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// access to the GPIOCR register .
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// Writing 0x4C4F.434B to the
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// GPIOLOCK register unlocks the
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// GPIOCR register. Writing any
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// other value to the GPIOLOCK
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// register re-enables the locked
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// state. Reading the GPIOLOCK
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// register returns the lock status
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// rather than the 32-bit value that
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// was previously written.
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// Therefore@@ when write accesses
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// are disabled@@ or locked@@
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// reading the GPIOLOCK register
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// returns 0x0000.0001. When write
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// accesses are enabled@@ or
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// unlocked@@ reading the GPIOLOCK
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// register returns 0x0000.0000.
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#define GPIO_O_GPIO_CR 0x00000524 // 0x4000 5524 0x4000 6524 0x4000
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// 7524 0x4002 4524 GPIO Commit
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// (GPIOCR)@@ offset 0x524 The
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// GPIOCR register is the commit
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// register. The value of the GPIOCR
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// register determines which bits of
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// the GPIOAFSEL@@ GPIOPUR@@
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// GPIOPDR@@ and GPIODEN registers
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// are committed when a write to
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// these registers is performed. If
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// a bit in the GPIOCR register is
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// cleared@@ the data being written
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// to the corresponding bit in the
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// GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@
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// or GPIODEN registers cannot be
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// committed and retains its
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// previous value. If a bit in the
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// GPIOCR register is set@@ the data
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// being written to the
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// corresponding bit of the
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// GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@
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// or GPIODEN registers is committed
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// to the register and reflects the
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// new value. The contents of the
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// GPIOCR register can only be
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// modified if the status in the
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// GPIOLOCK register is unlocked.
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// Writes to the GPIOCR register are
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// ignored if the status in the
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// GPIOLOCK register is locked.
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#define GPIO_O_GPIO_AMSEL 0x00000528 // 0x4000 5528 0x4000 6528 0x4000
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// 7528 0x4002 4528 The GPIOAMSEL
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// register controls isolation
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// circuits to the analog side of a
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// unified I/O pad. Because the
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// GPIOs may be driven by a 5-V
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// source and affect analog
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// operation@@ analog circuitry
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// requires isolation from the pins
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// when they are not used in their
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// analog function. Each bit of this
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// register controls the isolation
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// circuitry for the corresponding
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// GPIO signal.
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#define GPIO_O_GPIO_PCTL 0x0000052C // This register is not used in
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// cc3xx. equivalant register exsist
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// outside GPIO IP (refer
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// PAD*_config register in the
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// shared comn space) 0x4000 552C
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// 0x4000 652C 0x4000 752C 0x4002
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// 452C GPIO Port Control
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// (GPIOPCTL)@@ offset 0x52C The
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// GPIOPCTL register is used in
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// conjunction with the GPIOAFSEL
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// register and selects the specific
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// peripheral signal for each GPIO
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// pin when using the alternate
|
|
// function mode. Most bits in the
|
|
// GPIOAFSEL register are cleared on
|
|
// reset@@ therefore most GPIO pins
|
|
// are configured as GPIOs by
|
|
// default. When a bit is set in the
|
|
// GPIOAFSEL register@@ the
|
|
// corresponding GPIO signal is
|
|
// controlled by an associated
|
|
// peripheral. The GPIOPCTL register
|
|
// selects one out of a set of
|
|
// peripheral functions for each
|
|
// GPIO@@ providing additional
|
|
// flexibility in signal definition.
|
|
#define GPIO_O_GPIO_ADCCTL 0x00000530 // This register is not used in
|
|
// cc3xx. ADC trigger via GPIO is
|
|
// not supported. 0x4000 5530 0x4000
|
|
// 6530 0x4000 7530 0x4002 4530 GPIO
|
|
// ADC Control (GPIOADCCTL)@@ offset
|
|
// 0x530 This register is used to
|
|
// configure a GPIO pin as a source
|
|
// for the ADC trigger. Note that if
|
|
// the Port B GPIOADCCTL register is
|
|
// cleared@@ PB4 can still be used
|
|
// as an external trigger for the
|
|
// ADC. This is a legacy mode which
|
|
// allows code written for previous
|
|
// Stellaris devices to operate on
|
|
// this microcontroller.
|
|
#define GPIO_O_GPIO_DMACTL 0x00000534 // 0x4000 5534 0x4000 6534 0x4000
|
|
// 7534 0x4002 4534 GPIO DMA Control
|
|
// (GPIODMACTL)@@ offset 0x534 This
|
|
// register is used to configure a
|
|
// GPIO pin as a source for the ?DMA
|
|
// trigger.
|
|
#define GPIO_O_GPIO_SI 0x00000538 // 0x4000 5538 0x4000 6538 0x4000
|
|
// 7538 0x4002 4538 GPIO Select
|
|
// Interrupt (GPIOSI)@@ offset 0x538
|
|
// This register is used to enable
|
|
// individual interrupts for each
|
|
// pin. Note: This register is only
|
|
// available on Port P and Port Q.
|
|
#define GPIO_O_GPIO_PERIPHID4 0x00000FD0 // 0x4000 5FD0 0x4000 6FD0 0x4000
|
|
// 7FD0 0x4002 4FD0 GPIO Peripheral
|
|
// Identification 4
|
|
// (GPIOPeriphID4)@@ offset 0xFD0
|
|
// The GPIOPeriphID4@@
|
|
// GPIOPeriphID5@@ GPIOPeriphID6@@
|
|
// and GPIOPeriphID7 registers can
|
|
// conceptually be treated as one
|
|
// 32-bit register; each register
|
|
// contains eight bits of the 32-bit
|
|
// register@@ used by software to
|
|
// identify the peripheral.
|
|
#define GPIO_O_GPIO_PERIPHID5 0x00000FD4 // 0x4000 5FD4 0x4000 6FD4 0x4000
|
|
// 7FD4 0x4002 4FD4 GPIO Peripheral
|
|
// Identification 5
|
|
// (GPIOPeriphID5)@@ offset 0xFD4
|
|
// The GPIOPeriphID4@@
|
|
// GPIOPeriphID5@@ GPIOPeriphID6@@
|
|
// and GPIOPeriphID7 registers can
|
|
// conceptually be treated as one
|
|
// 32-bit register; each register
|
|
// contains eight bits of the 32-bit
|
|
// register@@ used by software to
|
|
// identify the peripheral.
|
|
#define GPIO_O_GPIO_PERIPHID6 0x00000FD8 // 0x4000 5FD8 0x4000 6FD8 0x4000
|
|
// 7FD8 0x4002 4FD8 GPIO Peripheral
|
|
// Identification 6
|
|
// (GPIOPeriphID6)@@ offset 0xFD8
|
|
// The GPIOPeriphID4@@
|
|
// GPIOPeriphID5@@ GPIOPeriphID6@@
|
|
// and GPIOPeriphID7 registers can
|
|
// conceptually be treated as one
|
|
// 32-bit register; each register
|
|
// contains eight bits of the 32-bit
|
|
// register@@ used by software to
|
|
// identify the peripheral.
|
|
#define GPIO_O_GPIO_PERIPHID7 0x00000FDC // 0x4000 5FDC 0x4000 6FDC 0x4000
|
|
// 7FDC 0x4002 4FDC GPIO Peripheral
|
|
// Identification 7
|
|
// (GPIOPeriphID7)@@ offset 0xFDC
|
|
// The GPIOPeriphID4@@
|
|
// GPIOPeriphID5@@ GPIOPeriphID6@@
|
|
// and GPIOPeriphID7 registers can
|
|
// conceptually be treated as one
|
|
// 32-bit register; each register
|
|
// contains eight bits of the 32-bit
|
|
// register@@ used by software to
|
|
// identify the peripheral.
|
|
#define GPIO_O_GPIO_PERIPHID0 0x00000FE0 // 0x4000 5FE0 0x4000 6FE0 0x4000
|
|
// 7FE0 0x4002 4FE0 GPIO Peripheral
|
|
// Identification 0
|
|
// (GPIOPeriphID0)@@ offset 0xFE0
|
|
// The GPIOPeriphID0@@
|
|
// GPIOPeriphID1@@ GPIOPeriphID2@@
|
|
// and GPIOPeriphID3 registers can
|
|
// conceptually be treated as one
|
|
// 32-bit register; each register
|
|
// contains eight bits of the 32-bit
|
|
// register@@ used by software to
|
|
// identify the peripheral.
|
|
#define GPIO_O_GPIO_PERIPHID1 0x00000FE4 // 0x4000 5FE4 0x4000 6FE4 0x4000
|
|
// 7FE4 0x4002 4FE4 GPIO Peripheral
|
|
// Identification 1
|
|
// (GPIOPeriphID1)@@ offset 0xFE4
|
|
// The GPIOPeriphID0@@
|
|
// GPIOPeriphID1@@ GPIOPeriphID2@@
|
|
// and GPIOPeriphID3 registers can
|
|
// conceptually be treated as one
|
|
// 32-bit register; each register
|
|
// contains eight bits of the 32-bit
|
|
// register@@ used by software to
|
|
// identify the peripheral.
|
|
#define GPIO_O_GPIO_PERIPHID2 0x00000FE8 // 0x4000 5FE8 0x4000 6FE8 0x4000
|
|
// 7FE8 0x4002 4FE8 GPIO Peripheral
|
|
// Identification 2
|
|
// (GPIOPeriphID2)@@ offset 0xFE8
|
|
// The GPIOPeriphID0@@
|
|
// GPIOPeriphID1@@ GPIOPeriphID2@@
|
|
// and GPIOPeriphID3 registers can
|
|
// conceptually be treated as one
|
|
// 32-bit register; each register
|
|
// contains eight bits of the 32-bit
|
|
// register@@ used by software to
|
|
// identify the peripheral.
|
|
#define GPIO_O_GPIO_PERIPHID3 0x00000FEC // 0x4000 5FEC 0x4000 6FEC 0x4000
|
|
// 7FEC 0x4002 4FEC GPIO Peripheral
|
|
// Identification 3
|
|
// (GPIOPeriphID3)@@ offset 0xFEC
|
|
// The GPIOPeriphID0@@
|
|
// GPIOPeriphID1@@ GPIOPeriphID2@@
|
|
// and GPIOPeriphID3 registers can
|
|
// conceptually be treated as one
|
|
// 32-bit register; each register
|
|
// contains eight bits of the 32-bit
|
|
// register@@ used by software to
|
|
// identify the peripheral.
|
|
#define GPIO_O_GPIO_PCELLID0 0x00000FF0 // 0x4000 5FF0 0x4000 6FF0 0x4000
|
|
// 7FF0 0x4002 4FF0 GPIO PrimeCell
|
|
// Identification 0 (GPIOPCellID0)@@
|
|
// offset 0xFF0 The GPIOPCellID0@@
|
|
// GPIOPCellID1@@ GPIOPCellID2@@ and
|
|
// GPIOPCellID3 registers are four
|
|
// 8-bit wide registers@@ that can
|
|
// conceptually be treated as one
|
|
// 32-bit register. The register is
|
|
// used as a standard
|
|
// cross-peripheral identification
|
|
// system.
|
|
#define GPIO_O_GPIO_PCELLID1 0x00000FF4 // 0x4000 5FF4 0x4000 6FF4 0x4000
|
|
// 7FF4 0x4002 4FF4 GPIO PrimeCell
|
|
// Identification 1 (GPIOPCellID1)@@
|
|
// offset 0xFF4 The GPIOPCellID0@@
|
|
// GPIOPCellID1@@ GPIOPCellID2@@ and
|
|
// GPIOPCellID3 registers are four
|
|
// 8-bit wide registers@@ that can
|
|
// conceptually be treated as one
|
|
// 32-bit register. The register is
|
|
// used as a standard
|
|
// cross-peripheral identification
|
|
// system.
|
|
#define GPIO_O_GPIO_PCELLID2 0x00000FF8 // 0x4000 5FF8 0x4000 6FF8 0x4000
|
|
// 7FF8 0x4002 4FF8 GPIO PrimeCell
|
|
// Identification 2 (GPIOPCellID2)@@
|
|
// offset 0xFF8 The GPIOPCellID0@@
|
|
// GPIOPCellID1@@ GPIOPCellID2@@ and
|
|
// GPIOPCellID3 registers are four
|
|
// 8-bit wide registers@@ that can
|
|
// conceptually be treated as one
|
|
// 32-bit register. The register is
|
|
// used as a standard
|
|
// cross-peripheral identification
|
|
// system.
|
|
#define GPIO_O_GPIO_PCELLID3 0x00000FFC // 0x4000 5FFC 0x4000 6FFC 0x4000
|
|
// 7FFC 0x4002 4FFC GPIO PrimeCell
|
|
// Identification 3 (GPIOPCellID3)@@
|
|
// offset 0xFFC The GPIOPCellID0@@
|
|
// GPIOPCellID1@@ GPIOPCellID2@@ and
|
|
// GPIOPCellID3 registers are four
|
|
// 8-bit wide registers@@ that can
|
|
// conceptually be treated as one
|
|
// 32-bit register. The register is
|
|
// used as a standard
|
|
// cross-peripheral identification
|
|
// system.0xb1
|
|
|
|
|
|
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_DATA register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_DATA_DATA_M 0x000000FF // GPIO Data This register is
|
|
// virtually mapped to 256 locations
|
|
// in the address space. To
|
|
// facilitate the reading and
|
|
// writing of data to these
|
|
// registers by independent
|
|
// drivers@@ the data read from and
|
|
// written to the registers are
|
|
// masked by the eight address lines
|
|
// [9:2]. Reads from this register
|
|
// return its current state. Writes
|
|
// to this register only affect bits
|
|
// that are not masked by ADDR[9:2]
|
|
// and are configured as outputs.
|
|
#define GPIO_GPIO_DATA_DATA_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_DIR register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_DIR_DIR_M 0x000000FF // GPIO Data Direction Value
|
|
// Description 0 Corresponding pin
|
|
// is an input. 1 Corresponding pins
|
|
// is an output.
|
|
#define GPIO_GPIO_DIR_DIR_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_IS register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_IS_IS_M 0x000000FF // GPIO Interrupt Sense Value
|
|
// Description 0 The edge on the
|
|
// corresponding pin is detected
|
|
// (edge-sensitive). 1 The level on
|
|
// the corresponding pin is detected
|
|
// (level-sensitive).
|
|
#define GPIO_GPIO_IS_IS_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_IBE register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_IBE_IBE_M 0x000000FF // GPIO Interrupt Both Edges Value
|
|
// Description 0 Interrupt
|
|
// generation is controlled by the
|
|
// GPIO Interrupt Event (GPIOIEV)
|
|
// register. 1 Both edges on the
|
|
// corresponding pin trigger an
|
|
// interrupt.
|
|
#define GPIO_GPIO_IBE_IBE_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_IEV register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_IEV_IEV_M 0x000000FF // GPIO Interrupt Event Value
|
|
// Description 1 A falling edge or a
|
|
// Low level on the corresponding
|
|
// pin triggers an interrupt. 0 A
|
|
// rising edge or a High level on
|
|
// the corresponding pin triggers an
|
|
// interrupt.
|
|
#define GPIO_GPIO_IEV_IEV_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_IM register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_IM_IME_M 0x000000FF // GPIO Interrupt Mask Enable Value
|
|
// Description 0 The interrupt from
|
|
// the corresponding pin is masked.
|
|
// 1 The interrupt from the
|
|
// corresponding pin is sent to the
|
|
// interrupt controller.
|
|
#define GPIO_GPIO_IM_IME_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_RIS register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_RIS_RIS_M 0x000000FF // GPIO Interrupt Raw Status Value
|
|
// Description 1 An interrupt
|
|
// condition has occurred on the
|
|
// corresponding pin. 0 interrupt
|
|
// condition has not occurred on the
|
|
// corresponding pin. A bit is
|
|
// cleared by writing a 1 to the
|
|
// corresponding bit in the GPIOICR
|
|
// register.
|
|
#define GPIO_GPIO_RIS_RIS_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_MIS register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_MIS_MIS_M 0x000000FF // GPIO Masked Interrupt Status
|
|
// Value Description 1 An interrupt
|
|
// condition on the corresponding
|
|
// pin has triggered an interrupt to
|
|
// the interrupt controller. 0 An
|
|
// interrupt condition on the
|
|
// corresponding pin is masked or
|
|
// has not occurred. A bit is
|
|
// cleared by writing a 1 to the
|
|
// corresponding bit in the GPIOICR
|
|
// register.
|
|
#define GPIO_GPIO_MIS_MIS_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_ICR register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_ICR_IC_M 0x000000FF // GPIO Interrupt Clear Value
|
|
// Description 1 The corresponding
|
|
// interrupt is cleared. 0 The
|
|
// corresponding interrupt is
|
|
// unaffected.
|
|
#define GPIO_GPIO_ICR_IC_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_AFSEL register.
|
|
//
|
|
//******************************************************************************
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_DR2R register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_DR2R_DRV2_M 0x000000FF // This register is not used in
|
|
// cc3xx. equivalant register exsist
|
|
// outside GPIO IP (refer
|
|
// PAD*_config register in the
|
|
// shared comn space) Output Pad
|
|
// 2-mA Drive Enable Value
|
|
// Description 1 The corresponding
|
|
// GPIO pin has 2-mA drive. The
|
|
// drive for the corresponding GPIO
|
|
// pin is controlled by the GPIODR4R
|
|
// or GPIODR8R register. 0 Setting a
|
|
// bit in either the GPIODR4
|
|
// register or the GPIODR8 register
|
|
// clears the corresponding 2-mA
|
|
// enable bit. The change is
|
|
// effective on the second clock
|
|
// cycle after the write if
|
|
// accessing GPIO via the APB memory
|
|
// aperture. If using AHB access@@
|
|
// the change is effective on the
|
|
// next clock cycle.
|
|
#define GPIO_GPIO_DR2R_DRV2_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_DR4R register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_DR4R_DRV4_M 0x000000FF // This register is not used in
|
|
// cc3xx. equivalant register exsist
|
|
// outside GPIO IP (refer
|
|
// PAD*_config register in the
|
|
// shared comn space) Output Pad
|
|
// 4-mA Drive Enable Value
|
|
// Description 1 The corresponding
|
|
// GPIO pin has 4-mA drive. The
|
|
// drive for the corresponding GPIO
|
|
// pin is controlled by the GPIODR2R
|
|
// or GPIODR8R register. 0 Setting a
|
|
// bit in either the GPIODR2
|
|
// register or the GPIODR8 register
|
|
// clears the corresponding 4-mA
|
|
// enable bit. The change is
|
|
// effective on the second clock
|
|
// cycle after the write if
|
|
// accessing GPIO via the APB memory
|
|
// aperture. If using AHB access@@
|
|
// the change is effective on the
|
|
// next clock cycle.
|
|
#define GPIO_GPIO_DR4R_DRV4_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_DR8R register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_DR8R_DRV8_M 0x000000FF // This register is not used in
|
|
// cc3xx. equivalant register exsist
|
|
// outside GPIO IP (refer
|
|
// PAD*_config register in the
|
|
// shared comn space) Output Pad
|
|
// 8-mA Drive Enable Value
|
|
// Description 1 The corresponding
|
|
// GPIO pin has 8-mA drive. The
|
|
// drive for the corresponding GPIO
|
|
// pin is controlled by the GPIODR2R
|
|
// or GPIODR4R register. 0 Setting a
|
|
// bit in either the GPIODR2
|
|
// register or the GPIODR4 register
|
|
// clears the corresponding 8-mA
|
|
// enable bit. The change is
|
|
// effective on the second clock
|
|
// cycle after the write if
|
|
// accessing GPIO via the APB memory
|
|
// aperture. If using AHB access@@
|
|
// the change is effective on the
|
|
// next clock cycle.
|
|
#define GPIO_GPIO_DR8R_DRV8_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_ODR register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_ODR_ODE_M 0x000000FF // This register is not used in
|
|
// cc3xx. equivalant register exsist
|
|
// outside GPIO IP (refer
|
|
// PAD*_config register in the
|
|
// shared comn space) Output Pad
|
|
// Open Drain Enable Value
|
|
// Description 1 The corresponding
|
|
// pin is configured as open drain.
|
|
// 0 The corresponding pin is not
|
|
// configured as open drain.
|
|
#define GPIO_GPIO_ODR_ODE_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_PUR register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_PUR_PUE_M 0x000000FF // This register is not used in
|
|
// cc3xx. equivalant register exsist
|
|
// outside GPIO IP (refer
|
|
// PAD*_config register in the
|
|
// shared comn space) Pad Weak
|
|
// Pull-Up Enable Value Description
|
|
// 1 The corresponding pin has a
|
|
// weak pull-up resistor. 0 The
|
|
// corresponding pin is not
|
|
// affected. Setting a bit in the
|
|
// GPIOPDR register clears the
|
|
// corresponding bit in the GPIOPUR
|
|
// register. The change is effective
|
|
// on the second clock cycle after
|
|
// the write if accessing GPIO via
|
|
// the APB memory aperture. If using
|
|
// AHB access@@ the change is
|
|
// effective on the next clock
|
|
// cycle.
|
|
#define GPIO_GPIO_PUR_PUE_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_PDR register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_PDR_PDE_M 0x000000FF // This register is not used in
|
|
// cc3xx. equivalant register exsist
|
|
// outside GPIO IP (refer
|
|
// PAD*_config register in the
|
|
// shared comn space) Pad Weak
|
|
// Pull-Down Enable Value
|
|
// Description 1 The corresponding
|
|
// pin has a weak pull-down
|
|
// resistor. 0 The corresponding pin
|
|
// is not affected. Setting a bit in
|
|
// the GPIOPUR register clears the
|
|
// corresponding bit in the GPIOPDR
|
|
// register. The change is effective
|
|
// on the second clock cycle after
|
|
// the write if accessing GPIO via
|
|
// the APB memory aperture. If using
|
|
// AHB access@@ the change is
|
|
// effective on the next clock
|
|
// cycle.
|
|
#define GPIO_GPIO_PDR_PDE_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_SLR register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_SLR_SRL_M 0x000000FF // This register is not used in
|
|
// cc3xx. equivalant register exsist
|
|
// outside GPIO IP (refer
|
|
// PAD*_config register in the
|
|
// shared comn space) Slew Rate
|
|
// Limit Enable (8-mA drive only)
|
|
// Value Description 1 Slew rate
|
|
// control is enabled for the
|
|
// corresponding pin. 0 Slew rate
|
|
// control is disabled for the
|
|
// corresponding pin.
|
|
#define GPIO_GPIO_SLR_SRL_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_DEN register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_DEN_DEN_M 0x000000FF // This register is not used in
|
|
// cc3xx. equivalant register exsist
|
|
// outside GPIO IP (refer
|
|
// PAD*_config register in the
|
|
// shared comn space) Digital Enable
|
|
// Value Description 0 The digital
|
|
// functions for the corresponding
|
|
// pin are disabled. 1 The digital
|
|
// functions for the corresponding
|
|
// pin are enabled.
|
|
#define GPIO_GPIO_DEN_DEN_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_LOCK register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_LOCK_LOCK_M 0xFFFFFFFF // This register is not used in
|
|
// cc3xx. GPIO Lock A write of the
|
|
// value 0x4C4F.434B unlocks the
|
|
// GPIO Commit (GPIOCR) register for
|
|
// write access.A write of any other
|
|
// value or a write to the GPIOCR
|
|
// register reapplies the lock@@
|
|
// preventing any register updates.
|
|
// A read of this register returns
|
|
// the following values: Value
|
|
// Description 0x1 The GPIOCR
|
|
// register is locked and may not be
|
|
// modified. 0x0 The GPIOCR register
|
|
// is unlocked and may be modified.
|
|
#define GPIO_GPIO_LOCK_LOCK_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_CR register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_CR_CR_M 0x000000FF // This register is not used in
|
|
// cc3xx. equivalant register exsist
|
|
// outside GPIO IP (refer
|
|
// PAD*_config register in the
|
|
// shared comn space) GPIO Commit
|
|
// Value Description The
|
|
// corresponding GPIOAFSEL@@
|
|
// GPIOPUR@@ GPIOPDR@@ or GPIODEN
|
|
// bits can be written. 1 The
|
|
// corresponding GPIOAFSEL@@
|
|
// GPIOPUR@@ GPIOPDR@@ or GPIODEN
|
|
// bits cannot be written. 0 Note:
|
|
// The default register type for the
|
|
// GPIOCR register is RO for all
|
|
// GPIO pins with the exception of
|
|
// the NMI pin and the four JTAG/SWD
|
|
// pins (PD7@@ PF0@@ and PC[3:0]).
|
|
// These six pins are the only GPIOs
|
|
// that are protected by the GPIOCR
|
|
// register. Because of this@@ the
|
|
// register type for GPIO Port D7@@
|
|
// GPIO Port F0@@ and GPIO Port
|
|
// C[3:0] is R/W. The default reset
|
|
// value for the GPIOCR register is
|
|
// 0x0000.00FF for all GPIO pins@@
|
|
// with the exception of the NMI pin
|
|
// and the four JTAG/SWD pins (PD7@@
|
|
// PF0@@ and PC[3:0]). To ensure
|
|
// that the JTAG port is not
|
|
// accidentally programmed as GPIO
|
|
// pins@@ the PC[3:0] pins default
|
|
// to non-committable. Similarly@@
|
|
// to ensure that the NMI pin is not
|
|
// accidentally programmed as a GPIO
|
|
// pin@@ the PD7 and PF0 pins
|
|
// default to non-committable.
|
|
// Because of this@@ the default
|
|
// reset value of GPIOCR for GPIO
|
|
// Port C is 0x0000.00F0@@ for GPIO
|
|
// Port D is 0x0000.007F@@ and for
|
|
// GPIO Port F is 0x0000.00FE.
|
|
#define GPIO_GPIO_CR_CR_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_AMSEL register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_AMSEL_GPIO_AMSEL_M \
|
|
0x000000FF // This register is not used in
|
|
// cc3xx. equivalant register exsist
|
|
// outside GPIO IP (refer
|
|
// PAD*_config register in the
|
|
// shared comn space) GPIO Analog
|
|
// Mode Select Value Description 1
|
|
// The analog function of the pin is
|
|
// enabled@@ the isolation is
|
|
// disabled@@ and the pin is capable
|
|
// of analog functions. 0 The analog
|
|
// function of the pin is disabled@@
|
|
// the isolation is enabled@@ and
|
|
// the pin is capable of digital
|
|
// functions as specified by the
|
|
// other GPIO configuration
|
|
// registers. Note: This register
|
|
// and bits are only valid for GPIO
|
|
// signals that share analog
|
|
// function through a unified I/O
|
|
// pad. The reset state of this
|
|
// register is 0 for all signals.
|
|
|
|
#define GPIO_GPIO_AMSEL_GPIO_AMSEL_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_PCTL register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_PCTL_PMC7_M 0xF0000000 // This register is not used in
|
|
// cc3xx. equivalant register exsist
|
|
// outside GPIO IP (refer
|
|
// PAD*_config register in the
|
|
// shared comn space) Port Mux
|
|
// Control 7 This field controls the
|
|
// configuration for GPIO pin 7.
|
|
#define GPIO_GPIO_PCTL_PMC7_S 28
|
|
#define GPIO_GPIO_PCTL_PMC6_M 0x0F000000 // This register is not used in
|
|
// cc3xx. equivalant register exsist
|
|
// outside GPIO IP (refer
|
|
// PAD*_config register in the
|
|
// shared comn space) Port Mux
|
|
// Control 6 This field controls the
|
|
// configuration for GPIO pin 6.
|
|
#define GPIO_GPIO_PCTL_PMC6_S 24
|
|
#define GPIO_GPIO_PCTL_PMC5_M 0x00F00000 // This register is not used in
|
|
// cc3xx. equivalant register exsist
|
|
// outside GPIO IP (refer
|
|
// PAD*_config register in the
|
|
// shared comn space) Port Mux
|
|
// Control 5 This field controls the
|
|
// configuration for GPIO pin 5.
|
|
#define GPIO_GPIO_PCTL_PMC5_S 20
|
|
#define GPIO_GPIO_PCTL_PMC4_M 0x000F0000 // This register is not used in
|
|
// cc3xx. equivalant register exsist
|
|
// outside GPIO IP (refer
|
|
// PAD*_config register in the
|
|
// shared comn space) Port Mux
|
|
// Control 4 This field controls the
|
|
// configuration for GPIO pin 4.
|
|
#define GPIO_GPIO_PCTL_PMC4_S 16
|
|
#define GPIO_GPIO_PCTL_PMC3_M 0x0000F000 // This register is not used in
|
|
// cc3xx. equivalant register exsist
|
|
// outside GPIO IP (refer
|
|
// PAD*_config register in the
|
|
// shared comn space) Port Mux
|
|
// Control 43 This field controls
|
|
// the configuration for GPIO pin 3.
|
|
#define GPIO_GPIO_PCTL_PMC3_S 12
|
|
#define GPIO_GPIO_PCTL_PMC1_M 0x00000F00 // This register is not used in
|
|
// cc3xx. equivalant register exsist
|
|
// outside GPIO IP (refer
|
|
// PAD*_config register in the
|
|
// shared comn space) Port Mux
|
|
// Control 1 This field controls the
|
|
// configuration for GPIO pin 1.
|
|
#define GPIO_GPIO_PCTL_PMC1_S 8
|
|
#define GPIO_GPIO_PCTL_PMC2_M 0x000000F0 // This register is not used in
|
|
// cc3xx. equivalant register exsist
|
|
// outside GPIO IP (refer
|
|
// PAD*_config register in the
|
|
// shared comn space) Port Mux
|
|
// Control 2 This field controls the
|
|
// configuration for GPIO pin 2.
|
|
#define GPIO_GPIO_PCTL_PMC2_S 4
|
|
#define GPIO_GPIO_PCTL_PMC0_M 0x0000000F // This register is not used in
|
|
// cc3xx. equivalant register exsist
|
|
// outside GPIO IP (refer
|
|
// PAD*_config register in the
|
|
// shared comn space) Port Mux
|
|
// Control 0 This field controls the
|
|
// configuration for GPIO pin 0.
|
|
#define GPIO_GPIO_PCTL_PMC0_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the
|
|
// GPIO_O_GPIO_ADCCTL register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_ADCCTL_ADCEN_M \
|
|
0x000000FF // This register is not used in
|
|
// cc3xx. ADC trigger via GPIO is
|
|
// not supported. ADC Trigger Enable
|
|
// Value Description 1 The
|
|
// corresponding pin is used to
|
|
// trigger the ADC. 0 The
|
|
// corresponding pin is not used to
|
|
// trigger the ADC.
|
|
|
|
#define GPIO_GPIO_ADCCTL_ADCEN_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the
|
|
// GPIO_O_GPIO_DMACTL register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_DMACTL_DMAEN_M \
|
|
0x000000FF // This register is not used in the
|
|
// cc3xx. Alternate register to
|
|
// support this feature is coded in
|
|
// the APPS_NWP_CMN space. refer
|
|
// register as offset 0x400F70D8
|
|
// ?DMA Trigger Enable Value
|
|
// Description 1 The corresponding
|
|
// pin is used to trigger the ?DMA.
|
|
// 0 The corresponding pin is not
|
|
// used to trigger the ?DMA.
|
|
|
|
#define GPIO_GPIO_DMACTL_DMAEN_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_GPIO_SI register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_SI_SUM 0x00000001 // Summary Interrupt Value
|
|
// Description 1 Each pin has its
|
|
// own interrupt vector. 0 All port
|
|
// pin interrupts are OR'ed together
|
|
// to produce a summary interrupt.
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the
|
|
// GPIO_O_GPIO_PERIPHID4 register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_PERIPHID4_PID4_M \
|
|
0x000000FF // This register is not used in
|
|
// CC3XX. GPIO Peripheral ID
|
|
// Register [7:0]
|
|
|
|
#define GPIO_GPIO_PERIPHID4_PID4_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the
|
|
// GPIO_O_GPIO_PERIPHID5 register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_PERIPHID5_PID5_M \
|
|
0x000000FF // This register is not used in
|
|
// CC3XX. GPIO Peripheral ID
|
|
// Register [15:8]
|
|
|
|
#define GPIO_GPIO_PERIPHID5_PID5_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the
|
|
// GPIO_O_GPIO_PERIPHID6 register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_PERIPHID6_PID6_M \
|
|
0x000000FF // This register is not used in
|
|
// CC3XX. GPIO Peripheral ID
|
|
// Register [23:16]
|
|
|
|
#define GPIO_GPIO_PERIPHID6_PID6_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the
|
|
// GPIO_O_GPIO_PERIPHID7 register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_PERIPHID7_PID7_M \
|
|
0x000000FF // This register is not used in
|
|
// CC3XX. GPIO Peripheral ID
|
|
// Register [31:24]
|
|
|
|
#define GPIO_GPIO_PERIPHID7_PID7_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the
|
|
// GPIO_O_GPIO_PERIPHID0 register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_PERIPHID0_PID0_M \
|
|
0x000000FF // This register is not used in
|
|
// CC3XX. GPIO Peripheral ID
|
|
// Register [7:0] Can be used by
|
|
// software to identify the presence
|
|
// of this peripheral.
|
|
|
|
#define GPIO_GPIO_PERIPHID0_PID0_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the
|
|
// GPIO_O_GPIO_PERIPHID1 register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_PERIPHID1_PID1_M \
|
|
0x000000FF // GPIO Peripheral ID Register
|
|
// [15:8] Can be used by software to
|
|
// identify the presence of this
|
|
// peripheral.
|
|
|
|
#define GPIO_GPIO_PERIPHID1_PID1_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the
|
|
// GPIO_O_GPIO_PERIPHID2 register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_PERIPHID2_PID2_M \
|
|
0x000000FF // This register is not used in
|
|
// CC3XX.v GPIO Peripheral ID
|
|
// Register [23:16] Can be used by
|
|
// software to identify the presence
|
|
// of this peripheral.
|
|
|
|
#define GPIO_GPIO_PERIPHID2_PID2_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the
|
|
// GPIO_O_GPIO_PERIPHID3 register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_PERIPHID3_PID3_M \
|
|
0x000000FF // This register is not used in
|
|
// CC3XX. GPIO Peripheral ID
|
|
// Register [31:24] Can be used by
|
|
// software to identify the presence
|
|
// of this peripheral.
|
|
|
|
#define GPIO_GPIO_PERIPHID3_PID3_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the
|
|
// GPIO_O_GPIO_PCELLID0 register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_PCELLID0_CID0_M \
|
|
0x000000FF // This register is not used in
|
|
// CC3XX. GPIO PrimeCell ID Register
|
|
// [7:0] Provides software a
|
|
// standard cross-peripheral
|
|
// identification system.
|
|
|
|
#define GPIO_GPIO_PCELLID0_CID0_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the
|
|
// GPIO_O_GPIO_PCELLID1 register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_PCELLID1_CID1_M \
|
|
0x000000FF // This register is not used in
|
|
// CC3XX. GPIO PrimeCell ID Register
|
|
// [15:8] Provides software a
|
|
// standard cross-peripheral
|
|
// identification system.
|
|
|
|
#define GPIO_GPIO_PCELLID1_CID1_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the
|
|
// GPIO_O_GPIO_PCELLID2 register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_PCELLID2_CID2_M \
|
|
0x000000FF // This register is not used in
|
|
// CC3XX. GPIO PrimeCell ID Register
|
|
// [23:16] Provides software a
|
|
// standard cross-peripheral
|
|
// identification system.
|
|
|
|
#define GPIO_GPIO_PCELLID2_CID2_S 0
|
|
//******************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the
|
|
// GPIO_O_GPIO_PCELLID3 register.
|
|
//
|
|
//******************************************************************************
|
|
#define GPIO_GPIO_PCELLID3_CID3_M \
|
|
0x000000FF // This register is not used in
|
|
// CC3XX. GPIO PrimeCell ID Register
|
|
// [31:24] Provides software a
|
|
// standard cross-peripheral
|
|
// identification system.
|
|
|
|
#define GPIO_GPIO_PCELLID3_CID3_S 0
|
|
|
|
|
|
|
|
#endif // __HW_GPIO_H__
|