337 lines
17 KiB
C
337 lines
17 KiB
C
//*****************************************************************************
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//
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// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//*****************************************************************************
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#ifndef __HW_UDMA_H__
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#define __HW_UDMA_H__
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//*****************************************************************************
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//
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// The following are defines for the UDMA register offsets.
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//
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//*****************************************************************************
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#define UDMA_O_STAT 0x00000000
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#define UDMA_O_CFG 0x00000004
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#define UDMA_O_CTLBASE 0x00000008
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#define UDMA_O_ALTBASE 0x0000000C
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#define UDMA_O_WAITSTAT 0x00000010
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#define UDMA_O_SWREQ 0x00000014
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#define UDMA_O_USEBURSTSET 0x00000018
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#define UDMA_O_USEBURSTCLR 0x0000001C
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#define UDMA_O_REQMASKSET 0x00000020
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#define UDMA_O_REQMASKCLR 0x00000024
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#define UDMA_O_ENASET 0x00000028
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#define UDMA_O_ENACLR 0x0000002C
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#define UDMA_O_ALTSET 0x00000030
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#define UDMA_O_ALTCLR 0x00000034
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#define UDMA_O_PRIOSET 0x00000038
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#define UDMA_O_PRIOCLR 0x0000003C
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#define UDMA_O_ERRCLR 0x0000004C
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#define UDMA_O_CHASGN 0x00000500
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#define UDMA_O_CHIS 0x00000504
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#define UDMA_O_CHMAP0 0x00000510
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#define UDMA_O_CHMAP1 0x00000514
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#define UDMA_O_CHMAP2 0x00000518
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#define UDMA_O_CHMAP3 0x0000051C
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#define UDMA_O_PV 0x00000FB0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_STAT register.
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//
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//******************************************************************************
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#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1
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#define UDMA_STAT_DMACHANS_S 16
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#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status
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// 0x00000090 : UDMA_STAT_STATE_DONE
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// : Done 0x00000000 :
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// UDMA_STAT_STATE_IDLE : Idle
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// 0x00000010 :
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// UDMA_STAT_STATE_RD_CTRL : Reading
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// channel controller data
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// 0x00000030 :
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// UDMA_STAT_STATE_RD_DSTENDP :
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// Reading destination end pointer
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// 0x00000040 :
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// UDMA_STAT_STATE_RD_SRCDAT :
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// Reading source data 0x00000020 :
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// UDMA_STAT_STATE_RD_SRCENDP :
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// Reading source end pointer
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// 0x00000080 :
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// UDMA_STAT_STATE_STALL : Stalled
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// 0x000000A0 :
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// UDMA_STAT_STATE_UNDEF : Undefined
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// 0x00000060 : UDMA_STAT_STATE_WAIT
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// : Waiting for uDMA request to
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// clear 0x00000070 :
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// UDMA_STAT_STATE_WR_CTRL : Writing
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// channel controller data
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// 0x00000050 :
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// UDMA_STAT_STATE_WR_DSTDAT :
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// Writing destination data
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#define UDMA_STAT_STATE_S 4
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#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_CFG register.
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//
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//******************************************************************************
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#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_CTLBASE register.
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//
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//******************************************************************************
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#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address
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#define UDMA_CTLBASE_ADDR_S 10
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_ALTBASE register.
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//
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//******************************************************************************
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#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
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// Pointer
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#define UDMA_ALTBASE_ADDR_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_WAITSTAT register.
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//
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//******************************************************************************
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#define UDMA_WAITSTAT_WAITREQ_M \
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0xFFFFFFFF // Channel [n] Wait Status
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#define UDMA_WAITSTAT_WAITREQ_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_SWREQ register.
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//
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//******************************************************************************
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#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request
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#define UDMA_SWREQ_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// UDMA_O_USEBURSTSET register.
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//
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//******************************************************************************
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#define UDMA_USEBURSTSET_SET_M \
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0xFFFFFFFF // Channel [n] Useburst Set
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#define UDMA_USEBURSTSET_SET_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// UDMA_O_USEBURSTCLR register.
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//
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//******************************************************************************
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#define UDMA_USEBURSTCLR_CLR_M \
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0xFFFFFFFF // Channel [n] Useburst Clear
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#define UDMA_USEBURSTCLR_CLR_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_REQMASKSET register.
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//
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//******************************************************************************
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#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set
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#define UDMA_REQMASKSET_SET_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_REQMASKCLR register.
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//
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//******************************************************************************
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#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear
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#define UDMA_REQMASKCLR_CLR_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_ENASET register.
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//
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//******************************************************************************
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#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set
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#define UDMA_ENASET_CHENSET_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_ENACLR register.
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//
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//******************************************************************************
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#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear
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#define UDMA_ENACLR_CLR_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_ALTSET register.
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//
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//******************************************************************************
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#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set
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#define UDMA_ALTSET_SET_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_ALTCLR register.
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//
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//******************************************************************************
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#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear
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#define UDMA_ALTCLR_CLR_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_PRIOSET register.
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//
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//******************************************************************************
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#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set
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#define UDMA_PRIOSET_SET_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_PRIOCLR register.
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//
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//******************************************************************************
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#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear
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#define UDMA_PRIOCLR_CLR_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_ERRCLR register.
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//
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//******************************************************************************
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#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_CHASGN register.
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//
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//******************************************************************************
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#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select
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#define UDMA_CHASGN_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_CHIS register.
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//
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//******************************************************************************
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#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status
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#define UDMA_CHIS_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_CHMAP0 register.
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//
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//******************************************************************************
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#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select
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#define UDMA_CHMAP0_CH7SEL_S 28
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#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select
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#define UDMA_CHMAP0_CH6SEL_S 24
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#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select
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#define UDMA_CHMAP0_CH5SEL_S 20
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#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select
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#define UDMA_CHMAP0_CH4SEL_S 16
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#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select
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#define UDMA_CHMAP0_CH3SEL_S 12
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#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select
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#define UDMA_CHMAP0_CH2SEL_S 8
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#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select
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#define UDMA_CHMAP0_CH1SEL_S 4
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#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select
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#define UDMA_CHMAP0_CH0SEL_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_CHMAP1 register.
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//
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//******************************************************************************
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#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select
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#define UDMA_CHMAP1_CH15SEL_S 28
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#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select
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#define UDMA_CHMAP1_CH14SEL_S 24
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#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select
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#define UDMA_CHMAP1_CH13SEL_S 20
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#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select
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#define UDMA_CHMAP1_CH12SEL_S 16
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#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select
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#define UDMA_CHMAP1_CH11SEL_S 12
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#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select
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#define UDMA_CHMAP1_CH10SEL_S 8
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#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select
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#define UDMA_CHMAP1_CH9SEL_S 4
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#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select
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#define UDMA_CHMAP1_CH8SEL_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_CHMAP2 register.
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//
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//******************************************************************************
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#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select
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#define UDMA_CHMAP2_CH23SEL_S 28
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#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select
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#define UDMA_CHMAP2_CH22SEL_S 24
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#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select
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#define UDMA_CHMAP2_CH21SEL_S 20
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#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select
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#define UDMA_CHMAP2_CH20SEL_S 16
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#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select
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#define UDMA_CHMAP2_CH19SEL_S 12
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#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select
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#define UDMA_CHMAP2_CH18SEL_S 8
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#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select
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#define UDMA_CHMAP2_CH17SEL_S 4
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#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select
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#define UDMA_CHMAP2_CH16SEL_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_CHMAP3 register.
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//
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//******************************************************************************
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#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select
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#define UDMA_CHMAP3_CH31SEL_S 28
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#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select
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#define UDMA_CHMAP3_CH30SEL_S 24
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#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select
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#define UDMA_CHMAP3_CH29SEL_S 20
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#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select
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#define UDMA_CHMAP3_CH28SEL_S 16
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#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select
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#define UDMA_CHMAP3_CH27SEL_S 12
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#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select
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#define UDMA_CHMAP3_CH26SEL_S 8
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#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select
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#define UDMA_CHMAP3_CH25SEL_S 4
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#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select
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#define UDMA_CHMAP3_CH24SEL_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_PV register.
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//
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//******************************************************************************
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#define UDMA_PV_MAJOR_M 0x0000FF00 // Major Revision
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#define UDMA_PV_MAJOR_S 8
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#define UDMA_PV_MINOR_M 0x000000FF // Minor Revision
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#define UDMA_PV_MINOR_S 0
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#endif // __HW_UDMA_H__
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