864 lines
27 KiB
C
864 lines
27 KiB
C
//*****************************************************************************
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//
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// flash.c
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//
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// Driver for programming the on-chip flash.
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//
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// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup flash_api
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//! @{
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//
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//*****************************************************************************
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#include "inc/hw_types.h"
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#include "inc/hw_flash_ctrl.h"
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#include "inc/hw_memmap.h"
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#include "inc/hw_ints.h"
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#include "inc/hw_gprcm.h"
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#include "inc/hw_hib1p2.h"
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#include "inc/hw_hib3p3.h"
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#include "inc/hw_common_reg.h"
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#include "inc/hw_stack_die_ctrl.h"
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#include "debug.h"
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#include "flash.h"
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#include "utils.h"
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#include "interrupt.h"
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#define HAVE_WRITE_BUFFER 1
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//*****************************************************************************
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//
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// An array that maps the specified memory bank to the appropriate Flash
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// Memory Protection Program Enable (FMPPE) register.
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//
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//*****************************************************************************
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static const unsigned long g_pulFMPPERegs[] =
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{
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FLASH_FMPPE0,
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FLASH_FMPPE1,
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FLASH_FMPPE2,
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FLASH_FMPPE3,
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FLASH_FMPPE4,
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FLASH_FMPPE5,
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FLASH_FMPPE6,
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FLASH_FMPPE7,
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FLASH_FMPPE8,
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FLASH_FMPPE9,
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FLASH_FMPPE10,
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FLASH_FMPPE11,
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FLASH_FMPPE12,
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FLASH_FMPPE13,
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FLASH_FMPPE14,
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FLASH_FMPPE15
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};
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//*****************************************************************************
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//
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// An array that maps the specified memory bank to the appropriate Flash
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// Memory Protection Read Enable (FMPRE) register.
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//
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//*****************************************************************************
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static const unsigned long g_pulFMPRERegs[] =
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{
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FLASH_FMPRE0,
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FLASH_FMPRE1,
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FLASH_FMPRE2,
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FLASH_FMPRE3,
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FLASH_FMPRE4,
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FLASH_FMPRE5,
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FLASH_FMPRE6,
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FLASH_FMPRE7,
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FLASH_FMPRE8,
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FLASH_FMPRE9,
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FLASH_FMPRE10,
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FLASH_FMPRE11,
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FLASH_FMPRE12,
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FLASH_FMPRE13,
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FLASH_FMPRE14,
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FLASH_FMPRE15,
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};
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//*****************************************************************************
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//
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//! Flash Disable
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//!
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//! This function Disables the internal Flash.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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FlashDisable()
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{
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//
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// Wait for Flash Busy to get cleared
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//
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while((HWREG(GPRCM_BASE + GPRCM_O_TOP_DIE_ENABLE)
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& GPRCM_TOP_DIE_ENABLE_FLASH_BUSY))
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{
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}
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//
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// Assert reset
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//
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HWREG(HIB1P2_BASE + HIB1P2_O_PORPOL_SPARE) = 0xFFFF0000;
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//
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// 50 usec Delay Loop
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//
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UtilsDelay((50*80)/3);
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//
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// Disable TDFlash
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//
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HWREG(GPRCM_BASE + GPRCM_O_TOP_DIE_ENABLE) = 0x0;
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//
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// 50 usec Delay Loop
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//
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UtilsDelay((50*80)/3);
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HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1;
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//
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// 50 usec Delay Loop
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//
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UtilsDelay((50*80)/3);
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}
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//*****************************************************************************
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//
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//! Erases a block of flash.
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//!
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//! \param ulAddress is the start address of the flash block to be erased.
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//!
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//! This function will erase a 2 kB block of the on-chip flash. After erasing,
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//! the block will be filled with 0xFF bytes. Read-only and execute-only
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//! blocks cannot be erased.
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//!
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//! This function will not return until the block has been erased.
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//!
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//! \return Returns 0 on success, or -1 if an invalid block address was
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//! specified or the block is write-protected.
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//
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//*****************************************************************************
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long
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FlashErase(unsigned long ulAddress)
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{
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//
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// Check the arguments.
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//
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ASSERT(!(ulAddress & (FLASH_CTRL_ERASE_SIZE - 1)));
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//
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// Clear the flash access and error interrupts.
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//
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HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC)
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= (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
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FLASH_CTRL_FCMISC_ERMISC);
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// Erase the block.
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//
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HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress;
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HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC)
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= FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_ERASE;
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//
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// Wait until the block has been erased.
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//
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while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_ERASE)
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{
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}
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//
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// Return an error if an access violation or erase error occurred.
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//
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if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS)
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& (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS |
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FLASH_CTRL_FCRIS_ERRIS))
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{
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return(-1);
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}
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//
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// Success.
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//
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return(0);
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}
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//*****************************************************************************
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//
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//! Erases a block of flash but does not wait for completion.
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//!
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//! \param ulAddress is the start address of the flash block to be erased.
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//!
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//! This function will erase a 2 kB block of the on-chip flash. After erasing,
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//! the block will be filled with 0xFF bytes. Read-only and execute-only
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//! blocks cannot be erased.
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//!
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//! This function will return immediately after commanding the erase operation.
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//! Applications making use of the function can determine completion state by
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//! using a flash interrupt handler or by polling FlashIntStatus.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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FlashEraseNonBlocking(unsigned long ulAddress)
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{
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//
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// Check the arguments.
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//
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ASSERT(!(ulAddress & (FLASH_CTRL_ERASE_SIZE - 1)));
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//
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// Clear the flash access and error interrupts.
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//
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HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) =
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(FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
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FLASH_CTRL_FCMISC_ERMISC);
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//
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// Command the flash controller to erase the block.
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//
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HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress;
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HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_ERASE;
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}
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//*****************************************************************************
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//
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//! Erases a complele flash at shot.
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//!
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//! This function erases a complele flash at shot
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//!
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//! \return Returns 0 on success, or -1 if the block is write-protected.
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//
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//*****************************************************************************
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long
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FlashMassErase()
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{
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//
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// Clear the flash access and error interrupts.
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//
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HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) =
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(FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
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FLASH_CTRL_FCMISC_ERMISC);
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//
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// Command the flash controller for mass erase.
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//
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HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) =
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FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_MERASE1;
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//
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// Wait until mass erase completes.
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//
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while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_MERASE1)
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{
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}
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//
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// Return an error if an access violation or erase error occurred.
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//
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if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS)
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& (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS |
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FLASH_CTRL_FCRIS_ERRIS))
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{
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return -1;
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}
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//
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// Success.
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//
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return 0;
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}
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//*****************************************************************************
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//
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//! Erases a complele flash at shot but does not wait for completion.
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//!
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//!
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//! This function will not return until the Flash has been erased.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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FlashMassEraseNonBlocking()
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{
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//
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// Clear the flash access and error interrupts.
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//
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HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) =
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(FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
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FLASH_CTRL_FCMISC_ERMISC);
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//
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// Command the flash controller for mass erase.
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//
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HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) =
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FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_MERASE1;
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}
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//*****************************************************************************
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//
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//! Programs flash.
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//!
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//! \param pulData is a pointer to the data to be programmed.
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//! \param ulAddress is the starting address in flash to be programmed. Must
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//! be a multiple of four.
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//! \param ulCount is the number of bytes to be programmed. Must be a multiple
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//! of four.
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//!
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//! This function will program a sequence of words into the on-chip flash.
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//! Each word in a page of flash can only be programmed one time between an
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//! erase of that page; programming a word multiple times will result in an
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//! unpredictable value in that word of flash.
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//!
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//! Since the flash is programmed one word at a time, the starting address and
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//! byte count must both be multiples of four. It is up to the caller to
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//! verify the programmed contents, if such verification is required.
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//!
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//! This function will not return until the data has been programmed.
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//!
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//! \return Returns 0 on success, or -1 if a programming error is encountered.
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//
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//*****************************************************************************
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long
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FlashProgram(unsigned long *pulData, unsigned long ulAddress,
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unsigned long ulCount)
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{
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//
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// Check the arguments.
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//
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ASSERT(!(ulAddress & 3));
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ASSERT(!(ulCount & 3));
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//
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// Clear the flash access and error interrupts.
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//
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HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC)
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= (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
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FLASH_CTRL_FCMISC_INVDMISC | FLASH_CTRL_FCMISC_PROGMISC);
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//
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// See if this device has a write buffer.
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//
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#if HAVE_WRITE_BUFFER
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{
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//
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// Loop over the words to be programmed.
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//
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while(ulCount)
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{
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//
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// Set the address of this block of words. for 1 MB
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//
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HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress & ~(0x7F);
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//
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// Loop over the words in this 32-word block.
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//
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while(((ulAddress & 0x7C) ||
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(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBVAL) == 0)) &&
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(ulCount != 0))
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{
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//
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// Write this word into the write buffer.
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//
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HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBN
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+ (ulAddress & 0x7C)) = *pulData++;
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ulAddress += 4;
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ulCount -= 4;
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}
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//
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// Program the contents of the write buffer into flash.
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//
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HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2)
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= FLASH_CTRL_FMC2_WRKEY | FLASH_CTRL_FMC2_WRBUF;
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//
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// Wait until the write buffer has been programmed.
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//
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while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) & FLASH_CTRL_FMC2_WRBUF)
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{
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}
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}
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}
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#else
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{
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//
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// Loop over the words to be programmed.
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//
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while(ulCount)
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{
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//
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// Program the next word.
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//
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HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress;
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HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMD) = *pulData;
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HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_WRITE;
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//
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// Wait until the word has been programmed.
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//
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while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_WRITE)
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{
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}
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//
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// Increment to the next word.
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//
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pulData++;
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ulAddress += 4;
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ulCount -= 4;
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}
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}
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#endif
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//
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// Return an error if an access violation occurred.
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//
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if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS) & (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS |
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FLASH_CTRL_FCRIS_INVDRIS | FLASH_CTRL_FCRIS_PROGRIS))
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{
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return(-1);
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}
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//
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// Success.
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//
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return(0);
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}
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//*****************************************************************************
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//
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//! Programs flash but does not poll for completion.
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//!
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//! \param pulData is a pointer to the data to be programmed.
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//! \param ulAddress is the starting address in flash to be programmed. Must
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//! be a multiple of four.
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//! \param ulCount is the number of bytes to be programmed. Must be a multiple
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//! of four.
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//!
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//! This function will start programming one or more words into the on-chip
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//! flash and return immediately. The number of words that can be programmed
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//! in a single call depends the part on which the function is running. For
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//! parts without support for a flash write buffer, only a single word may be
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//! programmed on each call to this function (\e ulCount must be 1). If a
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//! write buffer is present, up to 32 words may be programmed on condition
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//! that the block being programmed does not straddle a 32 word address
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//! boundary. For example, wherease 32 words can be programmed if the address
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//! passed is 0x100 (a multiple of 128 bytes or 32 words), only 31 words could
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//! be programmed at 0x104 since attempting to write 32 would cross the 32
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//! word boundary at 0x180.
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//!
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//! Since the flash is programmed one word at a time, the starting address and
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//! byte count must both be multiples of four. It is up to the caller to
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//! verify the programmed contents, if such verification is required.
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//!
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//! This function will return immediately after commanding the erase operation.
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//! Applications making use of the function can determine completion state by
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//! using a flash interrupt handler or by polling FlashIntStatus.
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//!
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//! \return 0 if the write was started successfully, -1 if there was an error.
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//
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//*****************************************************************************
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long
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FlashProgramNonBlocking(unsigned long *pulData, unsigned long ulAddress,
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unsigned long ulCount)
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{
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//
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// Check the arguments.
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//
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ASSERT(!(ulAddress & 3));
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ASSERT(!(ulCount & 3));
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//
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// Clear the flash access and error interrupts.
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//
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HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC)
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= (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
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FLASH_CTRL_FCMISC_INVDMISC | FLASH_CTRL_FCMISC_PROGMISC);
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//
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// See if this device has a write buffer.
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//
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#if HAVE_WRITE_BUFFER
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{
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//
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// Make sure the address/count specified doesn't straddle a 32 word
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// boundary.
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//
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if(((ulAddress + (ulCount - 1)) & ~0x7F) != (ulAddress & ~0x7F))
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{
|
|
return(-1);
|
|
}
|
|
|
|
//
|
|
// Loop over the words to be programmed.
|
|
//
|
|
while(ulCount)
|
|
{
|
|
//
|
|
// Set the address of this block of words.
|
|
//
|
|
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress & ~(0x7F);
|
|
|
|
//
|
|
// Loop over the words in this 32-word block.
|
|
//
|
|
while(((ulAddress & 0x7C) || (HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBVAL) == 0)) &&
|
|
(ulCount != 0))
|
|
{
|
|
//
|
|
// Write this word into the write buffer.
|
|
//
|
|
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBN + (ulAddress & 0x7C)) = *pulData++;
|
|
ulAddress += 4;
|
|
ulCount -= 4;
|
|
}
|
|
|
|
//
|
|
// Program the contents of the write buffer into flash.
|
|
//
|
|
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) = FLASH_CTRL_FMC2_WRKEY | FLASH_CTRL_FMC2_WRBUF;
|
|
}
|
|
}
|
|
#else
|
|
{
|
|
//
|
|
// We don't have a write buffer so we can only write a single word.
|
|
//
|
|
if(ulCount > 1)
|
|
{
|
|
return(-1);
|
|
}
|
|
|
|
//
|
|
// Write a single word.
|
|
//
|
|
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress;
|
|
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMD) = *pulData;
|
|
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_WRITE;
|
|
}
|
|
#endif
|
|
//
|
|
// Success.
|
|
//
|
|
return(0);
|
|
}
|
|
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the protection setting for a block of flash.
|
|
//!
|
|
//! \param ulAddress is the start address of the flash block to be queried.
|
|
//!
|
|
//! This function gets the current protection for the specified 2-kB block
|
|
//! of flash. Each block can be read/write, read-only, or execute-only.
|
|
//! Read/write blocks can be read, executed, erased, and programmed. Read-only
|
|
//! blocks can be read and executed. Execute-only blocks can only be executed;
|
|
//! processor and debugger data reads are not allowed.
|
|
//!
|
|
//! \return Returns the protection setting for this block. See
|
|
//! FlashProtectSet() for possible values.
|
|
//
|
|
//*****************************************************************************
|
|
tFlashProtection
|
|
FlashProtectGet(unsigned long ulAddress)
|
|
{
|
|
unsigned long ulFMPRE, ulFMPPE;
|
|
unsigned long ulBank;
|
|
|
|
//
|
|
// Check the argument.
|
|
//
|
|
ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
|
|
|
|
//
|
|
// Calculate the Flash Bank from Base Address, and mask off the Bank
|
|
// from ulAddress for subsequent reference.
|
|
//
|
|
ulBank = (((ulAddress / FLASH_PROTECT_SIZE) / 32) % 16);
|
|
ulAddress &= ((FLASH_PROTECT_SIZE * 32) - 1);
|
|
|
|
//
|
|
// Read the appropriate flash protection registers for the specified
|
|
// flash bank.
|
|
//
|
|
ulFMPRE = HWREG(g_pulFMPRERegs[ulBank]);
|
|
ulFMPPE = HWREG(g_pulFMPPERegs[ulBank]);
|
|
|
|
//
|
|
// Check the appropriate protection bits for the block of memory that
|
|
// is specified by the address.
|
|
//
|
|
switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) &
|
|
FLASH_FMP_BLOCK_0) << 1) |
|
|
((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0))
|
|
{
|
|
//
|
|
// This block is marked as execute only (that is, it can not be erased
|
|
// or programmed, and the only reads allowed are via the instruction
|
|
// fetch interface).
|
|
//
|
|
case 0:
|
|
case 1:
|
|
{
|
|
return(FlashExecuteOnly);
|
|
}
|
|
|
|
//
|
|
// This block is marked as read only (that is, it can not be erased or
|
|
// programmed).
|
|
//
|
|
case 2:
|
|
{
|
|
return(FlashReadOnly);
|
|
}
|
|
|
|
//
|
|
// This block is read/write; it can be read, erased, and programmed.
|
|
//
|
|
case 3:
|
|
default:
|
|
{
|
|
return(FlashReadWrite);
|
|
}
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Registers an interrupt handler for the flash interrupt.
|
|
//!
|
|
//! \param pfnHandler is a pointer to the function to be called when the flash
|
|
//! interrupt occurs.
|
|
//!
|
|
//! This sets the handler to be called when the flash interrupt occurs. The
|
|
//! flash controller can generate an interrupt when an invalid flash access
|
|
//! occurs, such as trying to program or erase a read-only block, or trying to
|
|
//! read from an execute-only block. It can also generate an interrupt when a
|
|
//! program or erase operation has completed. The interrupt will be
|
|
//! automatically enabled when the handler is registered.
|
|
//!
|
|
//! \sa IntRegister() for important information about registering interrupt
|
|
//! handlers.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
FlashIntRegister(void (*pfnHandler)(void))
|
|
{
|
|
//
|
|
// Register the interrupt handler, returning an error if an error occurs.
|
|
//
|
|
IntRegister(INT_FLASH, pfnHandler);
|
|
|
|
//
|
|
// Enable the flash interrupt.
|
|
//
|
|
IntEnable(INT_FLASH);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Unregisters the interrupt handler for the flash interrupt.
|
|
//!
|
|
//! This function will clear the handler to be called when the flash interrupt
|
|
//! occurs. This will also mask off the interrupt in the interrupt controller
|
|
//! so that the interrupt handler is no longer called.
|
|
//!
|
|
//! \sa IntRegister() for important information about registering interrupt
|
|
//! handlers.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
FlashIntUnregister(void)
|
|
{
|
|
//
|
|
// Disable the interrupt.
|
|
//
|
|
IntDisable(INT_FLASH);
|
|
|
|
//
|
|
// Unregister the interrupt handler.
|
|
//
|
|
IntUnregister(INT_FLASH);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enables individual flash controller interrupt sources.
|
|
//!
|
|
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
|
|
//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_ACCESS values.
|
|
//!
|
|
//! Enables the indicated flash controller interrupt sources. Only the sources
|
|
//! that are enabled can be reflected to the processor interrupt; disabled
|
|
//! sources have no effect on the processor.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
FlashIntEnable(unsigned long ulIntFlags)
|
|
{
|
|
//
|
|
// Enable the specified interrupts.
|
|
//
|
|
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCIM) |= ulIntFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disables individual flash controller interrupt sources.
|
|
//!
|
|
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
|
|
//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_ACCESS values.
|
|
//!
|
|
//! Disables the indicated flash controller interrupt sources. Only the
|
|
//! sources that are enabled can be reflected to the processor interrupt;
|
|
//! disabled sources have no effect on the processor.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
FlashIntDisable(unsigned long ulIntFlags)
|
|
{
|
|
//
|
|
// Disable the specified interrupts.
|
|
//
|
|
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCIM) &= ~(ulIntFlags);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the current interrupt status.
|
|
//!
|
|
//! \param bMasked is false if the raw interrupt status is required and true if
|
|
//! the masked interrupt status is required.
|
|
//!
|
|
//! This returns the interrupt status for the flash controller. Either the raw
|
|
//! interrupt status or the status of interrupts that are allowed to reflect to
|
|
//! the processor can be returned.
|
|
//!
|
|
//! \return The current interrupt status, enumerated as a bit field of
|
|
//! \b FLASH_CTRL_PROGRAM and \b FLASH_CTRL_ACCESS.
|
|
//
|
|
//*****************************************************************************
|
|
unsigned long
|
|
FlashIntStatus(tBoolean bMasked)
|
|
{
|
|
//
|
|
// Return either the interrupt status or the raw interrupt status as
|
|
// requested.
|
|
//
|
|
if(bMasked)
|
|
{
|
|
return(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC));
|
|
}
|
|
else
|
|
{
|
|
return(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS));
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Clears flash controller interrupt sources.
|
|
//!
|
|
//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
|
|
//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_AMISC values.
|
|
//!
|
|
//! The specified flash controller interrupt sources are cleared, so that they
|
|
//! no longer assert. This must be done in the interrupt handler to keep it
|
|
//! from being called again immediately upon exit.
|
|
//!
|
|
//! \note Because there is a write buffer in the Cortex-M3 processor, it may
|
|
//! take several clock cycles before the interrupt source is actually cleared.
|
|
//! Therefore, it is recommended that the interrupt source be cleared early in
|
|
//! the interrupt handler (as opposed to the very last action) to avoid
|
|
//! returning from the interrupt handler before the interrupt source is
|
|
//! actually cleared. Failure to do so may result in the interrupt handler
|
|
//! being immediately reentered (because the interrupt controller still sees
|
|
//! the interrupt source asserted).
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
FlashIntClear(unsigned long ulIntFlags)
|
|
{
|
|
//
|
|
// Clear the flash interrupt.
|
|
//
|
|
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = ulIntFlags;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Close the Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|