Initial commit

Signed-off-by: Thomas Klaehn <thomas.klaehn@perinet.io>

lp-core/Cargo.toml

@@ -0,0 +1,45 @@
+[package]
+name         = "lp-core"
+version      = "0.1.0"
+edition      = "2021"
+rust-version = "1.84.0"
+description  = "Firmware for esp32-c6's low power core"
+keywords     = ["embedded", "embedded-hal", "esp32", "espressif", "hal"]
+categories   = ["embedded", "hardware-support", "no-std"]
+license      = "MIT OR Apache-2.0"
+
+[dependencies]
+cfg-if            = "1.0.0"
+document-features = "0.2.10"
+esp-lp-hal        = { version = "0.1.0", features = ["esp32c6"] }
+embedded-hal      = { version = "1.0.0" }
+embedded-hal-nb   = { version = "1.0.0",  optional = true }
+embedded-io       = { version = "0.6.1",  optional = true }
+esp32c6-lp        = { version = "0.3.0", features = ["critical-section"], optional = true }
+nb                = { version = "1.1.0",  optional = true }
+procmacros        = { version = "0.16.0", package = "esp-hal-procmacros" }
+riscv             = { version = "0.11.1", features = ["critical-section-single-hart"] }
+panic-halt = "0.2.0"
+
+[build-dependencies]
+esp-build = { version = "0.2.0" }
+
+[features]
+default = ["esp32c6"]
+
+## Enable debug features in the HAL (used for development).
+debug = [
+    "esp32c6-lp?/impl-register-debug",
+]
+
+# Chip Support Feature Flags
+# Target the ESP32-C6.
+esp32c6 = ["dep:esp32c6-lp",  "procmacros/is-lp-core", "dep:nb"]
+# embedded-hal = ["dep:embedded-hal"]
+
+#! ### Trait Implementation Feature Flags
+## Implement the traits defined in the `1.0.0` releases of `embedded-hal` and
+## `embedded-hal-nb` for the relevant peripherals.
+# embedded-hal = ["dep:embedded-hal", "dep:embedded-hal-nb"]
+## Implement the traits defined in `embedded-io` for the relevant peripherals.
+# embedded-io = ["dep:embedded-io"]

lp-core/build.rs

@@ -0,0 +1,27 @@
+use std::error::Error;
+
+use esp_build::assert_unique_used_features;
+
+fn main() -> Result<(), Box<dyn Error>> {
+    assert_unique_used_features!("esp32c6");
+
+    // NOTE: update when adding new device support!
+    // Determine the name of the configured device:
+    let device_name =  "esp32c6";
+
+    // Define all necessary configuration symbols for the configured device:
+    println!("cargo:rustc-cfg={}", device_name);
+
+    // Put the linker script somewhere the linker can find it:
+    // let out = PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    // println!("cargo:rustc-link-search={}", out.display());
+
+    // Copy the required linker script to the `out` directory:
+    // fs::copy("lp-core/ld/link.x", out.join("link.x"))?;
+    // println!("cargo:rerun-if-changed=lp-core/ld/link.x");
+
+    println!("cargo:rustc-link-arg=-Tlp-core/ld/link.x");
+
+    // // Done!
+    Ok(())
+}

lp-core/ld/link.x

@@ -0,0 +1,67 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ENTRY(reset_vector)
+
+VECTOR_TABLE_LENGTH = 0x80;
+CONFIG_ULP_COPROC_RESERVE_MEM = 1024 * 16;
+CONFIG_ULP_SHARED_MEM = 0;
+RAM_LENGTH = CONFIG_ULP_COPROC_RESERVE_MEM - VECTOR_TABLE_LENGTH - CONFIG_ULP_SHARED_MEM;
+
+MEMORY
+{
+    /*first 128byte for exception/interrupt vectors*/
+    vector_table(RX)  : ORIGIN = 0x50000000, LENGTH = VECTOR_TABLE_LENGTH
+             ram(RWX) : ORIGIN = 0x50000080, LENGTH = RAM_LENGTH
+}
+
+SECTIONS
+{
+    .vector.text :
+    {
+        /* Exception/interrupt vectors */
+        __mtvec_base = .;
+        KEEP (*(.init.vector))
+        __mtvec_end = .;
+    } > vector_table
+
+    . = ORIGIN(ram);
+
+    .text ALIGN(4):
+    {
+        *(.text.vectors) /* Default reset vector must link to offset 0x80 */
+        
+        KEEP(*(.init));
+        KEEP(*(.init.rust));        
+        *(.text)
+        *(.text*)
+    } > ram
+
+    .rodata ALIGN(4):
+    {
+        *(.rodata)
+        *(.rodata*)
+    } > ram
+
+    .data ALIGN(4):
+    {
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+    } > ram
+
+    .bss ALIGN(4) :
+    {
+        *(.bss)
+        *(.bss*)
+        *(.sbss)
+        *(.sbss*)
+        PROVIDE(end = .);
+    } > ram
+
+    __stack_top = ORIGIN(ram) + LENGTH(ram);
+}

lp-core/src/main.rs

@@ -0,0 +1,35 @@
+//! Counts a 32 bit value at a known point in memory, and blink GPIO1.
+//!
+//! When using the ESP32-C6's LP core, this address in memory is `0x5000_2000`.
+//!
+//! Make sure the LP RAM is cleared before loading the code.
+
+#![no_std]
+#![no_main]
+
+use embedded_hal::{delay::DelayNs, digital::OutputPin};
+use esp_lp_hal::{delay::Delay, gpio::Output, prelude::*};
+use panic_halt as _;
+
+const ADDRESS: u32 = 0x5000_2000;
+
+
+#[entry]
+fn main(mut gpio1: Output<1>) -> ! {
+    let mut i: u32 = 0;
+
+    let ptr = ADDRESS as *mut u32;
+
+    loop {
+        i = i.wrapping_add(1u32);
+        unsafe {
+            ptr.write_volatile(i);
+        }
+
+        gpio1.set_high().unwrap();
+        Delay.delay_ms(500);
+
+        gpio1.set_low().unwrap();
+        Delay.delay_ms(500);
+    }
+}