tkl/stm32g0xx
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code refactoring

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This commit is contained in:
Thomas Klaehn
2021-01-08 11:58:59 +01:00
parent 3c65600e31
commit 38095715e9
57 changed files with 238 additions and 58077 deletions
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8
Core/delay.h Normal file
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@@ -0,0 +1,8 @@
#ifndef __CORE_DELAY_H__
#define __CORE_DELAY_H__
#include <stdint.h>
void delay_ms(uint32_t);
#endif

101
Core/main.cc
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@@ -1,18 +1,12 @@
#include <string.h>
#include <stdint.h>
#include <stdio.h>
#include <stdbool.h>
#include "main.h"
#include <cstring>
#include <cstdint>
#include <cstdio>
#include "delay.h"
#include "platform/stm32g0xx/Gpio.h"
#include "platform/stm32g0xx/Uart.h"
#include "platform/stm32g0xx/IndependentWatchdog.h"
static void SystemClock_Config(void);
#define SYS_TICK_PRIO 0
// NOTE! The independent watchdog is clocked by a separate clock. this one
// isn't controlled by JTAG. That's why the independent watchdog needs to
// be disabled during JTAG debug sessions.
@@ -30,24 +24,6 @@ IndependentWatchdog watchdog(4095, 4095);
int main(void)
{
unsigned int i = 1, j = 40;
SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
SysTick_Config(SystemCoreClock / 1000U); // 1kHz
NVIC_SetPriority(SysTick_IRQn, SYS_TICK_PRIO);
SET_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN);
/* Delay after an RCC peripheral clock enabling */
READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN);
SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN);
/* Delay after an RCC peripheral clock enabling */
READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN);
/* Change strobe configuration of GPIO depending on UCPDx dead battery settings */
MODIFY_REG(SYSCFG->CFGR1, (SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE), SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE);
SystemClock_Config();
char tx_buf[80];
#ifndef JTAG_DEBUG
@@ -70,7 +46,7 @@ int main(void)
sprintf(tx_buf, "%u: Hello World\r\n", i++);
uart.sync_send((const uint8_t *)tx_buf, strlen(tx_buf));
green_led.toggle();
HAL_Delay(j);
delay_ms(j);
#ifndef JTAG_DEBUG
watchdog.trigger();
@@ -78,73 +54,6 @@ int main(void)
}
}
void SystemClock_Config(void)
{
/* Modify voltage scaling range */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
/* Wait until VOSF is reset */
while(HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF));
/* HSI clock config */
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, RCC_HSICALIBRATION_DEFAULT << RCC_ICSCR_HSITRIM_Pos);
/* Adjust the HSI16 division factor */
MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, RCC_HSI_DIV1);
/* Update the SystemCoreClock global variable with HSISYS value */
SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
/* Adapt Systick interrupt period */
SysTick_Config(SystemCoreClock / 1000U); // 1kHz
NVIC_SetPriority(SysTick_IRQn, SYS_TICK_PRIO);
/* LSI config */
/* Disable the Internal Low Speed oscillator (LSI). */
CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
/* Wait till LSI is disabled */
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U);
/* PLL config */
/* Disable the main PLL. */
CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U);
/* Configure the main PLL clock source, multiplication and division factors. */
MODIFY_REG(RCC->PLLCFGR, (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR),
(RCC_PLLSOURCE_HSI | RCC_PLLM_DIV1 | (8 << RCC_PLLCFGR_PLLN_Pos) | RCC_PLLP_DIV2 | RCC_PLLQ_DIV2 | RCC_PLLR_DIV2));
/* Enable the main PLL. */
SET_BIT(RCC->CR, RCC_CR_PLLON);
/* Enable PLLR Clock output. */
SET_BIT(RCC->PLLCFGR, RCC_PLLRCLK);
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U);
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, FLASH_LATENCY_2);
/* Check that the new number of wait states is taken into account to access the Flash
memory by polling the FLASH_ACR register */
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLASH_LATENCY_2);
/* HCLK config */
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
/* Set the new HCLK clock divider */
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
/* SYSCLK config */
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_SYSCLKSOURCE_PLLCLK);
while ((RCC->CFGR & RCC_CFGR_SWS) != (RCC_SYSCLKSOURCE_PLLCLK << RCC_CFGR_SWS_Pos));
/* PCLK1 Configuration */
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV1);
/* TODO: Update the SystemCoreClock global variable */
SystemCoreClock = 64000000;
/* Configure the USART2 clock source */
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, RCC_USART2CLKSOURCE_PCLK1);
}
#ifdef USE_FULL_ASSERT
void assert_failed(uint8_t *file, uint32_t line)
{

83
Core/main.h
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@@ -1,83 +0,0 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.h
* @brief : Header for main.c file.
* This file contains the common defines of the application.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H
#define __MAIN_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g0xx_hal.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
#define MCO_Pin GPIO_PIN_0
#define MCO_GPIO_Port GPIOF
#define USART2_TX_Pin GPIO_PIN_2
#define USART2_TX_GPIO_Port GPIOA
#define USART2_RX_Pin GPIO_PIN_3
#define USART2_RX_GPIO_Port GPIOA
#define LED_GREEN_Pin GPIO_PIN_5
#define LED_GREEN_GPIO_Port GPIOA
#define TMS_Pin GPIO_PIN_13
#define TMS_GPIO_Port GPIOA
#define TCK_Pin GPIO_PIN_14
#define TCK_GPIO_Port GPIOA
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

16
Core/print.c
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@@ -1,16 +0,0 @@
#include <stdint.h>
#include "main.h"
#ifdef __GNUC__
#define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
#else
#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
#endif /* __GNUC__ */
extern UART_HandleTypeDef huart2;
int __io_putchar(int ch)
{
HAL_UART_Transmit(&huart2, (uint8_t *)&ch, 1, 0xFFFF);
return ch;
}