vscode: Adapt launch configuration

.vscode/launch.json

@@ -1,34 +1,24 @@
 {
-    // Use IntelliSense to learn about possible attributes.
-    // Hover to view descriptions of existing attributes.
-    // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
     "version": "0.2.0",
     "configurations": [
         {
             "name": "gdb Launch Debug",
             "type": "cppdbg",
             "request": "launch",
+            "args": [],
             "program": "${workspaceFolder}/_build/firmware.elf",
-            "args": [
-                "-d","${workspaceFolder}/Core/Src",
-                "-d","${workspaceFolder}/Core/Startup",
-                "-d","${workspaceFolder}/Core/Drivers",
-                ],
             "stopAtEntry": true,
             "cwd": "${workspaceRoot}",
             "environment": [],
             "externalConsole": false,
             "MIMode": "gdb",
-            "miDebuggerPath": "/usr/bin/arm-none-eabi-gdb",
+            "miDebuggerPath": "arm-none-eabi-gdb",
             "debugServerPath": "openocd",
-            "debugServerArgs": "-f /usr/local/share/openocd/scripts/interface/stlink.cfg -f /usr/local/share/openocd/scripts/target/stm32g0x.cfg",
+            "debugServerArgs": "-f ${workspaceRoot}/openocd.cfg",
             "serverLaunchTimeout": 20000,
             "filterStderr": true,
             "filterStdout": false,
             "serverStarted": "Info : Listening on port 3333 for gdb connections",
-            // "sourceFileMap": {
-            //     "/work/":"${workspaceFolder}"
-            // },
             "sourceFileMap": {
                 "${workspaceRoot}":"${workspaceFolder}"
             },
@@ -62,6 +52,6 @@
                     "ignoreFailures": false
                 }
             ]
-        },
+        }
     ]
 }

.vscode/tasks.json

@@ -2,9 +2,8 @@
     "version": "2.0.0",
     "options": {
         "env": {
-            // "APPLICATION": "blinky",
-            // "APPLICATION": "spi",
-            // "APPLICATION": "st7789_lcd",
+            "SOC": "stm32g031",
+            // "SOC": "stm32g071",
         },
     },
     "presentation": {
@@ -31,23 +30,6 @@
                 "isDefault": true
             }
         },
-        {
-            "label": "flash",
-            "type":"shell",
-            "command": "make flash",
-            "problemMatcher": {
-                "base": "$gcc",
-                "owner": "gcc",
-                "fileLocation": [
-                    "relative",
-                    "${workspaceFolder}"
-                ]
-            },
-            "group": {
-                "kind": "build",
-                "isDefault": true
-            }
-        },
         {
             "label": "clean",
             "type":"shell",
@@ -64,40 +46,6 @@
                 "kind": "build",
                 "isDefault": true
             }
-        },
-        {
-            "label": "distclean",
-            "type":"shell",
-            "command": "make distclean",
-            "problemMatcher": {
-                "base": "$gcc",
-                "owner": "gcc",
-                "fileLocation": [
-                    "relative",
-                    "${workspaceFolder}"
-                ]
-            },
-            "group": {
-                "kind": "build",
-                "isDefault": true
-            }
-        },
-        {
-            "label": "check",
-            "type":"shell",
-            "command": "make check",
-            "problemMatcher": {
-                "base": "$gcc",
-                "owner": "gcc",
-                "fileLocation": [
-                    "relative",
-                    "${workspaceFolder}"
-                ]
-            },
-            "group": {
-                "kind": "build",
-                "isDefault": true
-            }
         }
     ]
 }

Core/main.cc

@@ -5,59 +5,25 @@
 #include "delay.h"
 #include "platform/stm32g0xx/Gpio.h"
 #include "platform/stm32g0xx/Uart.h"
-#include "platform/stm32g0xx/IndependentWatchdog.h"
 
-// NOTE! The independent watchdog is clocked by a separate clock. this one
-//       isn't controlled by JTAG. That's why the independent watchdog needs to
-//       be disabled during JTAG debug sessions.
-#define JTAG_DEBUG
 
 using namespace perinet::platform::stm32g0xx;
 
-Gpio green_led(Gpio::Port::PORT_A, 5, Gpio::Mode::MODE_OUTPUT_PP);
-Uart uart(Uart::UartDevice::UART_2, 115200);
-
-#ifndef JTAG_DEBUG
-IndependentWatchdog watchdog(4095, 4095);
-#endif
+Uart uart1(Uart::UartDevice::UART_1, 115200);
+Uart uart2(Uart::UartDevice::UART_2, 115200);
 
 int main(void)
 {
-    unsigned int i = 1, j = 40;
-    char tx_buf[80];
+    char tx_buf[] = "\r\rProgram: UART bridge\r\n\n Receive on uart2 and transmit it on uart 1\r\n";
+    uint8_t rec;
+        uart1.sync_send((const uint8_t *)tx_buf, strlen(tx_buf));
 
-#ifndef JTAG_DEBUG
-    watchdog.enable();
-#endif
-
-    while (1) {
-        if (j < 100) {
-            j += 10;
+    while(true) {
+        if(uart2.sync_receive(&rec)) {
+            uart1.sync_send(&rec, 1);
         }
-        else if (j < 200) {
-            j += 20;
-        }
-        else if (j < 400) {
-            j += 40;
-        }
-        if (j > 800) {
-            j = 800;
-        }
-        sprintf(tx_buf, "%u: Hello World\r\n", i++);
-        uart.sync_send((const uint8_t *)tx_buf, strlen(tx_buf));
-        green_led.toggle();
-        delay_ms(j);
-
-#ifndef JTAG_DEBUG
-        watchdog.trigger();
-#endif
+        if(uart1.sync_receive(&rec)) {
+            uart2.sync_send(&rec, 1);
         }
     }
-
-#ifdef  USE_FULL_ASSERT
-void assert_failed(uint8_t *file, uint32_t line)
-{
-    /* User can add his own implementation to report the file name and line number,
-       ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
 }
-#endif /* USE_FULL_ASSERT */

Makefile

@@ -17,9 +17,6 @@ platform/stm32g0xx/system_stm32g0xx.c \
 platform/stm32g0xx/syscalls.c \
 platform/stm32g0xx/sysmem.c \
 
-ASM_SOURCES = \
-platform/stm32g0xx/startup_stm32g071rbtx.s
-
 PREFIX = arm-none-eabi-
 CC = $(PREFIX)gcc
 CXX = $(PREFIX)g++
@@ -33,8 +30,21 @@ BIN = $(CP) -O binary -S
 CPU = -mcpu=cortex-m0plus
 MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
 
-C_DEFS = \
--DSTM32G071xx
+ifeq "$(SOC)" "stm32g071"
+
+C_DEFS = -DSTM32G071xx
+LDSCRIPT = platform/stm32g0xx/STM32G071RBTX_FLASH.ld
+ASM_SOURCES = platform/stm32g0xx/startup_stm32g071rbtx.s
+
+else
+ifeq "$(SOC)" "stm32g031"
+
+C_DEFS = -DSTM32G031xx
+LDSCRIPT = platform/stm32g0xx/STM32G031Y8YX_FLASH.ld
+ASM_SOURCES = platform/stm32g0xx/startup_stm32g031y8yx.s
+
+endif
+endif
 
 C_INCLUDES = \
 -I. \
@@ -52,8 +62,6 @@ endif
 
 CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
 
-LDSCRIPT = platform/stm32g0xx/STM32G071RBTX_FLASH.ld
-
 LIBS = -lc -lm -lnosys
 LIBDIR =
 LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
@@ -78,7 +86,7 @@ $(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR)
 $(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)
 	$(AS) -c $(CFLAGS) $< -o $@
 
-$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile
+$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) | Makefile
 	$(CXX) $(OBJECTS) $(LDFLAGS) -o $@
 	$(SZ) $@
 

openocd.cfg

@@ -0,0 +1,2 @@
+source [find interface/stlink.cfg]
+source [find target/stm32g0x.cfg]

platform/stm32g0xx/Gpio.h

@@ -3,7 +3,7 @@
 
 #include <cstdint>
 
-#include "stm32g071xx.h"
+#include "stm32g0xx.h"
 
 namespace perinet::platform::stm32g0xx {
 

platform/stm32g0xx/STM32G031Y8YX_FLASH.ld

@@ -0,0 +1,177 @@
+/**
+ ******************************************************************************
+ * @file      LinkerScript.ld
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     Linker script for STM32G031Y8Yx Device from STM32G0 series
+ *                      64Kbytes FLASH
+ *                      8Kbytes RAM
+ *
+ *            Set heap size, stack size and stack location according
+ *            to application requirements.
+ *
+ *            Set memory bank area and size if external memory is used
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ;	/* required amount of heap  */
+_Min_Stack_Size = 0x400 ;	/* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 8K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 64K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

platform/stm32g0xx/Uart.cc

@@ -6,47 +6,41 @@ using namespace perinet::platform::stm32g0xx;
 Uart::Uart(UartDevice device, uint32_t baud_rate)
 {
     uint32_t tx_pin = 2;
-    uint32_t rx_pin = 3;
+    uint32_t rx_pin = 15;
     Gpio::Port port = Gpio::Port::PORT_A;
+    Gpio::AlternateFunction alt_func = Gpio::AlternateFunction::ALTERNATE_FUNCTION_0;
     switch(device) {
+        case UartDevice::UART_1:
+            uart = USART1;
+            RCC->APBENR2 |= RCC_APBENR2_USART1EN;
+            tx_pin = 6;
+            rx_pin = 7;
+            port = Gpio::Port::PORT_B;
+            break;
+
         case UartDevice::UART_2:
-            this->uart = USART2;
+            uart = USART2;
             RCC->APBENR1 |= RCC_APBENR1_USART2EN;
-            break;
-
-        case UartDevice::UART_3:
-            this->uart = USART3;
-            RCC->APBENR1 |= RCC_APBENR1_USART3EN;
-
-            // FIXME: Set pin confing accordingly
-            break;
-
-        case UartDevice::UART_4:
-            this->uart = USART4;
-            RCC->APBENR1 |= RCC_APBENR1_USART4EN;
-
-            // FIXME: Set pin confing accordingly
+            alt_func = Gpio::AlternateFunction::ALTERNATE_FUNCTION_1;
             break;
     }
 
-    Gpio tx_gpio(port, tx_pin, Gpio::Mode::MODE_AF_PP, Gpio::Pullup::PULLUP,
-                 Gpio::AlternateFunction::ALTERNATE_FUNCTION_1);
-    Gpio rx_gpio(port, rx_pin, Gpio::Mode::MODE_AF_PP, Gpio::Pullup::PULLUP,
-                 Gpio::AlternateFunction::ALTERNATE_FUNCTION_1);
+    Gpio tx_gpio(port, tx_pin, Gpio::Mode::MODE_AF_PP, Gpio::Pullup::PULLUP, alt_func);
+    Gpio rx_gpio(port, rx_pin, Gpio::Mode::MODE_AF_PP, Gpio::Pullup::PULLUP, alt_func);
 
     // Disable UART
-    this->uart->CR1 &= ~USART_CR1_UE;
+    uart->CR1 &= ~USART_CR1_UE;
 
     // USART CR1 Configuration
-    uint32_t tmp = this->uart->CR1;
+    uint32_t tmp = uart->CR1;
     tmp &= ~((USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| USART_CR1_FIFOEN));
     tmp |= (USART_CR1_TE | USART_CR1_RE);  // RX and TX mode
-    this->uart->CR1 = tmp;
+    uart->CR1 = tmp;
 
     // USART CR2 Configuration
-    tmp = this->uart->CR2;
+    tmp = uart->CR2;
     tmp &= ~(USART_CR2_STOP);
-    this->uart->CR2 = tmp;
+    uart->CR2 = tmp;
 
     // USART CR3 Configuration
 
@@ -54,16 +48,16 @@ Uart::Uart(UartDevice device, uint32_t baud_rate)
 
     // USART BRR Configuration
     tmp = ((64000000 + (baud_rate / 2)) / baud_rate);
-    this->uart->BRR = tmp;
+    uart->BRR = tmp;
 
     // In asynchronous mode, the following bits must be kept cleared:
     //   - LINEN and CLKEN bits in the USART_CR2 register,
     //   - SCEN, HDSEL and IREN  bits in the USART_CR3 register.
-    this->uart->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
-    this->uart->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+    uart->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
+    uart->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
 
     // Enable UART
-    this->uart->CR1 |= USART_CR1_UE;
+    uart->CR1 |= USART_CR1_UE;
 }
 
 void Uart::sync_send(const uint8_t *buffer, uint32_t len)
@@ -74,7 +68,17 @@ void Uart::sync_send(const uint8_t *buffer, uint32_t len)
 
     for (uint32_t i = 0; i < len; i++) {
         // wait for tx not full
-        while ((this->uart->ISR & USART_ISR_TXE_TXFNF) == 0);
-        this->uart->TDR = buffer[i];
+        while ((uart->ISR & USART_ISR_TXE_TXFNF) == 0);
+        uart->TDR = buffer[i];
     }
 }
+
+bool Uart::sync_receive(uint8_t* res)
+{
+        if((uart->ISR & USART_ISR_RXNE_RXFNE) == 0) {
+            return false;
+        }
+
+        *res = (uint8_t)(uart->RDR);
+        return true;
+}

platform/stm32g0xx/Uart.h

@@ -12,13 +12,13 @@ class Uart
 public:
     enum class UartDevice
     {
-        UART_2,
-        UART_3,
-        UART_4
+        UART_1,
+        UART_2
     };
 
     Uart(UartDevice, uint32_t);
     void sync_send(const uint8_t *, uint32_t);
+    bool sync_receive(uint8_t*);
 
 private:
     USART_TypeDef   * uart;

platform/stm32g0xx/startup_stm32g031y8yx.s

@@ -0,0 +1,289 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32g031xx.s
+  * @author    MCD Application Team
+  * @brief     STM32G031xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M0+ processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+.syntax unified
+.cpu cortex-m0plus
+.fpu softvfp
+.thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval None
+*/
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+  bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application s entry point.*/
+  bl main
+
+LoopForever:
+  b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+  .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+  .word NMI_Handler
+  .word HardFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word 0
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler                   /* Window WatchDog              */
+  .word PVD_IRQHandler                    /* PVD through EXTI Line detect */
+  .word RTC_TAMP_IRQHandler               /* RTC through the EXTI line    */
+  .word FLASH_IRQHandler                  /* FLASH                        */
+  .word RCC_IRQHandler                    /* RCC                          */
+  .word EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
+  .word EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
+  .word EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
+  .word 0                                 /* reserved                     */
+  .word DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
+  .word DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
+  .word DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 5, DMAMUX1 overrun */
+  .word ADC1_IRQHandler                   /* ADC1                        */
+  .word TIM1_BRK_UP_TRG_COM_IRQHandler    /* TIM1 Break, Update, Trigger and Commutation */
+  .word TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
+  .word TIM2_IRQHandler                   /* TIM2                         */
+  .word TIM3_IRQHandler                   /* TIM3                         */
+  .word LPTIM1_IRQHandler                 /* LPTIM1                       */
+  .word LPTIM2_IRQHandler                 /* LPTIM2                       */
+  .word TIM14_IRQHandler                  /* TIM14                        */
+  .word 0                                 /* reserved                     */
+  .word TIM16_IRQHandler                  /* TIM16                        */
+  .word TIM17_IRQHandler                  /* TIM17                        */
+  .word I2C1_IRQHandler                   /* I2C1                         */
+  .word I2C2_IRQHandler                   /* I2C2                         */
+  .word SPI1_IRQHandler                   /* SPI1                         */
+  .word SPI2_IRQHandler                   /* SPI2                         */
+  .word USART1_IRQHandler                 /* USART1                       */
+  .word USART2_IRQHandler                 /* USART2                       */
+  .word LPUART1_IRQHandler                /* LPUART1                      */
+  .word 0                                 /* reserved                     */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak      NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak      HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak      SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak      PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak      SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak      WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak      PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak      RTC_TAMP_IRQHandler
+  .thumb_set RTC_TAMP_IRQHandler,Default_Handler
+
+  .weak      FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak      RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak      EXTI0_1_IRQHandler
+  .thumb_set EXTI0_1_IRQHandler,Default_Handler
+
+  .weak      EXTI2_3_IRQHandler
+  .thumb_set EXTI2_3_IRQHandler,Default_Handler
+
+  .weak      EXTI4_15_IRQHandler
+  .thumb_set EXTI4_15_IRQHandler,Default_Handler
+
+  .weak      DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak      DMA1_Channel2_3_IRQHandler
+  .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
+
+  .weak      DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler
+  .thumb_set DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler,Default_Handler
+
+  .weak      ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak      TIM1_BRK_UP_TRG_COM_IRQHandler
+  .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
+
+  .weak      TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak      TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak      TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak      LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+  .weak      LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+  .weak      TIM14_IRQHandler
+  .thumb_set TIM14_IRQHandler,Default_Handler
+
+  .weak      TIM16_IRQHandler
+  .thumb_set TIM16_IRQHandler,Default_Handler
+
+  .weak      TIM17_IRQHandler
+  .thumb_set TIM17_IRQHandler,Default_Handler
+
+  .weak      I2C1_IRQHandler
+  .thumb_set I2C1_IRQHandler,Default_Handler
+
+  .weak      I2C2_IRQHandler
+  .thumb_set I2C2_IRQHandler,Default_Handler
+
+  .weak      SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak      SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak      USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak      USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak      LPUART1_IRQHandler
+  .thumb_set LPUART1_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

platform/stm32g0xx/system_stm32g0xx.c

@@ -115,7 +115,6 @@ void SystemClock_Config(void)
     SysTick_Config(SystemCoreClock / 1000U);    // 1kHz
     NVIC_SetPriority(SysTick_IRQn, SYS_TICK_PRIO);
 
-
     /* LSI config */
     /* Disable the Internal Low Speed oscillator (LSI). */
     RCC->CSR &= ~(RCC_CSR_LSION);
@@ -178,12 +177,17 @@ void SystemClock_Config(void)
     tmp &= ~(RCC_CFGR_PPRE);    // HCLK not divided
     RCC->CFGR = tmp;
 
+    /* Adapt Systick interrupt period */
     SystemCoreClock = 64000000;
+    SysTick_Config(SystemCoreClock / 1000U);    // 1kHz
+    NVIC_SetPriority(SysTick_IRQn, SYS_TICK_PRIO);
 
+#ifdef STM32G071xx
     /* Configure the USART2 clock source */
     tmp = RCC->CCIPR;
     tmp &= ~(RCC_CCIPR_USART2SEL);  // APB clock selected as USART2 clock
     RCC->CCIPR = tmp;
+#endif
 }
 
 void SystemInit(void)
@@ -201,11 +205,13 @@ void SystemInit(void)
     RCC->APBENR2 |= RCC_APBENR2_SYSCFGEN;
     RCC->APBENR1 |= RCC_APBENR1_PWREN;
 
+#ifdef STM32G071xx
     /* Change strobe configuration of GPIO depending on UCPDx dead battery settings */
     uint32_t tmp = SYSCFG->CFGR1;
     tmp &= ~(SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE);
     tmp |= (SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE);
     SYSCFG->CFGR1 = tmp;
+#endif
 
     SystemClock_Config();
 }