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6 Commits

Author SHA1 Message Date
Thomas Klaehn
d509688167 vscode: Add devcontainer
Signed-off-by: Thomas Klaehn <thomas.klaehn@perinet.io>
2025-02-01 09:29:56 +01:00
Thomas Klaehn
f94eeb5ffe Code reorganization 2022-12-15 10:18:35 +01:00
Thomas Klaehn
1eee0af374 vscode: Adapt launch configuration 2022-11-16 10:02:47 +01:00
Thomas Klaehn
103cbe1d6a Implement uart bridge application 2021-06-09 13:34:48 +02:00
Thomas Klaehn
46382e2cf7 Adapt launch config to periCORE3 dev board 2021-06-09 13:33:43 +02:00
Thomas Klaehn
4ff7ad8748 Port to srm32g031 2021-05-28 11:06:00 +02:00
49 changed files with 8079 additions and 9379 deletions

38
.devcontainer/Dockerfile Normal file
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@@ -0,0 +1,38 @@
FROM debian:stable-slim
LABEL maintainer="thomas.klaehn@perinet.io"
# Enable contrip section for "repo"
# RUN sed -i -e 's/.main$/ main contrib/' /etc/apt/sources.list
RUN export DEBIAN_FRONTEND=noninteractive && apt-get update && apt-get -y install --no-install-recommends \
binutils-arm-none-eabi \
gcc-arm-none-eabi \
gdb-multiarch \
git \
libstdc++-arm-none-eabi-dev \
libstdc++-arm-none-eabi-newlib \
make \
openocd
# Set UTF8 locale settings
# RUN apt-get install -yq locales && \
# locale-gen en_US.UTF-8 && \
# sed -i -e 's/# en_US.UTF-8 UTF-8/en_US.UTF-8 UTF-8/' /etc/locale.gen && \
# dpkg-reconfigure --frontend=noninteractive locales && \
# update-locale LANG=en_US.UTF-8
# ENV LANG en_US.UTF-8
# RUN useradd -ms /bin/bash builder
# RUN echo "builder:builder" | chpasswd
# ADD init.sh /usr/local/bin/init.sh
# WORKDIR = /work
# ENTRYPOINT ["/usr/local/bin/init.sh"]
RUN mkdir /workspaces
VOLUME /workspaces
WORKDIR /workspaces/
CMD ["/bin/bash"]

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@@ -0,0 +1,48 @@
// For format details, see https://aka.ms/devcontainer.json. For config options, see the
// README at: https://github.com/devcontainers/templates/tree/main/src/typescript-node
{
"name": "arm-none-eabi-cpp",
// Or use a Dockerfile or Docker Compose file. More info: https://containers.dev/guide/dockerfile
"build": { "dockerfile": "Dockerfile" },
// Privileged container in order to access /dev
"privileged": true,
// Mount USB devices (debug probes, UART interfaces, ...)
"mounts": [
"source=/dev/bus/usb/,target=/dev/bus/usb/,type=bind"
],
// Features to add to the dev container. More info: https://containers.dev/features.
// "features": {},
// Use 'forwardPorts' to make a list of ports inside the container available locally.
// "forwardPorts": [],
// Use 'postCreateCommand' to run commands after the container is created.
// "postCreateCommand": "sudo apt update && sudo apt install -y openocd && sudo apt install -y gdb-multiarch",
// Configure tool-specific properties.
"customizations": {
"vscode": {
"extensions": [
"ms-vscode.cpptools",
"ms-vscode.cpptools-extension-pack",
"marus25.cortex-debug",
"zoma.vscode-auto-open-workspace"
],
// default settings, can be overwritten in .vscode/settings.conf
"settings": {
"terminal.integrated.defaultProfile.linux.shell": "/bin/bash",
"autoOpenWorkspace.enableAutoOpenIfSingleWorkspace": true,
"autoOpenWorkspace.enableAutoOpenAlwaysFirst": true,
"files.exclude": {
"**/.git": true,
"**/.repo": true
}
}
}
}
// Uncomment to connect as root instead. More info: https://aka.ms/dev-containers-non-root.
// "remoteUser": "root"
}

2
.gitignore vendored
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@@ -1 +1 @@
_build/ build/

26
.vscode/launch.json vendored
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@@ -1,34 +1,24 @@
{ {
// Use IntelliSense to learn about possible attributes.
// Hover to view descriptions of existing attributes.
// For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
"version": "0.2.0", "version": "0.2.0",
"configurations": [ "configurations": [
{ {
"name": "gdb Launch Debug", "name": "gdb Launch Debug",
"type": "cppdbg", "type": "cppdbg",
"request": "launch", "request": "launch",
"program": "${workspaceFolder}/_build/firmware.elf", "args": [],
"args": [ "program": "${workspaceFolder}/build/firmware.elf",
"-d","${workspaceFolder}/Core/Src",
"-d","${workspaceFolder}/Core/Startup",
"-d","${workspaceFolder}/Core/Drivers",
],
"stopAtEntry": true, "stopAtEntry": true,
"cwd": "${workspaceRoot}", "cwd": "${workspaceRoot}",
"environment": [], "environment": [],
"externalConsole": false, "externalConsole": false,
"MIMode": "gdb", "MIMode": "gdb",
"miDebuggerPath": "/usr/bin/arm-none-eabi-gdb", "miDebuggerPath": "gdb-multiarch",
"debugServerPath": "openocd", "debugServerPath": "openocd",
"debugServerArgs": "-f /usr/local/share/openocd/scripts/interface/stlink.cfg -f /usr/local/share/openocd/scripts/target/stm32g0x.cfg", "debugServerArgs": "-f ${workspaceRoot}/openocd.cfg",
"serverLaunchTimeout": 20000, "serverLaunchTimeout": 20000,
"filterStderr": true, "filterStderr": true,
"filterStdout": false, "filterStdout": false,
"serverStarted": "Info : Listening on port 3333 for gdb connections", "serverStarted": "Info : Listening on port 3333 for gdb connections",
// "sourceFileMap": {
// "/work/":"${workspaceFolder}"
// },
"sourceFileMap": { "sourceFileMap": {
"${workspaceRoot}":"${workspaceFolder}" "${workspaceRoot}":"${workspaceFolder}"
}, },
@@ -53,7 +43,7 @@
}, },
{ {
"description": "Load executable into debugger.", "description": "Load executable into debugger.",
"text": "file ${workspaceFolder}/_build/firmware.elf", "text": "file ${workspaceFolder}/build/firmware.elf",
"ignoreFailures": false "ignoreFailures": false
}, },
{ {
@@ -61,7 +51,7 @@
"text": "load", "text": "load",
"ignoreFailures": false "ignoreFailures": false
} }
] ]
}, }
] ]
} }

56
.vscode/tasks.json vendored
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@@ -2,9 +2,8 @@
"version": "2.0.0", "version": "2.0.0",
"options": { "options": {
"env": { "env": {
// "APPLICATION": "blinky", "SOC": "stm32g031",
// "APPLICATION": "spi", // "SOC": "stm32g071",
// "APPLICATION": "st7789_lcd",
}, },
}, },
"presentation": { "presentation": {
@@ -31,23 +30,6 @@
"isDefault": true "isDefault": true
} }
}, },
{
"label": "flash",
"type":"shell",
"command": "make flash",
"problemMatcher": {
"base": "$gcc",
"owner": "gcc",
"fileLocation": [
"relative",
"${workspaceFolder}"
]
},
"group": {
"kind": "build",
"isDefault": true
}
},
{ {
"label": "clean", "label": "clean",
"type":"shell", "type":"shell",
@@ -64,40 +46,6 @@
"kind": "build", "kind": "build",
"isDefault": true "isDefault": true
} }
},
{
"label": "distclean",
"type":"shell",
"command": "make distclean",
"problemMatcher": {
"base": "$gcc",
"owner": "gcc",
"fileLocation": [
"relative",
"${workspaceFolder}"
]
},
"group": {
"kind": "build",
"isDefault": true
}
},
{
"label": "check",
"type":"shell",
"command": "make check",
"problemMatcher": {
"base": "$gcc",
"owner": "gcc",
"fileLocation": [
"relative",
"${workspaceFolder}"
]
},
"group": {
"kind": "build",
"isDefault": true
}
} }
] ]
} }

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@@ -1,63 +0,0 @@
#include <cstring>
#include <cstdint>
#include <cstdio>
#include "delay.h"
#include "platform/stm32g0xx/Gpio.h"
#include "platform/stm32g0xx/Uart.h"
#include "platform/stm32g0xx/IndependentWatchdog.h"
// NOTE! The independent watchdog is clocked by a separate clock. this one
// isn't controlled by JTAG. That's why the independent watchdog needs to
// be disabled during JTAG debug sessions.
#define JTAG_DEBUG
using namespace perinet::platform::stm32g0xx;
Gpio green_led(Gpio::Port::PORT_A, 5, Gpio::Mode::MODE_OUTPUT_PP);
Uart uart(Uart::UartDevice::UART_2, 115200);
#ifndef JTAG_DEBUG
IndependentWatchdog watchdog(4095, 4095);
#endif
int main(void)
{
unsigned int i = 1, j = 40;
char tx_buf[80];
#ifndef JTAG_DEBUG
watchdog.enable();
#endif
while (1) {
if (j < 100) {
j += 10;
}
else if (j < 200) {
j += 20;
}
else if (j < 400) {
j += 40;
}
if (j > 800) {
j = 800;
}
sprintf(tx_buf, "%u: Hello World\r\n", i++);
uart.sync_send((const uint8_t *)tx_buf, strlen(tx_buf));
green_led.toggle();
delay_ms(j);
#ifndef JTAG_DEBUG
watchdog.trigger();
#endif
}
}
#ifdef USE_FULL_ASSERT
void assert_failed(uint8_t *file, uint32_t line)
{
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
}
#endif /* USE_FULL_ASSERT */

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@@ -3,22 +3,12 @@ TARGET = firmware
DEBUG = 1 DEBUG = 1
OPT = -O0 OPT = -O0
BUILD_DIR = _build BUILD_DIR = build
CC_SOURCES = \ SRC_DIRS := $(shell find src -type d)
Core/main.cc \ CC_SOURCES = $(foreach folder, $(SRC_DIRS), $(wildcard $(folder)/*.cc))
platform/stm32g0xx/Gpio.cc \ C_SOURCES = $(foreach folder, $(SRC_DIRS), $(wildcard $(folder)/*.c))
platform/stm32g0xx/Uart.cc \ ASM_SOURCES = $(foreach folder, $(SRC_DIRS), $(wildcard $(folder)/*.s))
platform/stm32g0xx/IndependentWatchdog.cc \
platform/stm32g0xx/low_level_interrupt.cc
C_SOURCES = \
platform/stm32g0xx/system_stm32g0xx.c \
platform/stm32g0xx/syscalls.c \
platform/stm32g0xx/sysmem.c \
ASM_SOURCES = \
platform/stm32g0xx/startup_stm32g071rbtx.s
PREFIX = arm-none-eabi- PREFIX = arm-none-eabi-
CC = $(PREFIX)gcc CC = $(PREFIX)gcc
@@ -33,18 +23,11 @@ BIN = $(CP) -O binary -S
CPU = -mcpu=cortex-m0plus CPU = -mcpu=cortex-m0plus
MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
C_DEFS = \ C_DEFS = -DSTM32G031xx
-DSTM32G071xx LDSCRIPT = src/platform/stm32g0xx/STM32G031Y8YX_FLASH.ld
C_INCLUDES = \
-I. \
-ICore \
-Iarch/CMSIS/Device/ST/STM32G0xx/Include \
-Iarch/CMSIS/Include \
-Iplatform/stm32g0xx
ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections CFLAGS = $(MCU) $(C_DEFS) $(addprefix -I,$(SRC_DIRS)) $(OPT) -Wall -fdata-sections -ffunction-sections
ifeq ($(DEBUG), 1) ifeq ($(DEBUG), 1)
CFLAGS += -ggdb3 CFLAGS += -ggdb3
@@ -52,8 +35,6 @@ endif
CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
LDSCRIPT = platform/stm32g0xx/STM32G071RBTX_FLASH.ld
LIBS = -lc -lm -lnosys LIBS = -lc -lm -lnosys
LIBDIR = LIBDIR =
LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
@@ -78,7 +59,7 @@ $(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR)
$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR) $(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)
$(AS) -c $(CFLAGS) $< -o $@ $(AS) -c $(CFLAGS) $< -o $@
$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile $(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) | Makefile
$(CXX) $(OBJECTS) $(LDFLAGS) -o $@ $(CXX) $(OBJECTS) $(LDFLAGS) -o $@
$(SZ) $@ $(SZ) $@

2
openocd.cfg Normal file
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@@ -0,0 +1,2 @@
source [find interface/stlink.cfg]
source [find target/stm32g0x.cfg]

29
src/main.cc Normal file
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@@ -0,0 +1,29 @@
#include <cstring>
#include <cstdint>
#include <cstdio>
#include "delay.h"
#include "platform/stm32g0xx/Gpio.h"
#include "platform/stm32g0xx/Uart.h"
using namespace perinet::platform::stm32g0xx;
Uart uart1(Uart::UartDevice::UART_1, 115200);
Uart uart2(Uart::UartDevice::UART_2, 115200);
int main(void)
{
char tx_buf[] = "\r\rProgram: UART bridge\r\n\n Receive on uart2 and transmit it on uart 1\r\n";
uint8_t rec;
uart1.sync_send((const uint8_t *)tx_buf, strlen(tx_buf));
while(true) {
if(uart2.sync_receive(&rec)) {
uart1.sync_send(&rec, 1);
}
if(uart1.sync_receive(&rec)) {
uart2.sync_send(&rec, 1);
}
}
}

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@@ -3,7 +3,7 @@
#include <cstdint> #include <cstdint>
#include "stm32g071xx.h" #include "stm32g0xx.h"
namespace perinet::platform::stm32g0xx { namespace perinet::platform::stm32g0xx {

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@@ -2,9 +2,9 @@
****************************************************************************** ******************************************************************************
* @file LinkerScript.ld * @file LinkerScript.ld
* @author Auto-generated by STM32CubeIDE * @author Auto-generated by STM32CubeIDE
* Abstract : Linker script for NUCLEO-G071RB Board embedding STM32G071RBTx Device from stm32g0 series * @brief Linker script for STM32G031Y8Yx Device from STM32G0 series
* 128Kbytes FLASH * 64Kbytes FLASH
* 36Kbytes RAM * 8Kbytes RAM
* *
* Set heap size, stack size and stack location according * Set heap size, stack size and stack location according
* to application requirements. * to application requirements.
@@ -36,8 +36,8 @@ _Min_Stack_Size = 0x400 ; /* required amount of stack */
/* Memories definition */ /* Memories definition */
MEMORY MEMORY
{ {
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 36K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8K
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K
} }
/* Sections */ /* Sections */

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@@ -6,47 +6,41 @@ using namespace perinet::platform::stm32g0xx;
Uart::Uart(UartDevice device, uint32_t baud_rate) Uart::Uart(UartDevice device, uint32_t baud_rate)
{ {
uint32_t tx_pin = 2; uint32_t tx_pin = 2;
uint32_t rx_pin = 3; uint32_t rx_pin = 15;
Gpio::Port port = Gpio::Port::PORT_A; Gpio::Port port = Gpio::Port::PORT_A;
Gpio::AlternateFunction alt_func = Gpio::AlternateFunction::ALTERNATE_FUNCTION_0;
switch(device) { switch(device) {
case UartDevice::UART_1:
uart = USART1;
RCC->APBENR2 |= RCC_APBENR2_USART1EN;
tx_pin = 6;
rx_pin = 7;
port = Gpio::Port::PORT_B;
break;
case UartDevice::UART_2: case UartDevice::UART_2:
this->uart = USART2; uart = USART2;
RCC->APBENR1 |= RCC_APBENR1_USART2EN; RCC->APBENR1 |= RCC_APBENR1_USART2EN;
break; alt_func = Gpio::AlternateFunction::ALTERNATE_FUNCTION_1;
case UartDevice::UART_3:
this->uart = USART3;
RCC->APBENR1 |= RCC_APBENR1_USART3EN;
// FIXME: Set pin confing accordingly
break;
case UartDevice::UART_4:
this->uart = USART4;
RCC->APBENR1 |= RCC_APBENR1_USART4EN;
// FIXME: Set pin confing accordingly
break; break;
} }
Gpio tx_gpio(port, tx_pin, Gpio::Mode::MODE_AF_PP, Gpio::Pullup::PULLUP, Gpio tx_gpio(port, tx_pin, Gpio::Mode::MODE_AF_PP, Gpio::Pullup::PULLUP, alt_func);
Gpio::AlternateFunction::ALTERNATE_FUNCTION_1); Gpio rx_gpio(port, rx_pin, Gpio::Mode::MODE_AF_PP, Gpio::Pullup::PULLUP, alt_func);
Gpio rx_gpio(port, rx_pin, Gpio::Mode::MODE_AF_PP, Gpio::Pullup::PULLUP,
Gpio::AlternateFunction::ALTERNATE_FUNCTION_1);
// Disable UART // Disable UART
this->uart->CR1 &= ~USART_CR1_UE; uart->CR1 &= ~USART_CR1_UE;
// USART CR1 Configuration // USART CR1 Configuration
uint32_t tmp = this->uart->CR1; uint32_t tmp = uart->CR1;
tmp &= ~((USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| USART_CR1_FIFOEN)); tmp &= ~((USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| USART_CR1_FIFOEN));
tmp |= (USART_CR1_TE | USART_CR1_RE); // RX and TX mode tmp |= (USART_CR1_TE | USART_CR1_RE); // RX and TX mode
this->uart->CR1 = tmp; uart->CR1 = tmp;
// USART CR2 Configuration // USART CR2 Configuration
tmp = this->uart->CR2; tmp = uart->CR2;
tmp &= ~(USART_CR2_STOP); tmp &= ~(USART_CR2_STOP);
this->uart->CR2 = tmp; uart->CR2 = tmp;
// USART CR3 Configuration // USART CR3 Configuration
@@ -54,16 +48,16 @@ Uart::Uart(UartDevice device, uint32_t baud_rate)
// USART BRR Configuration // USART BRR Configuration
tmp = ((64000000 + (baud_rate / 2)) / baud_rate); tmp = ((64000000 + (baud_rate / 2)) / baud_rate);
this->uart->BRR = tmp; uart->BRR = tmp;
// In asynchronous mode, the following bits must be kept cleared: // In asynchronous mode, the following bits must be kept cleared:
// - LINEN and CLKEN bits in the USART_CR2 register, // - LINEN and CLKEN bits in the USART_CR2 register,
// - SCEN, HDSEL and IREN bits in the USART_CR3 register. // - SCEN, HDSEL and IREN bits in the USART_CR3 register.
this->uart->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN); uart->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
this->uart->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); uart->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
// Enable UART // Enable UART
this->uart->CR1 |= USART_CR1_UE; uart->CR1 |= USART_CR1_UE;
} }
void Uart::sync_send(const uint8_t *buffer, uint32_t len) void Uart::sync_send(const uint8_t *buffer, uint32_t len)
@@ -74,7 +68,17 @@ void Uart::sync_send(const uint8_t *buffer, uint32_t len)
for (uint32_t i = 0; i < len; i++) { for (uint32_t i = 0; i < len; i++) {
// wait for tx not full // wait for tx not full
while ((this->uart->ISR & USART_ISR_TXE_TXFNF) == 0); while ((uart->ISR & USART_ISR_TXE_TXFNF) == 0);
this->uart->TDR = buffer[i]; uart->TDR = buffer[i];
} }
} }
bool Uart::sync_receive(uint8_t* res)
{
if((uart->ISR & USART_ISR_RXNE_RXFNE) == 0) {
return false;
}
*res = (uint8_t)(uart->RDR);
return true;
}

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@@ -12,13 +12,13 @@ class Uart
public: public:
enum class UartDevice enum class UartDevice
{ {
UART_2, UART_1,
UART_3, UART_2
UART_4
}; };
Uart(UartDevice, uint32_t); Uart(UartDevice, uint32_t);
void sync_send(const uint8_t *, uint32_t); void sync_send(const uint8_t *, uint32_t);
bool sync_receive(uint8_t*);
private: private:
USART_TypeDef * uart; USART_TypeDef * uart;

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@@ -1,8 +1,8 @@
/** /**
****************************************************************************** ******************************************************************************
* @file startup_stm32g071xx.s * @file startup_stm32g031xx.s
* @author MCD Application Team * @author MCD Application Team
* @brief STM32G071xx devices vector table GCC toolchain. * @brief STM32G031xx devices vector table GCC toolchain.
* This module performs: * This module performs:
* - Set the initial SP * - Set the initial SP
* - Set the initial PC == Reset_Handler, * - Set the initial PC == Reset_Handler,
@@ -14,7 +14,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* Copyright (c) 2018 STMicroelectronics. All rights reserved. * Copyright (c) 2019 STMicroelectronics. All rights reserved.
* *
* This software component is licensed by ST under Apache License, Version 2.0, * This software component is licensed by ST under Apache License, Version 2.0,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
@@ -96,7 +96,6 @@ LoopFillZerobss:
/* Call static constructors */ /* Call static constructors */
bl __libc_init_array bl __libc_init_array
@ bl system_early_init
/* Call the application s entry point.*/ /* Call the application s entry point.*/
bl main bl main
@@ -155,19 +154,19 @@ g_pfnVectors:
.word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
.word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
.word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
.word UCPD1_2_IRQHandler /* UCPD1, UCPD2 */ .word 0 /* reserved */
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
.word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
.word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */ .word DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 5, DMAMUX1 overrun */
.word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */ .word ADC1_IRQHandler /* ADC1 */
.word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */ .word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */ .word TIM3_IRQHandler /* TIM3 */
.word TIM6_DAC_LPTIM1_IRQHandler /* TIM6, DAC and LPTIM1 */ .word LPTIM1_IRQHandler /* LPTIM1 */
.word TIM7_LPTIM2_IRQHandler /* TIM7 and LPTIM2 */ .word LPTIM2_IRQHandler /* LPTIM2 */
.word TIM14_IRQHandler /* TIM14 */ .word TIM14_IRQHandler /* TIM14 */
.word TIM15_IRQHandler /* TIM15 */ .word 0 /* reserved */
.word TIM16_IRQHandler /* TIM16 */ .word TIM16_IRQHandler /* TIM16 */
.word TIM17_IRQHandler /* TIM17 */ .word TIM17_IRQHandler /* TIM17 */
.word I2C1_IRQHandler /* I2C1 */ .word I2C1_IRQHandler /* I2C1 */
@@ -176,8 +175,8 @@ g_pfnVectors:
.word SPI2_IRQHandler /* SPI2 */ .word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */ .word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */ .word USART2_IRQHandler /* USART2 */
.word USART3_4_LPUART1_IRQHandler /* USART3, USART4 and LPUART1 */ .word LPUART1_IRQHandler /* LPUART1 */
.word CEC_IRQHandler /* CEC */ .word 0 /* reserved */
/******************************************************************************* /*******************************************************************************
* *
@@ -226,20 +225,17 @@ g_pfnVectors:
.weak EXTI4_15_IRQHandler .weak EXTI4_15_IRQHandler
.thumb_set EXTI4_15_IRQHandler,Default_Handler .thumb_set EXTI4_15_IRQHandler,Default_Handler
.weak UCPD1_2_IRQHandler
.thumb_set UCPD1_2_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler .weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_3_IRQHandler .weak DMA1_Channel2_3_IRQHandler
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
.weak DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler .weak DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler
.thumb_set DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler,Default_Handler .thumb_set DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler,Default_Handler
.weak ADC1_COMP_IRQHandler .weak ADC1_IRQHandler
.thumb_set ADC1_COMP_IRQHandler,Default_Handler .thumb_set ADC1_IRQHandler,Default_Handler
.weak TIM1_BRK_UP_TRG_COM_IRQHandler .weak TIM1_BRK_UP_TRG_COM_IRQHandler
.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
@@ -253,18 +249,15 @@ g_pfnVectors:
.weak TIM3_IRQHandler .weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler .thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM6_DAC_LPTIM1_IRQHandler .weak LPTIM1_IRQHandler
.thumb_set TIM6_DAC_LPTIM1_IRQHandler,Default_Handler .thumb_set LPTIM1_IRQHandler,Default_Handler
.weak TIM7_LPTIM2_IRQHandler .weak LPTIM2_IRQHandler
.thumb_set TIM7_LPTIM2_IRQHandler,Default_Handler .thumb_set LPTIM2_IRQHandler,Default_Handler
.weak TIM14_IRQHandler .weak TIM14_IRQHandler
.thumb_set TIM14_IRQHandler,Default_Handler .thumb_set TIM14_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler .weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler .thumb_set TIM16_IRQHandler,Default_Handler
@@ -289,11 +282,8 @@ g_pfnVectors:
.weak USART2_IRQHandler .weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler .thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_4_LPUART1_IRQHandler .weak LPUART1_IRQHandler
.thumb_set USART3_4_LPUART1_IRQHandler,Default_Handler .thumb_set LPUART1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

View File

@@ -115,7 +115,6 @@ void SystemClock_Config(void)
SysTick_Config(SystemCoreClock / 1000U); // 1kHz SysTick_Config(SystemCoreClock / 1000U); // 1kHz
NVIC_SetPriority(SysTick_IRQn, SYS_TICK_PRIO); NVIC_SetPriority(SysTick_IRQn, SYS_TICK_PRIO);
/* LSI config */ /* LSI config */
/* Disable the Internal Low Speed oscillator (LSI). */ /* Disable the Internal Low Speed oscillator (LSI). */
RCC->CSR &= ~(RCC_CSR_LSION); RCC->CSR &= ~(RCC_CSR_LSION);
@@ -178,12 +177,17 @@ void SystemClock_Config(void)
tmp &= ~(RCC_CFGR_PPRE); // HCLK not divided tmp &= ~(RCC_CFGR_PPRE); // HCLK not divided
RCC->CFGR = tmp; RCC->CFGR = tmp;
/* Adapt Systick interrupt period */
SystemCoreClock = 64000000; SystemCoreClock = 64000000;
SysTick_Config(SystemCoreClock / 1000U); // 1kHz
NVIC_SetPriority(SysTick_IRQn, SYS_TICK_PRIO);
#ifdef STM32G071xx
/* Configure the USART2 clock source */ /* Configure the USART2 clock source */
tmp = RCC->CCIPR; tmp = RCC->CCIPR;
tmp &= ~(RCC_CCIPR_USART2SEL); // APB clock selected as USART2 clock tmp &= ~(RCC_CCIPR_USART2SEL); // APB clock selected as USART2 clock
RCC->CCIPR = tmp; RCC->CCIPR = tmp;
#endif
} }
void SystemInit(void) void SystemInit(void)
@@ -201,11 +205,13 @@ void SystemInit(void)
RCC->APBENR2 |= RCC_APBENR2_SYSCFGEN; RCC->APBENR2 |= RCC_APBENR2_SYSCFGEN;
RCC->APBENR1 |= RCC_APBENR1_PWREN; RCC->APBENR1 |= RCC_APBENR1_PWREN;
#ifdef STM32G071xx
/* Change strobe configuration of GPIO depending on UCPDx dead battery settings */ /* Change strobe configuration of GPIO depending on UCPDx dead battery settings */
uint32_t tmp = SYSCFG->CFGR1; uint32_t tmp = SYSCFG->CFGR1;
tmp &= ~(SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE); tmp &= ~(SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE);
tmp |= (SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE); tmp |= (SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE);
SYSCFG->CFGR1 = tmp; SYSCFG->CFGR1 = tmp;
#endif
SystemClock_Config(); SystemClock_Config();
} }