Compare commits
6 Commits
38095715e9
...
main
Author | SHA1 | Date | |
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d509688167 | ||
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f94eeb5ffe | ||
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1eee0af374 | ||
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103cbe1d6a | ||
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46382e2cf7 | ||
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4ff7ad8748 |
38
.devcontainer/Dockerfile
Normal file
38
.devcontainer/Dockerfile
Normal file
@@ -0,0 +1,38 @@
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FROM debian:stable-slim
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LABEL maintainer="thomas.klaehn@perinet.io"
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# Enable contrip section for "repo"
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# RUN sed -i -e 's/.main$/ main contrib/' /etc/apt/sources.list
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RUN export DEBIAN_FRONTEND=noninteractive && apt-get update && apt-get -y install --no-install-recommends \
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binutils-arm-none-eabi \
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gcc-arm-none-eabi \
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gdb-multiarch \
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git \
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libstdc++-arm-none-eabi-dev \
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libstdc++-arm-none-eabi-newlib \
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make \
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openocd
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# Set UTF8 locale settings
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# RUN apt-get install -yq locales && \
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# locale-gen en_US.UTF-8 && \
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# sed -i -e 's/# en_US.UTF-8 UTF-8/en_US.UTF-8 UTF-8/' /etc/locale.gen && \
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# dpkg-reconfigure --frontend=noninteractive locales && \
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# update-locale LANG=en_US.UTF-8
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# ENV LANG en_US.UTF-8
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# RUN useradd -ms /bin/bash builder
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# RUN echo "builder:builder" | chpasswd
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# ADD init.sh /usr/local/bin/init.sh
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# WORKDIR = /work
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# ENTRYPOINT ["/usr/local/bin/init.sh"]
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RUN mkdir /workspaces
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VOLUME /workspaces
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WORKDIR /workspaces/
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CMD ["/bin/bash"]
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48
.devcontainer/devcontainer.json
Normal file
48
.devcontainer/devcontainer.json
Normal file
@@ -0,0 +1,48 @@
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// For format details, see https://aka.ms/devcontainer.json. For config options, see the
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// README at: https://github.com/devcontainers/templates/tree/main/src/typescript-node
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{
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"name": "arm-none-eabi-cpp",
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// Or use a Dockerfile or Docker Compose file. More info: https://containers.dev/guide/dockerfile
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"build": { "dockerfile": "Dockerfile" },
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// Privileged container in order to access /dev
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"privileged": true,
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// Mount USB devices (debug probes, UART interfaces, ...)
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"mounts": [
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"source=/dev/bus/usb/,target=/dev/bus/usb/,type=bind"
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],
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// Features to add to the dev container. More info: https://containers.dev/features.
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// "features": {},
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// Use 'forwardPorts' to make a list of ports inside the container available locally.
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// "forwardPorts": [],
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// Use 'postCreateCommand' to run commands after the container is created.
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// "postCreateCommand": "sudo apt update && sudo apt install -y openocd && sudo apt install -y gdb-multiarch",
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// Configure tool-specific properties.
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"customizations": {
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"vscode": {
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"extensions": [
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"ms-vscode.cpptools",
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"ms-vscode.cpptools-extension-pack",
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"marus25.cortex-debug",
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"zoma.vscode-auto-open-workspace"
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],
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// default settings, can be overwritten in .vscode/settings.conf
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"settings": {
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"terminal.integrated.defaultProfile.linux.shell": "/bin/bash",
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"autoOpenWorkspace.enableAutoOpenIfSingleWorkspace": true,
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"autoOpenWorkspace.enableAutoOpenAlwaysFirst": true,
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"files.exclude": {
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"**/.git": true,
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"**/.repo": true
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}
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}
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}
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}
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// Uncomment to connect as root instead. More info: https://aka.ms/dev-containers-non-root.
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// "remoteUser": "root"
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}
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2
.gitignore
vendored
2
.gitignore
vendored
@@ -1 +1 @@
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_build/
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build/
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26
.vscode/launch.json
vendored
26
.vscode/launch.json
vendored
@@ -1,34 +1,24 @@
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{
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{
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// Use IntelliSense to learn about possible attributes.
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// Hover to view descriptions of existing attributes.
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// For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
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"version": "0.2.0",
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"version": "0.2.0",
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"configurations": [
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"configurations": [
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{
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{
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"name": "gdb Launch Debug",
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"name": "gdb Launch Debug",
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"type": "cppdbg",
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"type": "cppdbg",
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"request": "launch",
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"request": "launch",
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"program": "${workspaceFolder}/_build/firmware.elf",
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"args": [],
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"args": [
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"program": "${workspaceFolder}/build/firmware.elf",
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"-d","${workspaceFolder}/Core/Src",
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"-d","${workspaceFolder}/Core/Startup",
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"-d","${workspaceFolder}/Core/Drivers",
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],
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"stopAtEntry": true,
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"stopAtEntry": true,
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"cwd": "${workspaceRoot}",
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"cwd": "${workspaceRoot}",
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"environment": [],
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"environment": [],
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"externalConsole": false,
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"externalConsole": false,
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"MIMode": "gdb",
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"MIMode": "gdb",
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"miDebuggerPath": "/usr/bin/arm-none-eabi-gdb",
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"miDebuggerPath": "gdb-multiarch",
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"debugServerPath": "openocd",
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"debugServerPath": "openocd",
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"debugServerArgs": "-f /usr/local/share/openocd/scripts/interface/stlink.cfg -f /usr/local/share/openocd/scripts/target/stm32g0x.cfg",
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"debugServerArgs": "-f ${workspaceRoot}/openocd.cfg",
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"serverLaunchTimeout": 20000,
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"serverLaunchTimeout": 20000,
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"filterStderr": true,
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"filterStderr": true,
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"filterStdout": false,
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"filterStdout": false,
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"serverStarted": "Info : Listening on port 3333 for gdb connections",
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"serverStarted": "Info : Listening on port 3333 for gdb connections",
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// "sourceFileMap": {
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// "/work/":"${workspaceFolder}"
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// },
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"sourceFileMap": {
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"sourceFileMap": {
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"${workspaceRoot}":"${workspaceFolder}"
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"${workspaceRoot}":"${workspaceFolder}"
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},
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},
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@@ -53,7 +43,7 @@
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},
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},
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{
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{
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"description": "Load executable into debugger.",
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"description": "Load executable into debugger.",
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"text": "file ${workspaceFolder}/_build/firmware.elf",
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"text": "file ${workspaceFolder}/build/firmware.elf",
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"ignoreFailures": false
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"ignoreFailures": false
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},
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},
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{
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{
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@@ -61,7 +51,7 @@
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"text": "load",
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"text": "load",
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"ignoreFailures": false
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"ignoreFailures": false
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}
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}
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]
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]
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},
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}
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]
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]
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}
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}
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56
.vscode/tasks.json
vendored
56
.vscode/tasks.json
vendored
@@ -2,9 +2,8 @@
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"version": "2.0.0",
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"version": "2.0.0",
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"options": {
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"options": {
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"env": {
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"env": {
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// "APPLICATION": "blinky",
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"SOC": "stm32g031",
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// "APPLICATION": "spi",
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// "SOC": "stm32g071",
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// "APPLICATION": "st7789_lcd",
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},
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},
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},
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},
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"presentation": {
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"presentation": {
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@@ -31,23 +30,6 @@
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"isDefault": true
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"isDefault": true
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}
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}
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},
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},
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{
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"label": "flash",
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"type":"shell",
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"command": "make flash",
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"problemMatcher": {
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"base": "$gcc",
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"owner": "gcc",
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"fileLocation": [
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"relative",
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"${workspaceFolder}"
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]
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},
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"group": {
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"kind": "build",
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"isDefault": true
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}
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},
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{
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{
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"label": "clean",
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"label": "clean",
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"type":"shell",
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"type":"shell",
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@@ -64,40 +46,6 @@
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"kind": "build",
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"kind": "build",
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"isDefault": true
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"isDefault": true
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}
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}
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},
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{
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"label": "distclean",
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"type":"shell",
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"command": "make distclean",
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"problemMatcher": {
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"base": "$gcc",
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"owner": "gcc",
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"fileLocation": [
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"relative",
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"${workspaceFolder}"
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]
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},
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"group": {
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"kind": "build",
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"isDefault": true
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}
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},
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{
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"label": "check",
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"type":"shell",
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"command": "make check",
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"problemMatcher": {
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"base": "$gcc",
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"owner": "gcc",
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"fileLocation": [
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"relative",
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"${workspaceFolder}"
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]
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},
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"group": {
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|
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"kind": "build",
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|
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"isDefault": true
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|
||||||
}
|
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}
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}
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]
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]
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}
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}
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|
63
Core/main.cc
63
Core/main.cc
@@ -1,63 +0,0 @@
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#include <cstring>
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#include <cstdint>
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#include <cstdio>
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#include "delay.h"
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#include "platform/stm32g0xx/Gpio.h"
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#include "platform/stm32g0xx/Uart.h"
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#include "platform/stm32g0xx/IndependentWatchdog.h"
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// NOTE! The independent watchdog is clocked by a separate clock. this one
|
|
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// isn't controlled by JTAG. That's why the independent watchdog needs to
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// be disabled during JTAG debug sessions.
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#define JTAG_DEBUG
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using namespace perinet::platform::stm32g0xx;
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Gpio green_led(Gpio::Port::PORT_A, 5, Gpio::Mode::MODE_OUTPUT_PP);
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Uart uart(Uart::UartDevice::UART_2, 115200);
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#ifndef JTAG_DEBUG
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IndependentWatchdog watchdog(4095, 4095);
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#endif
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int main(void)
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{
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unsigned int i = 1, j = 40;
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char tx_buf[80];
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|
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|
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#ifndef JTAG_DEBUG
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watchdog.enable();
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#endif
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|
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while (1) {
|
|
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if (j < 100) {
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j += 10;
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}
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|
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else if (j < 200) {
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|
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j += 20;
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|
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}
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|
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else if (j < 400) {
|
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j += 40;
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}
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|
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if (j > 800) {
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j = 800;
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}
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sprintf(tx_buf, "%u: Hello World\r\n", i++);
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uart.sync_send((const uint8_t *)tx_buf, strlen(tx_buf));
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green_led.toggle();
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|
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delay_ms(j);
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|
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#ifndef JTAG_DEBUG
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|
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watchdog.trigger();
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|
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#endif
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|
||||||
}
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|
||||||
}
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|
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|
|
||||||
#ifdef USE_FULL_ASSERT
|
|
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void assert_failed(uint8_t *file, uint32_t line)
|
|
||||||
{
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|
||||||
/* User can add his own implementation to report the file name and line number,
|
|
||||||
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
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|
||||||
}
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|
||||||
#endif /* USE_FULL_ASSERT */
|
|
37
Makefile
37
Makefile
@@ -3,22 +3,12 @@ TARGET = firmware
|
|||||||
DEBUG = 1
|
DEBUG = 1
|
||||||
OPT = -O0
|
OPT = -O0
|
||||||
|
|
||||||
BUILD_DIR = _build
|
BUILD_DIR = build
|
||||||
|
|
||||||
CC_SOURCES = \
|
SRC_DIRS := $(shell find src -type d)
|
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Core/main.cc \
|
CC_SOURCES = $(foreach folder, $(SRC_DIRS), $(wildcard $(folder)/*.cc))
|
||||||
platform/stm32g0xx/Gpio.cc \
|
C_SOURCES = $(foreach folder, $(SRC_DIRS), $(wildcard $(folder)/*.c))
|
||||||
platform/stm32g0xx/Uart.cc \
|
ASM_SOURCES = $(foreach folder, $(SRC_DIRS), $(wildcard $(folder)/*.s))
|
||||||
platform/stm32g0xx/IndependentWatchdog.cc \
|
|
||||||
platform/stm32g0xx/low_level_interrupt.cc
|
|
||||||
|
|
||||||
C_SOURCES = \
|
|
||||||
platform/stm32g0xx/system_stm32g0xx.c \
|
|
||||||
platform/stm32g0xx/syscalls.c \
|
|
||||||
platform/stm32g0xx/sysmem.c \
|
|
||||||
|
|
||||||
ASM_SOURCES = \
|
|
||||||
platform/stm32g0xx/startup_stm32g071rbtx.s
|
|
||||||
|
|
||||||
PREFIX = arm-none-eabi-
|
PREFIX = arm-none-eabi-
|
||||||
CC = $(PREFIX)gcc
|
CC = $(PREFIX)gcc
|
||||||
@@ -33,18 +23,11 @@ BIN = $(CP) -O binary -S
|
|||||||
CPU = -mcpu=cortex-m0plus
|
CPU = -mcpu=cortex-m0plus
|
||||||
MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
|
MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
|
||||||
|
|
||||||
C_DEFS = \
|
C_DEFS = -DSTM32G031xx
|
||||||
-DSTM32G071xx
|
LDSCRIPT = src/platform/stm32g0xx/STM32G031Y8YX_FLASH.ld
|
||||||
|
|
||||||
C_INCLUDES = \
|
|
||||||
-I. \
|
|
||||||
-ICore \
|
|
||||||
-Iarch/CMSIS/Device/ST/STM32G0xx/Include \
|
|
||||||
-Iarch/CMSIS/Include \
|
|
||||||
-Iplatform/stm32g0xx
|
|
||||||
|
|
||||||
ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
|
ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
|
||||||
CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
|
CFLAGS = $(MCU) $(C_DEFS) $(addprefix -I,$(SRC_DIRS)) $(OPT) -Wall -fdata-sections -ffunction-sections
|
||||||
|
|
||||||
ifeq ($(DEBUG), 1)
|
ifeq ($(DEBUG), 1)
|
||||||
CFLAGS += -ggdb3
|
CFLAGS += -ggdb3
|
||||||
@@ -52,8 +35,6 @@ endif
|
|||||||
|
|
||||||
CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
|
CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
|
||||||
|
|
||||||
LDSCRIPT = platform/stm32g0xx/STM32G071RBTX_FLASH.ld
|
|
||||||
|
|
||||||
LIBS = -lc -lm -lnosys
|
LIBS = -lc -lm -lnosys
|
||||||
LIBDIR =
|
LIBDIR =
|
||||||
LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
|
LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
|
||||||
@@ -78,7 +59,7 @@ $(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR)
|
|||||||
$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)
|
$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)
|
||||||
$(AS) -c $(CFLAGS) $< -o $@
|
$(AS) -c $(CFLAGS) $< -o $@
|
||||||
|
|
||||||
$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile
|
$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) | Makefile
|
||||||
$(CXX) $(OBJECTS) $(LDFLAGS) -o $@
|
$(CXX) $(OBJECTS) $(LDFLAGS) -o $@
|
||||||
$(SZ) $@
|
$(SZ) $@
|
||||||
|
|
||||||
|
2
openocd.cfg
Normal file
2
openocd.cfg
Normal file
@@ -0,0 +1,2 @@
|
|||||||
|
source [find interface/stlink.cfg]
|
||||||
|
source [find target/stm32g0x.cfg]
|
File diff suppressed because it is too large
Load Diff
29
src/main.cc
Normal file
29
src/main.cc
Normal file
@@ -0,0 +1,29 @@
|
|||||||
|
#include <cstring>
|
||||||
|
#include <cstdint>
|
||||||
|
#include <cstdio>
|
||||||
|
|
||||||
|
#include "delay.h"
|
||||||
|
#include "platform/stm32g0xx/Gpio.h"
|
||||||
|
#include "platform/stm32g0xx/Uart.h"
|
||||||
|
|
||||||
|
|
||||||
|
using namespace perinet::platform::stm32g0xx;
|
||||||
|
|
||||||
|
Uart uart1(Uart::UartDevice::UART_1, 115200);
|
||||||
|
Uart uart2(Uart::UartDevice::UART_2, 115200);
|
||||||
|
|
||||||
|
int main(void)
|
||||||
|
{
|
||||||
|
char tx_buf[] = "\r\rProgram: UART bridge\r\n\n Receive on uart2 and transmit it on uart 1\r\n";
|
||||||
|
uint8_t rec;
|
||||||
|
uart1.sync_send((const uint8_t *)tx_buf, strlen(tx_buf));
|
||||||
|
|
||||||
|
while(true) {
|
||||||
|
if(uart2.sync_receive(&rec)) {
|
||||||
|
uart1.sync_send(&rec, 1);
|
||||||
|
}
|
||||||
|
if(uart1.sync_receive(&rec)) {
|
||||||
|
uart2.sync_send(&rec, 1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
@@ -3,7 +3,7 @@
|
|||||||
|
|
||||||
#include <cstdint>
|
#include <cstdint>
|
||||||
|
|
||||||
#include "stm32g071xx.h"
|
#include "stm32g0xx.h"
|
||||||
|
|
||||||
namespace perinet::platform::stm32g0xx {
|
namespace perinet::platform::stm32g0xx {
|
||||||
|
|
@@ -2,9 +2,9 @@
|
|||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @file LinkerScript.ld
|
* @file LinkerScript.ld
|
||||||
* @author Auto-generated by STM32CubeIDE
|
* @author Auto-generated by STM32CubeIDE
|
||||||
* Abstract : Linker script for NUCLEO-G071RB Board embedding STM32G071RBTx Device from stm32g0 series
|
* @brief Linker script for STM32G031Y8Yx Device from STM32G0 series
|
||||||
* 128Kbytes FLASH
|
* 64Kbytes FLASH
|
||||||
* 36Kbytes RAM
|
* 8Kbytes RAM
|
||||||
*
|
*
|
||||||
* Set heap size, stack size and stack location according
|
* Set heap size, stack size and stack location according
|
||||||
* to application requirements.
|
* to application requirements.
|
||||||
@@ -36,8 +36,8 @@ _Min_Stack_Size = 0x400 ; /* required amount of stack */
|
|||||||
/* Memories definition */
|
/* Memories definition */
|
||||||
MEMORY
|
MEMORY
|
||||||
{
|
{
|
||||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 36K
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8K
|
||||||
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K
|
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Sections */
|
/* Sections */
|
@@ -6,47 +6,41 @@ using namespace perinet::platform::stm32g0xx;
|
|||||||
Uart::Uart(UartDevice device, uint32_t baud_rate)
|
Uart::Uart(UartDevice device, uint32_t baud_rate)
|
||||||
{
|
{
|
||||||
uint32_t tx_pin = 2;
|
uint32_t tx_pin = 2;
|
||||||
uint32_t rx_pin = 3;
|
uint32_t rx_pin = 15;
|
||||||
Gpio::Port port = Gpio::Port::PORT_A;
|
Gpio::Port port = Gpio::Port::PORT_A;
|
||||||
|
Gpio::AlternateFunction alt_func = Gpio::AlternateFunction::ALTERNATE_FUNCTION_0;
|
||||||
switch(device) {
|
switch(device) {
|
||||||
|
case UartDevice::UART_1:
|
||||||
|
uart = USART1;
|
||||||
|
RCC->APBENR2 |= RCC_APBENR2_USART1EN;
|
||||||
|
tx_pin = 6;
|
||||||
|
rx_pin = 7;
|
||||||
|
port = Gpio::Port::PORT_B;
|
||||||
|
break;
|
||||||
|
|
||||||
case UartDevice::UART_2:
|
case UartDevice::UART_2:
|
||||||
this->uart = USART2;
|
uart = USART2;
|
||||||
RCC->APBENR1 |= RCC_APBENR1_USART2EN;
|
RCC->APBENR1 |= RCC_APBENR1_USART2EN;
|
||||||
break;
|
alt_func = Gpio::AlternateFunction::ALTERNATE_FUNCTION_1;
|
||||||
|
|
||||||
case UartDevice::UART_3:
|
|
||||||
this->uart = USART3;
|
|
||||||
RCC->APBENR1 |= RCC_APBENR1_USART3EN;
|
|
||||||
|
|
||||||
// FIXME: Set pin confing accordingly
|
|
||||||
break;
|
|
||||||
|
|
||||||
case UartDevice::UART_4:
|
|
||||||
this->uart = USART4;
|
|
||||||
RCC->APBENR1 |= RCC_APBENR1_USART4EN;
|
|
||||||
|
|
||||||
// FIXME: Set pin confing accordingly
|
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
Gpio tx_gpio(port, tx_pin, Gpio::Mode::MODE_AF_PP, Gpio::Pullup::PULLUP,
|
Gpio tx_gpio(port, tx_pin, Gpio::Mode::MODE_AF_PP, Gpio::Pullup::PULLUP, alt_func);
|
||||||
Gpio::AlternateFunction::ALTERNATE_FUNCTION_1);
|
Gpio rx_gpio(port, rx_pin, Gpio::Mode::MODE_AF_PP, Gpio::Pullup::PULLUP, alt_func);
|
||||||
Gpio rx_gpio(port, rx_pin, Gpio::Mode::MODE_AF_PP, Gpio::Pullup::PULLUP,
|
|
||||||
Gpio::AlternateFunction::ALTERNATE_FUNCTION_1);
|
|
||||||
|
|
||||||
// Disable UART
|
// Disable UART
|
||||||
this->uart->CR1 &= ~USART_CR1_UE;
|
uart->CR1 &= ~USART_CR1_UE;
|
||||||
|
|
||||||
// USART CR1 Configuration
|
// USART CR1 Configuration
|
||||||
uint32_t tmp = this->uart->CR1;
|
uint32_t tmp = uart->CR1;
|
||||||
tmp &= ~((USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| USART_CR1_FIFOEN));
|
tmp &= ~((USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| USART_CR1_FIFOEN));
|
||||||
tmp |= (USART_CR1_TE | USART_CR1_RE); // RX and TX mode
|
tmp |= (USART_CR1_TE | USART_CR1_RE); // RX and TX mode
|
||||||
this->uart->CR1 = tmp;
|
uart->CR1 = tmp;
|
||||||
|
|
||||||
// USART CR2 Configuration
|
// USART CR2 Configuration
|
||||||
tmp = this->uart->CR2;
|
tmp = uart->CR2;
|
||||||
tmp &= ~(USART_CR2_STOP);
|
tmp &= ~(USART_CR2_STOP);
|
||||||
this->uart->CR2 = tmp;
|
uart->CR2 = tmp;
|
||||||
|
|
||||||
// USART CR3 Configuration
|
// USART CR3 Configuration
|
||||||
|
|
||||||
@@ -54,16 +48,16 @@ Uart::Uart(UartDevice device, uint32_t baud_rate)
|
|||||||
|
|
||||||
// USART BRR Configuration
|
// USART BRR Configuration
|
||||||
tmp = ((64000000 + (baud_rate / 2)) / baud_rate);
|
tmp = ((64000000 + (baud_rate / 2)) / baud_rate);
|
||||||
this->uart->BRR = tmp;
|
uart->BRR = tmp;
|
||||||
|
|
||||||
// In asynchronous mode, the following bits must be kept cleared:
|
// In asynchronous mode, the following bits must be kept cleared:
|
||||||
// - LINEN and CLKEN bits in the USART_CR2 register,
|
// - LINEN and CLKEN bits in the USART_CR2 register,
|
||||||
// - SCEN, HDSEL and IREN bits in the USART_CR3 register.
|
// - SCEN, HDSEL and IREN bits in the USART_CR3 register.
|
||||||
this->uart->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
|
uart->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
|
||||||
this->uart->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
|
uart->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
|
||||||
|
|
||||||
// Enable UART
|
// Enable UART
|
||||||
this->uart->CR1 |= USART_CR1_UE;
|
uart->CR1 |= USART_CR1_UE;
|
||||||
}
|
}
|
||||||
|
|
||||||
void Uart::sync_send(const uint8_t *buffer, uint32_t len)
|
void Uart::sync_send(const uint8_t *buffer, uint32_t len)
|
||||||
@@ -74,7 +68,17 @@ void Uart::sync_send(const uint8_t *buffer, uint32_t len)
|
|||||||
|
|
||||||
for (uint32_t i = 0; i < len; i++) {
|
for (uint32_t i = 0; i < len; i++) {
|
||||||
// wait for tx not full
|
// wait for tx not full
|
||||||
while ((this->uart->ISR & USART_ISR_TXE_TXFNF) == 0);
|
while ((uart->ISR & USART_ISR_TXE_TXFNF) == 0);
|
||||||
this->uart->TDR = buffer[i];
|
uart->TDR = buffer[i];
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
bool Uart::sync_receive(uint8_t* res)
|
||||||
|
{
|
||||||
|
if((uart->ISR & USART_ISR_RXNE_RXFNE) == 0) {
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
*res = (uint8_t)(uart->RDR);
|
||||||
|
return true;
|
||||||
|
}
|
@@ -12,13 +12,13 @@ class Uart
|
|||||||
public:
|
public:
|
||||||
enum class UartDevice
|
enum class UartDevice
|
||||||
{
|
{
|
||||||
UART_2,
|
UART_1,
|
||||||
UART_3,
|
UART_2
|
||||||
UART_4
|
|
||||||
};
|
};
|
||||||
|
|
||||||
Uart(UartDevice, uint32_t);
|
Uart(UartDevice, uint32_t);
|
||||||
void sync_send(const uint8_t *, uint32_t);
|
void sync_send(const uint8_t *, uint32_t);
|
||||||
|
bool sync_receive(uint8_t*);
|
||||||
|
|
||||||
private:
|
private:
|
||||||
USART_TypeDef * uart;
|
USART_TypeDef * uart;
|
@@ -1,8 +1,8 @@
|
|||||||
/**
|
/**
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @file startup_stm32g071xx.s
|
* @file startup_stm32g031xx.s
|
||||||
* @author MCD Application Team
|
* @author MCD Application Team
|
||||||
* @brief STM32G071xx devices vector table GCC toolchain.
|
* @brief STM32G031xx devices vector table GCC toolchain.
|
||||||
* This module performs:
|
* This module performs:
|
||||||
* - Set the initial SP
|
* - Set the initial SP
|
||||||
* - Set the initial PC == Reset_Handler,
|
* - Set the initial PC == Reset_Handler,
|
||||||
@@ -14,7 +14,7 @@
|
|||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* Copyright (c) 2018 STMicroelectronics. All rights reserved.
|
* Copyright (c) 2019 STMicroelectronics. All rights reserved.
|
||||||
*
|
*
|
||||||
* This software component is licensed by ST under Apache License, Version 2.0,
|
* This software component is licensed by ST under Apache License, Version 2.0,
|
||||||
* the "License"; You may not use this file except in compliance with the
|
* the "License"; You may not use this file except in compliance with the
|
||||||
@@ -96,7 +96,6 @@ LoopFillZerobss:
|
|||||||
|
|
||||||
/* Call static constructors */
|
/* Call static constructors */
|
||||||
bl __libc_init_array
|
bl __libc_init_array
|
||||||
@ bl system_early_init
|
|
||||||
/* Call the application s entry point.*/
|
/* Call the application s entry point.*/
|
||||||
bl main
|
bl main
|
||||||
|
|
||||||
@@ -155,19 +154,19 @@ g_pfnVectors:
|
|||||||
.word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
|
.word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
|
||||||
.word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
|
.word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
|
||||||
.word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
|
.word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
|
||||||
.word UCPD1_2_IRQHandler /* UCPD1, UCPD2 */
|
.word 0 /* reserved */
|
||||||
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
||||||
.word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
|
.word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
|
||||||
.word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */
|
.word DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 5, DMAMUX1 overrun */
|
||||||
.word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */
|
.word ADC1_IRQHandler /* ADC1 */
|
||||||
.word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
|
.word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
|
||||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||||
.word TIM2_IRQHandler /* TIM2 */
|
.word TIM2_IRQHandler /* TIM2 */
|
||||||
.word TIM3_IRQHandler /* TIM3 */
|
.word TIM3_IRQHandler /* TIM3 */
|
||||||
.word TIM6_DAC_LPTIM1_IRQHandler /* TIM6, DAC and LPTIM1 */
|
.word LPTIM1_IRQHandler /* LPTIM1 */
|
||||||
.word TIM7_LPTIM2_IRQHandler /* TIM7 and LPTIM2 */
|
.word LPTIM2_IRQHandler /* LPTIM2 */
|
||||||
.word TIM14_IRQHandler /* TIM14 */
|
.word TIM14_IRQHandler /* TIM14 */
|
||||||
.word TIM15_IRQHandler /* TIM15 */
|
.word 0 /* reserved */
|
||||||
.word TIM16_IRQHandler /* TIM16 */
|
.word TIM16_IRQHandler /* TIM16 */
|
||||||
.word TIM17_IRQHandler /* TIM17 */
|
.word TIM17_IRQHandler /* TIM17 */
|
||||||
.word I2C1_IRQHandler /* I2C1 */
|
.word I2C1_IRQHandler /* I2C1 */
|
||||||
@@ -176,8 +175,8 @@ g_pfnVectors:
|
|||||||
.word SPI2_IRQHandler /* SPI2 */
|
.word SPI2_IRQHandler /* SPI2 */
|
||||||
.word USART1_IRQHandler /* USART1 */
|
.word USART1_IRQHandler /* USART1 */
|
||||||
.word USART2_IRQHandler /* USART2 */
|
.word USART2_IRQHandler /* USART2 */
|
||||||
.word USART3_4_LPUART1_IRQHandler /* USART3, USART4 and LPUART1 */
|
.word LPUART1_IRQHandler /* LPUART1 */
|
||||||
.word CEC_IRQHandler /* CEC */
|
.word 0 /* reserved */
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
*
|
*
|
||||||
@@ -226,20 +225,17 @@ g_pfnVectors:
|
|||||||
.weak EXTI4_15_IRQHandler
|
.weak EXTI4_15_IRQHandler
|
||||||
.thumb_set EXTI4_15_IRQHandler,Default_Handler
|
.thumb_set EXTI4_15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak UCPD1_2_IRQHandler
|
|
||||||
.thumb_set UCPD1_2_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak DMA1_Channel1_IRQHandler
|
.weak DMA1_Channel1_IRQHandler
|
||||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA1_Channel2_3_IRQHandler
|
.weak DMA1_Channel2_3_IRQHandler
|
||||||
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
|
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
|
.weak DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler
|
||||||
.thumb_set DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler,Default_Handler
|
.thumb_set DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak ADC1_COMP_IRQHandler
|
.weak ADC1_IRQHandler
|
||||||
.thumb_set ADC1_COMP_IRQHandler,Default_Handler
|
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM1_BRK_UP_TRG_COM_IRQHandler
|
.weak TIM1_BRK_UP_TRG_COM_IRQHandler
|
||||||
.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
|
.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
|
||||||
@@ -253,18 +249,15 @@ g_pfnVectors:
|
|||||||
.weak TIM3_IRQHandler
|
.weak TIM3_IRQHandler
|
||||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM6_DAC_LPTIM1_IRQHandler
|
.weak LPTIM1_IRQHandler
|
||||||
.thumb_set TIM6_DAC_LPTIM1_IRQHandler,Default_Handler
|
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM7_LPTIM2_IRQHandler
|
.weak LPTIM2_IRQHandler
|
||||||
.thumb_set TIM7_LPTIM2_IRQHandler,Default_Handler
|
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM14_IRQHandler
|
.weak TIM14_IRQHandler
|
||||||
.thumb_set TIM14_IRQHandler,Default_Handler
|
.thumb_set TIM14_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak TIM15_IRQHandler
|
|
||||||
.thumb_set TIM15_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
.weak TIM16_IRQHandler
|
.weak TIM16_IRQHandler
|
||||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||||
|
|
||||||
@@ -289,11 +282,8 @@ g_pfnVectors:
|
|||||||
.weak USART2_IRQHandler
|
.weak USART2_IRQHandler
|
||||||
.thumb_set USART2_IRQHandler,Default_Handler
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak USART3_4_LPUART1_IRQHandler
|
.weak LPUART1_IRQHandler
|
||||||
.thumb_set USART3_4_LPUART1_IRQHandler,Default_Handler
|
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
.weak CEC_IRQHandler
|
|
||||||
.thumb_set CEC_IRQHandler,Default_Handler
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@@ -115,7 +115,6 @@ void SystemClock_Config(void)
|
|||||||
SysTick_Config(SystemCoreClock / 1000U); // 1kHz
|
SysTick_Config(SystemCoreClock / 1000U); // 1kHz
|
||||||
NVIC_SetPriority(SysTick_IRQn, SYS_TICK_PRIO);
|
NVIC_SetPriority(SysTick_IRQn, SYS_TICK_PRIO);
|
||||||
|
|
||||||
|
|
||||||
/* LSI config */
|
/* LSI config */
|
||||||
/* Disable the Internal Low Speed oscillator (LSI). */
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
||||||
RCC->CSR &= ~(RCC_CSR_LSION);
|
RCC->CSR &= ~(RCC_CSR_LSION);
|
||||||
@@ -178,12 +177,17 @@ void SystemClock_Config(void)
|
|||||||
tmp &= ~(RCC_CFGR_PPRE); // HCLK not divided
|
tmp &= ~(RCC_CFGR_PPRE); // HCLK not divided
|
||||||
RCC->CFGR = tmp;
|
RCC->CFGR = tmp;
|
||||||
|
|
||||||
|
/* Adapt Systick interrupt period */
|
||||||
SystemCoreClock = 64000000;
|
SystemCoreClock = 64000000;
|
||||||
|
SysTick_Config(SystemCoreClock / 1000U); // 1kHz
|
||||||
|
NVIC_SetPriority(SysTick_IRQn, SYS_TICK_PRIO);
|
||||||
|
|
||||||
|
#ifdef STM32G071xx
|
||||||
/* Configure the USART2 clock source */
|
/* Configure the USART2 clock source */
|
||||||
tmp = RCC->CCIPR;
|
tmp = RCC->CCIPR;
|
||||||
tmp &= ~(RCC_CCIPR_USART2SEL); // APB clock selected as USART2 clock
|
tmp &= ~(RCC_CCIPR_USART2SEL); // APB clock selected as USART2 clock
|
||||||
RCC->CCIPR = tmp;
|
RCC->CCIPR = tmp;
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
void SystemInit(void)
|
void SystemInit(void)
|
||||||
@@ -201,11 +205,13 @@ void SystemInit(void)
|
|||||||
RCC->APBENR2 |= RCC_APBENR2_SYSCFGEN;
|
RCC->APBENR2 |= RCC_APBENR2_SYSCFGEN;
|
||||||
RCC->APBENR1 |= RCC_APBENR1_PWREN;
|
RCC->APBENR1 |= RCC_APBENR1_PWREN;
|
||||||
|
|
||||||
|
#ifdef STM32G071xx
|
||||||
/* Change strobe configuration of GPIO depending on UCPDx dead battery settings */
|
/* Change strobe configuration of GPIO depending on UCPDx dead battery settings */
|
||||||
uint32_t tmp = SYSCFG->CFGR1;
|
uint32_t tmp = SYSCFG->CFGR1;
|
||||||
tmp &= ~(SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE);
|
tmp &= ~(SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE);
|
||||||
tmp |= (SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE);
|
tmp |= (SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE);
|
||||||
SYSCFG->CFGR1 = tmp;
|
SYSCFG->CFGR1 = tmp;
|
||||||
|
#endif
|
||||||
|
|
||||||
SystemClock_Config();
|
SystemClock_Config();
|
||||||
}
|
}
|
Reference in New Issue
Block a user