I2c tx/rx non-blocking

.vscode/c_cpp_properties.json

@@ -3,8 +3,7 @@
         {
             "name": "Linux",
             "includePath": [
-                "${workspaceFolder}/**",
+                "${workspaceFolder}/**"
-                "${workspaceFolder}/base"
             ],
             "defines": [],
             "compilerPath": "/usr/bin/clang",

.vscode/launch.json

@@ -1,20 +1,27 @@
 {
+    // Use IntelliSense to learn about possible attributes.
+    // Hover to view descriptions of existing attributes.
+    // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
     "version": "0.2.0",
     "configurations": [
         {
             "name": "gdb Launch Debug",
             "type": "cppdbg",
             "request": "launch",
-            "args": [],
             "program": "${workspaceFolder}/build/firmware.elf",
+            "args": [
+                "-d","${workspaceFolder}/Core/Src",
+                "-d","${workspaceFolder}/Core/Startup",
+                "-d","${workspaceFolder}/Core/Drivers",
+                ],
             "stopAtEntry": true,
             "cwd": "${workspaceRoot}",
             "environment": [],
             "externalConsole": false,
             "MIMode": "gdb",
-            "miDebuggerPath": "arm-none-eabi-gdb",
+            "miDebuggerPath": "/usr/local/bin/arm-none-eabi-gdb",
             "debugServerPath": "openocd",
-            "debugServerArgs": "-f ${workspaceRoot}/openocd.cfg",
+            "debugServerArgs": "-f /usr/local/share/openocd/scripts/interface/stlink.cfg -f /usr/local/share/openocd/scripts/target/stm32g0x.cfg",
             "serverLaunchTimeout": 20000,
             "filterStderr": true,
             "filterStdout": false,
@@ -51,7 +58,7 @@
                     "text": "load",
                     "ignoreFailures": false
                 }
-            ]
+             ]
-        }
+        },
     ]
 }

.vscode/tasks.json

@@ -2,8 +2,9 @@
     "version": "2.0.0",
     "options": {
         "env": {
-            "SOC": "stm32g031",
+            // "APPLICATION": "blinky",
-            // "SOC": "stm32g071",
+            // "APPLICATION": "spi",
+            // "APPLICATION": "st7789_lcd",
         },
     },
     "presentation": {
@@ -30,6 +31,23 @@
                 "isDefault": true
             }
         },
+        {
+            "label": "flash",
+            "type":"shell",
+            "command": "make flash",
+            "problemMatcher": {
+                "base": "$gcc",
+                "owner": "gcc",
+                "fileLocation": [
+                    "relative",
+                    "${workspaceFolder}"
+                ]
+            },
+            "group": {
+                "kind": "build",
+                "isDefault": true
+            }
+        },
         {
             "label": "clean",
             "type":"shell",
@@ -46,6 +64,40 @@
                 "kind": "build",
                 "isDefault": true
             }
+        },
+        {
+            "label": "distclean",
+            "type":"shell",
+            "command": "make distclean",
+            "problemMatcher": {
+                "base": "$gcc",
+                "owner": "gcc",
+                "fileLocation": [
+                    "relative",
+                    "${workspaceFolder}"
+                ]
+            },
+            "group": {
+                "kind": "build",
+                "isDefault": true
+            }
+        },
+        {
+            "label": "check",
+            "type":"shell",
+            "command": "make check",
+            "problemMatcher": {
+                "base": "$gcc",
+                "owner": "gcc",
+                "fileLocation": [
+                    "relative",
+                    "${workspaceFolder}"
+                ]
+            },
+            "group": {
+                "kind": "build",
+                "isDefault": true
+            }
         }
     ]
 }

Core/Inc/main.h

@@ -0,0 +1,77 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.h
+  * @brief          : Header for main.c file.
+  *                   This file contains the common defines of the application.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define USART2_TX_Pin GPIO_PIN_2
+#define USART2_TX_GPIO_Port GPIOA
+#define USART2_RX_Pin GPIO_PIN_15
+#define USART2_RX_GPIO_Port GPIOA
+#define LED_GREEN_Pin GPIO_PIN_6
+#define LED_GREEN_GPIO_Port GPIOC
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Core/Inc/stm32g0xx_hal_conf.h

@@ -0,0 +1,352 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_CONF_H
+#define STM32G0xx_HAL_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+/* #define HAL_ADC_MODULE_ENABLED   */
+/* #define HAL_CEC_MODULE_ENABLED   */
+/* #define HAL_COMP_MODULE_ENABLED   */
+/* #define HAL_CRC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_DAC_MODULE_ENABLED   */
+/* #define HAL_EXTI_MODULE_ENABLED   */
+/* #define HAL_FDCAN_MODULE_ENABLED   */
+/* #define HAL_HCD_MODULE_ENABLED   */
+#define HAL_I2C_MODULE_ENABLED
+/* #define HAL_I2S_MODULE_ENABLED   */
+/* #define HAL_IWDG_MODULE_ENABLED   */
+/* #define HAL_IRDA_MODULE_ENABLED   */
+/* #define HAL_LPTIM_MODULE_ENABLED   */
+/* #define HAL_PCD_MODULE_ENABLED   */
+/* #define HAL_RNG_MODULE_ENABLED   */
+/* #define HAL_RTC_MODULE_ENABLED   */
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
+/* #define HAL_SMBUS_MODULE_ENABLED   */
+/* #define HAL_SPI_MODULE_ENABLED   */
+/* #define HAL_TIM_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED   */
+/* #define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## Register Callbacks selection ############################## */
+/**
+  * @brief This is the list of modules where register callback can be used
+  */
+#define USE_HAL_ADC_REGISTER_CALLBACKS    0u
+#define USE_HAL_CEC_REGISTER_CALLBACKS    0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS   0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS   0u
+#define USE_HAL_DAC_REGISTER_CALLBACKS    0u
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS  0u
+#define USE_HAL_HCD_REGISTER_CALLBACKS    0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS    0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS    0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS   0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS  0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS    0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS    0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS    0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS  0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS    0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS    0u
+#define USE_HAL_UART_REGISTER_CALLBACKS   0u
+#define USE_HAL_USART_REGISTER_CALLBACKS  0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS   0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    (8000000UL)         /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT    (100UL)         /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    (16000000UL)            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
+/**
+  * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
+  *        This internal oscillator is mainly dedicated to provide a high precision clock to
+  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
+  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
+  *        which is subject to manufacturing process variations.
+  */
+#if !defined  (HSI48_VALUE)
+  #define HSI48_VALUE   48000000U             /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
+                                               The real value my vary depending on manufacturing process variations.*/
+#endif /* HSI48_VALUE */
+#endif
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE  (32000UL)                /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+The real value may vary depending on the variations
+in voltage and temperature.*/
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    (32768UL)               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    (5000UL)      /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S1 peripheral
+  *        This value is used by the RCC HAL module to compute the I2S1 clock source
+  *        frequency.
+  */
+#if !defined  (EXTERNAL_I2S1_CLOCK_VALUE)
+#define EXTERNAL_I2S1_CLOCK_VALUE    (12288000UL) /*!< Value of the I2S1 External clock source in Hz*/
+#endif /* EXTERNAL_I2S1_CLOCK_VALUE */
+
+#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
+/**
+  * @brief External clock source for I2S2 peripheral
+  *        This value is used by the RCC HAL module to compute the I2S2 clock source
+  *        frequency.
+  */
+#if !defined  (EXTERNAL_I2S2_CLOCK_VALUE)
+  #define EXTERNAL_I2S2_CLOCK_VALUE    48000U /*!< Value of the I2S2 External clock source in Hz*/
+#endif /* EXTERNAL_I2S2_CLOCK_VALUE */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    (3300UL)                                        /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            0U /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                     0U
+
+/* ################## CRYP peripheral configuration ########################## */
+
+#define USE_HAL_CRYP_SUSPEND_RESUME     1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include modules header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32g0xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32g0xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32g0xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32g0xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32g0xx_hal_adc.h"
+#include "stm32g0xx_hal_adc_ex.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+#include "stm32g0xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+#include "stm32g0xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32g0xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#include "stm32g0xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#include "stm32g0xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32g0xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+#include "stm32g0xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+#include "stm32g0xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+#include "stm32g0xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32g0xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+#include "stm32g0xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32g0xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32g0xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32g0xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32g0xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32g0xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#include "stm32g0xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32g0xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32g0xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32g0xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32g0xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32g0xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32g0xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32g0xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32g0xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for functions parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G0xx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Core/Inc/stm32g0xx_it.h

@@ -0,0 +1,65 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_it.h
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+ ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G0xx_IT_H
+#define __STM32G0xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G0xx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Core/Src/main.c

@@ -0,0 +1,185 @@
+#include <string.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdbool.h>
+
+#include "main.h"
+
+UART_HandleTypeDef huart2;
+I2C_HandleTypeDef hi2c1;
+
+uint8_t data[2] = {0};
+
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_USART2_UART_Init(void);
+static void MX_I2C1_Init(void);
+
+
+#ifdef __GNUC__
+#define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
+#else
+#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
+#endif /* __GNUC__ */
+
+PUTCHAR_PROTOTYPE
+{
+    HAL_UART_Transmit(&huart2, (uint8_t *)&ch, 1, 0xFFFF);
+
+    return ch;
+}
+
+int main(void)
+{
+    HAL_Init();
+    SystemClock_Config();
+    MX_GPIO_Init();
+    MX_USART2_UART_Init();
+    MX_I2C1_Init();
+
+    data[0] = 1; // Config register
+    if(HAL_I2C_Master_Transmit_IT(&hi2c1, (uint16_t)(0x48 << 1), data, 1) != HAL_OK) {
+        printf("I2c tx failed.\r\n");
+    }
+    while(1) {};
+}
+
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+    if(HAL_I2C_Master_Receive_IT(&hi2c1, (uint16_t)(0x48 << 1), data, 2) != HAL_OK) {
+        printf("I2c rx failed.\r\n");
+    }
+}
+
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+    uint16_t config = (uint16_t)(data[0] << 8) | data[1];
+    printf("ADS1115 config register: 0x%04x\r\n", config);
+}
+
+void SystemClock_Config(void)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+
+    HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI;
+    RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+    RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+    RCC_OscInitStruct.PLL.PLLN = 8;
+    RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+    RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+    RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        Error_Handler();
+    }
+
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+    RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        Error_Handler();
+    }
+
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_I2C1;
+    PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
+        Error_Handler();
+    }
+}
+
+static void MX_USART2_UART_Init(void)
+{
+    huart2.Instance = USART2;
+    huart2.Init.BaudRate = 115200;
+    huart2.Init.WordLength = UART_WORDLENGTH_8B;
+    huart2.Init.StopBits = UART_STOPBITS_1;
+    huart2.Init.Parity = UART_PARITY_NONE;
+    huart2.Init.Mode = UART_MODE_TX_RX;
+    huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+    huart2.Init.OverSampling = UART_OVERSAMPLING_16;
+    huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+    huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+    huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+    if (HAL_UART_Init(&huart2) != HAL_OK) {
+        Error_Handler();
+    }
+}
+
+/**
+  * @brief I2C1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_I2C1_Init(void)
+{
+
+  /* USER CODE BEGIN I2C1_Init 0 */
+
+  /* USER CODE END I2C1_Init 0 */
+
+  /* USER CODE BEGIN I2C1_Init 1 */
+
+  /* USER CODE END I2C1_Init 1 */
+  hi2c1.Instance = I2C1;
+  hi2c1.Init.Timing = 0x10707DBC;
+  hi2c1.Init.OwnAddress1 = 0;
+  hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+  hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+  hi2c1.Init.OwnAddress2 = 0;
+  hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+  hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+  hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+  if (HAL_I2C_Init(&hi2c1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Analogue filter
+  */
+  if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Digital filter
+  */
+  if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN I2C1_Init 2 */
+
+  /* USER CODE END I2C1_Init 2 */
+
+}
+
+static void MX_GPIO_Init(void)
+{
+    GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOF_CLK_ENABLE();
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+
+    HAL_GPIO_WritePin(LED_GREEN_GPIO_Port, LED_GREEN_Pin, GPIO_PIN_RESET);
+
+    GPIO_InitStruct.Pin = LED_GREEN_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    HAL_GPIO_Init(LED_GREEN_GPIO_Port, &GPIO_InitStruct);
+}
+
+void Error_Handler(void)
+{
+    __disable_irq();
+    while (1) {
+    }
+}

Core/Src/stm32g0xx_hal_msp.c

@@ -0,0 +1,61 @@
+#include "main.h"
+
+void HAL_MspInit(void)
+{
+    __HAL_RCC_SYSCFG_CLK_ENABLE();
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    HAL_SYSCFG_StrobeDBattpinsConfig(SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE);
+}
+
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+    GPIO_InitTypeDef GPIO_InitStruct = {0};
+    if(huart->Instance == USART2) {
+        __HAL_RCC_USART2_CLK_ENABLE();
+
+        __HAL_RCC_GPIOA_CLK_ENABLE();
+        GPIO_InitStruct.Pin = USART2_TX_Pin | USART2_RX_Pin;
+        GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+        GPIO_InitStruct.Pull = GPIO_PULLUP;
+        GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+        GPIO_InitStruct.Alternate = GPIO_AF1_USART2;
+        HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+    }
+}
+
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+    if(huart->Instance == USART2) {
+        __HAL_RCC_USART2_CLK_DISABLE();
+
+        HAL_GPIO_DeInit(GPIOA, USART2_TX_Pin | USART2_RX_Pin);
+    }
+}
+
+void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
+{
+    GPIO_InitTypeDef GPIO_InitStruct = {0};
+    if(hi2c->Instance == I2C1) {
+        __HAL_RCC_GPIOA_CLK_ENABLE();
+        GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
+        GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+        GPIO_InitStruct.Pull = GPIO_PULLUP;
+        GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+        GPIO_InitStruct.Alternate = GPIO_AF6_I2C1;
+        HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+        __HAL_RCC_I2C1_CLK_ENABLE();
+        HAL_NVIC_SetPriority(I2C1_IRQn, 0, 0);
+        HAL_NVIC_EnableIRQ(I2C1_IRQn);
+    }
+}
+
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
+{
+    if(hi2c->Instance == I2C1) {
+        __HAL_RCC_I2C1_CLK_DISABLE();
+        HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9);
+        HAL_GPIO_DeInit(GPIOA, GPIO_PIN_10);
+        HAL_NVIC_DisableIRQ(I2C1_IRQn);
+    }
+}

Core/Src/stm32g0xx_it.c

@@ -0,0 +1,36 @@
+#include "main.h"
+#include "stm32g0xx_it.h"
+
+extern I2C_HandleTypeDef hi2c1;
+
+void NMI_Handler(void)
+{
+    while (1) {}
+}
+
+void HardFault_Handler(void)
+{
+    while (1) {}
+}
+
+void SVC_Handler(void)
+{
+}
+
+void PendSV_Handler(void)
+{
+}
+
+void SysTick_Handler(void)
+{
+    HAL_IncTick();
+}
+
+void I2C1_IRQHandler(void)
+{
+    if(hi2c1.Instance->ISR & (I2C_FLAG_BERR | I2C_FLAG_ARLO | I2C_FLAG_OVR)) {
+        HAL_I2C_ER_IRQHandler(&hi2c1);
+    } else {
+        HAL_I2C_EV_IRQHandler(&hi2c1);
+    }
+}

Core/Src/system_stm32g0xx.c

@@ -0,0 +1,96 @@
+#include "stm32g0xx.h"
+
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    (8000000UL)    /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE  (16000000UL)   /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE   (32000UL)     /*!< Value of LSI in Hz*/
+#endif /* LSI_VALUE */
+
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE  (32768UL)      /*!< Value of LSE in Hz*/
+#endif /* LSE_VALUE */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0U /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x100. */
+/* The SystemCoreClock variable is updated in three ways:
+  1) by calling CMSIS function SystemCoreClockUpdate()
+  2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+  3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+	 Note: If you use this function to configure the system clock; then there
+		   is no need to call the 2 first functions listed above, since SystemCoreClock
+		   variable is updated automatically.
+*/
+uint32_t SystemCoreClock = 16000000UL;
+
+const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};
+const uint32_t APBPrescTable[8UL] =  {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
+
+void SystemInit(void)
+{
+#ifdef VECT_TAB_SRAM
+	SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+	SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+void SystemCoreClockUpdate(void)
+{
+	uint32_t tmp;
+	uint32_t pllvco;
+	uint32_t pllr;
+	uint32_t pllsource;
+	uint32_t pllm;
+	uint32_t hsidiv;
+
+	switch (RCC->CFGR & RCC_CFGR_SWS)
+	{
+    	case RCC_CFGR_SWS_0:                /* HSE used as system clock */
+    		SystemCoreClock = HSE_VALUE;
+    		break;
+    	case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0):  /* LSI used as system clock */
+    		  SystemCoreClock = LSI_VALUE;
+    		break;
+    	case RCC_CFGR_SWS_2:                /* LSE used as system clock */
+    		SystemCoreClock = LSE_VALUE;
+    		break;
+    	case RCC_CFGR_SWS_1:  /* PLL used as system clock */
+    		/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+         	   SYSCLK = PLL_VCO / PLLR */
+    		pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+    		pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL;
+
+    		if(pllsource == 0x03UL) {
+    			/* HSE used as PLL clock source */
+    			pllvco = (HSE_VALUE / pllm);
+    		}
+    		else {
+    			/* HSI used as PLL clock source */
+    			pllvco = (HSI_VALUE / pllm);
+    		}
+    		pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+    		pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
+
+    		SystemCoreClock = pllvco/pllr;
+    		break;
+    	case 0x00000000U:                   /* HSI used as system clock */
+    	default:                            /* HSI used as system clock */
+    		hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
+    		SystemCoreClock = (HSI_VALUE/hsidiv);
+    		break;
+	}
+	/* Compute HCLK clock frequency --------------------------------------------*/
+	/* Get HCLK prescaler */
+	tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+	/* HCLK clock frequency */
+	SystemCoreClock >>= tmp;
+}

Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h

@@ -0,0 +1,211 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32G0xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32G0xx device used in the target application
+  *              - To use or not the peripherals drivers in application code(i.e.
+  *                code will be based on direct access to peripherals registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32g0xx
+  * @{
+  */
+
+#ifndef STM32G0xx_H
+#define STM32G0xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32G0)
+#define STM32G0
+#endif /* STM32G0 */
+
+/* Uncomment the line below according to the target STM32G0 device used in your
+   application
+  */
+
+#if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) \
+ && !defined (STM32G030xx) && !defined (STM32G031xx) && !defined (STM32G041xx) \
+ && !defined (STM32G0B0xx) && !defined (STM32G0B1xx) && !defined (STM32G0C1xx) \
+ && !defined (STM32G050xx) && !defined (STM32G051xx) && !defined (STM32G061xx)
+  /* #define STM32G0B0xx */   /*!< STM32G0B0xx Devices */
+  /* #define STM32G0B1xx */   /*!< STM32G0B1xx Devices */
+  /* #define STM32G0C1xx */   /*!< STM32G0C1xx Devices */
+  /* #define STM32G070xx */   /*!< STM32G070xx Devices */
+  /* #define STM32G071xx */   /*!< STM32G071xx Devices */
+  /* #define STM32G081xx */   /*!< STM32G081xx Devices */
+  /* #define STM32G050xx */   /*!< STM32G050xx Devices */
+  /* #define STM32G051xx */   /*!< STM32G051xx Devices */
+  /* #define STM32G061xx */   /*!< STM32G061xx Devices */
+  /* #define STM32G030xx */   /*!< STM32G030xx Devices */
+  /* #define STM32G031xx */   /*!< STM32G031xx Devices */
+  /* #define STM32G041xx */   /*!< STM32G041xx Devices */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number $VERSION$
+  */
+#define __STM32G0_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
+#define __STM32G0_CMSIS_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
+#define __STM32G0_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
+#define __STM32G0_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32G0_CMSIS_VERSION        ((__STM32G0_CMSIS_VERSION_MAIN << 24)\
+                                       |(__STM32G0_CMSIS_VERSION_SUB1 << 16)\
+                                       |(__STM32G0_CMSIS_VERSION_SUB2 << 8 )\
+                                       |(__STM32G0_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32G0B1xx)
+  #include "stm32g0b1xx.h"
+#elif defined(STM32G0C1xx)
+  #include "stm32g0c1xx.h"
+#elif defined(STM32G0B0xx)
+  #include "stm32g0b0xx.h"
+#elif defined(STM32G071xx)
+  #include "stm32g071xx.h"
+#elif defined(STM32G081xx)
+  #include "stm32g081xx.h"
+#elif defined(STM32G070xx)
+  #include "stm32g070xx.h"
+#elif defined(STM32G031xx)
+  #include "stm32g031xx.h"
+#elif defined(STM32G041xx)
+  #include "stm32g041xx.h"
+#elif defined(STM32G030xx)
+  #include "stm32g030xx.h"
+#elif defined(STM32G051xx)
+  #include "stm32g051xx.h"
+#elif defined(STM32G061xx)
+  #include "stm32g061xx.h"
+#elif defined(STM32G050xx)
+  #include "stm32g050xx.h"
+#else
+ #error "Please select first the target STM32G0xx device used in your application (in stm32g0xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  SUCCESS = 0,
+  ERROR = !SUCCESS
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/*#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))*/
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32g0xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32G0xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h

@@ -0,0 +1,839 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for the HAL
+  *          module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_H
+#define STM32G0xx_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal_conf.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL HAL
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+  * @{
+  */
+typedef enum
+{
+  HAL_TICK_FREQ_10HZ         = 100U,
+  HAL_TICK_FREQ_100HZ        = 10U,
+  HAL_TICK_FREQ_1KHZ         = 1U,
+  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+  * @{
+  */
+
+/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
+  * @{
+  */
+
+/** @defgroup SYSCFG_BootMode Boot Mode
+  * @{
+  */
+#define SYSCFG_BOOT_MAINFLASH          0x00000000U                      /*!< Main Flash memory mapped at 0x0000 0000   */
+#define SYSCFG_BOOT_SYSTEMFLASH        SYSCFG_CFGR1_MEM_MODE_0          /*!< System Flash memory mapped at 0x0000 0000 */
+#define SYSCFG_BOOT_SRAM               (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0)  /*!< Embedded SRAM mapped at 0x0000 0000 */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Break Break
+  * @{
+  */
+#define SYSCFG_BREAK_SP                SYSCFG_CFGR2_SPL    /*!< Enables and locks the SRAM Parity error signal with Break Input of TIM1/15/16/17 */
+#if defined(SYSCFG_CFGR2_PVDL)
+#define SYSCFG_BREAK_PVD               SYSCFG_CFGR2_PVDL   /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
+#endif /* SYSCFG_CFGR2_PVDL */
+#define SYSCFG_BREAK_LOCKUP            SYSCFG_CFGR2_CLL    /*!< Enables and locks the LOCKUP output of CortexM0+ with Break Input of TIM1/15/16/17 */
+#define SYSCFG_BREAK_ECC               SYSCFG_CFGR2_ECCL   /*!< Enables and locks the ECC of CortexM0+ with Break Input of TIM1/15/16/17 */
+/**
+  * @}
+  */
+
+#if defined(SYSCFG_CDEN_SUPPORT)
+/** @defgroup SYSCFG_ClampingDiode Clamping Diode
+  * @{
+  */
+#define SYSCFG_CDEN_PA1                SYSCFG_CFGR2_PA1_CDEN    /*!< Enables Clamping Diode on PA1 */
+#define SYSCFG_CDEN_PA3                SYSCFG_CFGR2_PA3_CDEN    /*!< Enables Clamping Diode on PA3 */
+#define SYSCFG_CDEN_PA5                SYSCFG_CFGR2_PA5_CDEN    /*!< Enables Clamping Diode on PA5 */
+#define SYSCFG_CDEN_PA6                SYSCFG_CFGR2_PA6_CDEN    /*!< Enables Clamping Diode on PA6 */
+#define SYSCFG_CDEN_PA13               SYSCFG_CFGR2_PA13_CDEN   /*!< Enables Clamping Diode on PA13 */
+#define SYSCFG_CDEN_PB0                SYSCFG_CFGR2_PB0_CDEN    /*!< Enables Clamping Diode on PB0 */
+#define SYSCFG_CDEN_PB1                SYSCFG_CFGR2_PB1_CDEN    /*!< Enables Clamping Diode on PB1 */
+#define SYSCFG_CDEN_PB2                SYSCFG_CFGR2_PB2_CDEN    /*!< Enables Clamping Diode on PB2 */
+
+/**
+  * @}
+  */
+#endif /* SYSCFG_CDEN_SUPPORT */
+
+/** @defgroup HAL_Pin_remapping Pin remapping
+  * @{
+  */
+/* Only available on cut2.0 */
+#define SYSCFG_REMAP_PA11                   SYSCFG_CFGR1_PA11_RMP       /*!< PA11 pad behaves digitally as PA9 GPIO pin */
+#define SYSCFG_REMAP_PA12                   SYSCFG_CFGR1_PA12_RMP       /*!< PA12 pad behaves digitally as PA10 GPIO pin */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IR_ENV_SEL IR Modulation Envelope signal selection
+  * @{
+  */
+#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16     (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1)    /*!< 00: Timer16 is selected as IR Modulation envelope source */
+#define HAL_SYSCFG_IRDA_ENV_SEL_USART1    (SYSCFG_CFGR1_IR_MOD_0)                            /*!< 01: USART1 is selected as IR Modulation envelope source */
+#if defined(USART4)
+#define HAL_SYSCFG_IRDA_ENV_SEL_USART4    (SYSCFG_CFGR1_IR_MOD_1)                            /*!< 10: USART4 is selected as IR Modulation envelope source */
+#else
+#define HAL_SYSCFG_IRDA_ENV_SEL_USART2    (SYSCFG_CFGR1_IR_MOD_1)                            /*!< 10: USART2 is selected as IR Modulation envelope source */
+#endif /* USART4 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IR_POL_SEL IR output polarity selection
+  * @{
+  */
+#define HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED     0x00000000U                                /*!< 00: IR output polarity not inverted */
+#define HAL_SYSCFG_IRDA_POLARITY_INVERTED         SYSCFG_CFGR1_IR_POL                        /*!< 01: IR output polarity inverted */
+
+/**
+  * @}
+  */
+
+#if defined(VREFBUF)
+/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
+  * @{
+  */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0  0x00000000U            /*!< Voltage reference scale 0: VREF_OUT1 around 2.048 V.
+                                                                   This requires VDDA equal to or higher than 2.4 V.   */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1  VREFBUF_CSR_VRS        /*!< Voltage reference scale 1: VREF_OUT1 around 2.5 V.
+                                                                   This requires VDDA equal to or higher than 2.8 V.   */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
+  * @{
+  */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  0x00000000U        /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ    /*!< VREF_plus pin is high impedance */
+
+/**
+  * @}
+  */
+#endif /* VREFBUF */
+
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast mode Plus on GPIO
+  * @{
+  */
+
+/** @brief  Fast mode Plus driving capability on a specific GPIO
+  */
+#define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast mode Plus on PB6 */
+#define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast mode Plus on PB7 */
+#define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast mode Plus on PB8 */
+#define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast mode Plus on PB9 */
+#define SYSCFG_FASTMODEPLUS_PA9        SYSCFG_CFGR1_I2C_PA9_FMP  /*!< Enable Fast mode Plus on PA9 */
+#define SYSCFG_FASTMODEPLUS_PA10       SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast mode Plus on PA10 */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_FastModePlus_I2Cx Fast mode Plus driving capability activation for I2Cx
+  * @{
+  */
+
+/** @brief  Fast mode Plus driving capability on a specific GPIO
+  */
+#define SYSCFG_FASTMODEPLUS_I2C1       SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast mode Plus on I2C1 */
+#define SYSCFG_FASTMODEPLUS_I2C2       SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast mode Plus on I2C2 */
+#if  defined (I2C3)
+#define SYSCFG_FASTMODEPLUS_I2C3       SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast mode Plus on I2C3 */  
+#endif /* I2C3 */
+
+/**
+ * @}
+ */
+#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
+/** @defgroup SYSCFG_UCPDx_STROBE SYSCFG Dead Battery feature configuration
+  * @{
+  */
+#define SYSCFG_UCPD1_STROBE          SYSCFG_CFGR1_UCPD1_STROBE /*!< UCPD1 Dead battery sw configuration */
+#define SYSCFG_UCPD2_STROBE          SYSCFG_CFGR1_UCPD2_STROBE /*!< UCPD2 Dead battery sw configuration */
+/**
+  * @}
+  */
+#endif /* SYSCFG_CFGR1_UCPD1_STROBE) || SYSCFG_CFGR1_UCPD2_STROBE */
+
+/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
+  * @brief ISR Wrapper
+  * @{
+  */
+#define HAL_SYSCFG_ITLINE0                           0x00000000U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE1                           0x00000001U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE2                           0x00000002U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE3                           0x00000003U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE4                           0x00000004U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE5                           0x00000005U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE6                           0x00000006U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE7                           0x00000007U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE8                           0x00000008U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE9                           0x00000009U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE10                          0x0000000AU /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE11                          0x0000000BU /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE12                          0x0000000CU /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE13                          0x0000000DU /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE14                          0x0000000EU /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE15                          0x0000000FU /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE16                          0x00000010U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE17                          0x00000011U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE18                          0x00000012U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE19                          0x00000013U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE20                          0x00000014U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE21                          0x00000015U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE22                          0x00000016U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE23                          0x00000017U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE24                          0x00000018U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE25                          0x00000019U /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE26                          0x0000001AU /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE27                          0x0000001BU /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE28                          0x0000001CU /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE29                          0x0000001DU /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE30                          0x0000001EU /*!< Internal define for macro handling */
+#define HAL_SYSCFG_ITLINE31                          0x0000001FU /*!< Internal define for macro handling */
+
+#define HAL_ITLINE_WWDG           ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG)          /*!< WWDG has expired .... */
+#if defined (PWR_PVD_SUPPORT)
+#define HAL_ITLINE_PVDOUT         ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)        /*!< Power voltage detection Interrupt .... */
+#endif /* PWR_PVD_SUPPORT */
+#if defined (PWR_PVM_SUPPORT)
+#define HAL_ITLINE_PVMOUT         ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVMOUT)        /*!< Power voltage monitor Interrupt .... */
+#endif /* PWR_PVM_SUPPORT */
+#define HAL_ITLINE_RTC            ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC)           /*!< RTC -> exti[19] Interrupt */
+#define HAL_ITLINE_TAMPER         ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_TAMPER)        /*!< TAMPER -> exti[21] interrupt .... */
+#define HAL_ITLINE_FLASH_ECC      ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ECC)     /*!< Flash ECC Interrupt */
+#define HAL_ITLINE_FLASH_ITF      ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)     /*!< Flash ITF Interrupt */
+#define HAL_ITLINE_CLK_CTRL       ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)      /*!< CLK Control Interrupt */
+#if defined (CRS)
+#define HAL_ITLINE_CRS            ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS)           /*!< CRS Interrupt */
+#endif /*CRS  */
+#define HAL_ITLINE_EXTI0          ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)         /*!< External Interrupt 0 */
+#define HAL_ITLINE_EXTI1          ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)         /*!< External Interrupt 1 */
+#define HAL_ITLINE_EXTI2          ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)         /*!< External Interrupt 2 */
+#define HAL_ITLINE_EXTI3          ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)         /*!< External Interrupt 3 */
+#define HAL_ITLINE_EXTI4          ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)         /*!< EXTI4 Interrupt */
+#define HAL_ITLINE_EXTI5          ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)         /*!< EXTI5 Interrupt */
+#define HAL_ITLINE_EXTI6          ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)         /*!< EXTI6 Interrupt */
+#define HAL_ITLINE_EXTI7          ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)         /*!< EXTI7 Interrupt */
+#define HAL_ITLINE_EXTI8          ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)         /*!< EXTI8 Interrupt */
+#define HAL_ITLINE_EXTI9          ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)         /*!< EXTI9 Interrupt */
+#define HAL_ITLINE_EXTI10         ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)        /*!< EXTI10 Interrupt */
+#define HAL_ITLINE_EXTI11         ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)        /*!< EXTI11 Interrupt */
+#define HAL_ITLINE_EXTI12         ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)        /*!< EXTI12 Interrupt */
+#define HAL_ITLINE_EXTI13         ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)        /*!< EXTI13 Interrupt */
+#define HAL_ITLINE_EXTI14         ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)        /*!< EXTI14 Interrupt */
+#define HAL_ITLINE_EXTI15         ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)        /*!< EXTI15 Interrupt */
+#if defined (UCPD1)
+#define HAL_ITLINE_UCPD1          ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD1)         /*!< UCPD1 Interrupt */
+#endif /* UCPD1 */
+#if defined (UCPD2)
+#define HAL_ITLINE_UCPD2          ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD2)         /*!< UCPD2 Interrupt */
+#endif /* UCPD2 */
+#if defined (STM32G0C1xx) || defined (STM32G0B1xx) || defined (STM32G0B0xx)
+#define HAL_ITLINE_USB            ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_USB)           /*!< USB Interrupt */
+#endif /* STM32G0C1xx) || STM32G0B1xx) || STM32G0B0xx */
+#define HAL_ITLINE_DMA1_CH1       ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)      /*!< DMA1 Channel 1 Interrupt */
+#define HAL_ITLINE_DMA1_CH2       ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)    /*!< DMA1 Channel 2 Interrupt */
+#define HAL_ITLINE_DMA1_CH3       ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)    /*!< DMA1 Channel 3 Interrupt */
+#define HAL_ITLINE_DMAMUX1        ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMAMUX1)     /*!< DMAMUX1 Interrupt */
+#define HAL_ITLINE_DMA1_CH4       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)    /*!< DMA1 Channel 4 Interrupt */
+#define HAL_ITLINE_DMA1_CH5       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)    /*!< DMA1 Channel 5 Interrupt */
+#if defined(DMA1_Channel7)
+#define HAL_ITLINE_DMA1_CH6       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)    /*!< DMA1 Channel 6 Interrupt */
+#define HAL_ITLINE_DMA1_CH7       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)    /*!< DMA1 Channel 7 Interrupt */
+#endif /* DMA1_Channel7 */
+#if defined (DMA2)
+#define HAL_ITLINE_DMA2_CH1       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH1)    /*!< DMA2 Channel 1 Interrupt */
+#define HAL_ITLINE_DMA2_CH2       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH2)    /*!< DMA2 Channel 2 Interrupt */
+#define HAL_ITLINE_DMA2_CH3       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)    /*!< DMA2 Channel 3 Interrupt */
+#define HAL_ITLINE_DMA2_CH4       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)    /*!< DMA2 Channel 4 Interrupt */
+#define HAL_ITLINE_DMA2_CH5       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)    /*!< DMA2 Channel 5 Interrupt */
+#endif /* DMA2 */
+#define HAL_ITLINE_ADC            ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC)         /*!< ADC Interrupt */
+#if defined (COMP1)
+#define HAL_ITLINE_COMP1          ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1)       /*!< COMP1 Interrupt -> exti[17] */
+#endif /* COMP1 */
+#if defined (COMP2)
+#define HAL_ITLINE_COMP2          ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2)       /*!< COMP2 Interrupt -> exti[18] */
+#endif /* COMP2 */
+#if defined (COMP3)
+#define HAL_ITLINE_COMP3          ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP3)       /*!< COMP3 Interrupt -> exti[1x] */
+#endif /* COMP3 */
+#define HAL_ITLINE_TIM1_BRK       ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)    /*!< TIM1 BRK Interrupt */
+#define HAL_ITLINE_TIM1_UPD       ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)    /*!< TIM1 UPD Interrupt */
+#define HAL_ITLINE_TIM1_TRG       ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)    /*!< TIM1 TRG Interrupt */
+#define HAL_ITLINE_TIM1_CCU       ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)    /*!< TIM1 CCU Interrupt */
+#define HAL_ITLINE_TIM1_CC        ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)     /*!< TIM1 CC Interrupt */
+#if defined (TIM2)
+#define HAL_ITLINE_TIM2           ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)    /*!< TIM2 Interrupt */
+#endif /* TIM2 */
+#define HAL_ITLINE_TIM3           ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)    /*!< TIM3 Interrupt */
+#if defined (TIM4)
+#define HAL_ITLINE_TIM4           ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM4_GLB)    /*!< TIM4 Interrupt */
+#endif /* TIM4 */
+#if defined(TIM6)
+#define HAL_ITLINE_TIM6           ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)    /*!< TIM6 Interrupt */
+#endif /* TIM6 */
+#if defined(DAC1)
+#define HAL_ITLINE_DAC            ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC)         /*!< DAC Interrupt */
+#endif /* DAC1 */
+#if defined(LPTIM1)
+#define HAL_ITLINE_LPTIM1         ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_LPTIM1_GLB)  /*!< LPTIM1 Interrupt -> exti[29] */
+#endif /* LPTIM1 */
+#if defined(TIM7)
+#define HAL_ITLINE_TIM7           ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)    /*!< TIM7 Interrupt */
+#endif /* TIM7 */
+#if defined(LPTIM2)
+#define HAL_ITLINE_LPTIM2         ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_LPTIM2_GLB)  /*!< LPTIM2 Interrupt -> exti[30] */
+#endif /* LPTIM2 */
+#define HAL_ITLINE_TIM14          ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)   /*!< TIM14 Interrupt */
+#if defined(TIM15)
+#define HAL_ITLINE_TIM15          ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)   /*!< TIM15 Interrupt */
+#endif /* TIM15 */
+#define HAL_ITLINE_TIM16          ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)   /*!< TIM16 Interrupt */
+#if defined (FDCAN1) || defined (FDCAN2)
+#define HAL_ITLINE_FDCAN1_IT0     ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN1_IT0)  /*!< FDCAN1_IT0 Interrupt */
+#define HAL_ITLINE_FDCAN2_IT0     ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN2_IT0)  /*!< FDCAN2_IT0 Interrupt */
+#endif /* FDCAN1 || FDCAN2 */
+#define HAL_ITLINE_TIM17          ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)   /*!< TIM17 Interrupt */
+#if defined (FDCAN1) || defined (FDCAN2)
+#define HAL_ITLINE_FDCAN1_IT1     ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN1_IT1)  /*!< FDCAN1_IT1 Interrupt */
+#define HAL_ITLINE_FDCAN2_IT1     ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN2_IT1)  /*!< FDCAN2_IT1 Interrupt */
+#endif /* FDCAN1 || FDCAN2 */
+#define HAL_ITLINE_I2C1           ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)    /*!< I2C1 Interrupt -> exti[23] */
+#define HAL_ITLINE_I2C2           ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)    /*!< I2C2 Interrupt -> exti[24] */
+#if defined (I2C3)
+#define HAL_ITLINE_I2C3           ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C3_GLB)    /*!< I2C3 Interrupt -> exti[22] */
+#endif /* I2C3 */
+#define HAL_ITLINE_SPI1           ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1)        /*!< SPI1 Interrupt  */
+#define HAL_ITLINE_SPI2           ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2)        /*!< SPI2 Interrupt */
+#if defined (SPI3)
+#define HAL_ITLINE_SPI3           ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI3)        /*!< SPI3 Interrupt */
+#endif /* SPI3 */
+#define HAL_ITLINE_USART1         ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)  /*!< USART1 GLB Interrupt -> exti[25] */
+#define HAL_ITLINE_USART2         ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)  /*!< USART2 GLB Interrupt -> exti[26] */
+#if defined (LPUART2)
+#define HAL_ITLINE_LPUART2        ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_LPUART2_GLB)  /*!< LPUART2 GLB Interrupt -> exti[26] */
+#endif /* LPUART2 */
+#if defined(USART3)
+#define HAL_ITLINE_USART3         ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)  /*!< USART3 Interrupt .... */
+#endif /* USART3 */
+#if defined(USART4)
+#define HAL_ITLINE_USART4         ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)  /*!< USART4 Interrupt .... */
+#endif /* USART4 */
+#if defined (LPUART1)
+#define HAL_ITLINE_LPUART1        ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_LPUART1_GLB) /*!< LPUART1 Interrupt -> exti[28]*/
+#endif /* LPUART1 */
+#if defined (USART5)
+#define HAL_ITLINE_USART5         ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)  /*!< USART5 Interrupt .... */
+#endif /* USART5 */
+#if defined (USART6)
+#define HAL_ITLINE_USART6         ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)  /*!< USART6 Interrupt .... */
+#endif /* USART6 */
+#if defined (CEC)
+#define HAL_ITLINE_CEC            ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC)         /*!< CEC Interrupt -> exti[27] */
+#endif /* CEC */
+#if defined (RNG)
+#define HAL_ITLINE_RNG            ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_RNG)         /*!< RNG Interrupt */
+#endif /* RNG */
+#if defined (AES)
+#define HAL_ITLINE_AES            ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_AES)         /*!< AES Interrupt */
+#endif /* AES */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+  * @{
+  */
+
+/** @defgroup DBG_Exported_Macros DBG Exported Macros
+  * @{
+  */
+
+/** @brief  Freeze and Unfreeze Peripherals in Debug mode
+  */
+#if defined(DBG_APB_FZ1_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM2()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM2()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP)
+#endif /* DBG_APB_FZ1_DBG_TIM2_STOP */
+
+#if defined(DBG_APB_FZ1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM3()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM3()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)
+#endif /* DBG_APB_FZ1_DBG_TIM3_STOP */
+
+#if defined(DBG_APB_FZ1_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM4()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM4()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP)
+#endif /* DBG_APB_FZ1_DBG_TIM4_STOP */
+
+#if defined(DBG_APB_FZ1_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM6()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM6()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP)
+#endif /* DBG_APB_FZ1_DBG_TIM6_STOP */
+
+#if defined(DBG_APB_FZ1_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM7()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM7()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP)
+#endif /* DBG_APB_FZ1_DBG_TIM7_STOP */
+
+#if defined(DBG_APB_FZ1_DBG_RTC_STOP)
+#define __HAL_DBGMCU_FREEZE_RTC()            SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)
+#define __HAL_DBGMCU_UNFREEZE_RTC()          CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)
+#endif /* DBG_APB_FZ1_DBG_RTC_STOP */
+
+#if defined(DBG_APB_FZ1_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_WWDG()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_WWDG()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)
+#endif /* DBG_APB_FZ1_DBG_WWDG_STOP */
+
+#if defined(DBG_APB_FZ1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_IWDG()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_IWDG()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)
+#endif /* DBG_APB_FZ1_DBG_IWDG_STOP */
+
+#if defined(DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
+#endif /* DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP */
+
+#if defined(DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)
+#endif /* DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP */
+
+#if defined(DBG_APB_FZ1_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM1()         SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM1()       CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP)
+#endif /* DBG_APB_FZ1_DBG_LPTIM1_STOP */
+
+#if defined(DBG_APB_FZ1_DBG_LPTIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM2()         SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM2()       CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP)
+#endif /* DBG_APB_FZ1_DBG_LPTIM2_STOP */
+
+#if defined(DBG_APB_FZ2_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM1()           SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM1()         CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)
+#endif /* DBG_APB_FZ2_DBG_TIM1_STOP */
+
+#if defined(DBG_APB_FZ2_DBG_TIM14_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM14()          SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM14()        CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)
+#endif /* DBG_APB_FZ2_DBG_TIM14_STOP */
+
+#if defined(DBG_APB_FZ2_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM15()          SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM15()        CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP)
+#endif /* DBG_APB_FZ2_DBG_TIM15_STOP */
+
+#if defined(DBG_APB_FZ2_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM16()          SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM16()        CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)
+#endif /* DBG_APB_FZ2_DBG_TIM16_STOP */
+
+#if defined(DBG_APB_FZ2_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM17()          SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM17()        CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)
+#endif /* DBG_APB_FZ2_DBG_TIM17_STOP */
+    
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
+  * @{
+  */
+
+/**
+  * @brief ISR wrapper check
+  * @note Allow to determine interrupt source per line.
+  */
+#define __HAL_GET_PENDING_IT(__SOURCE__)     (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF))
+    
+/** @brief  Main Flash memory mapped at 0x00000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_FLASH()     CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
+
+/** @brief  System Flash memory mapped at 0x00000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0)
+
+/** @brief  Embedded SRAM mapped at 0x00000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_SRAM() \
+  MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, (SYSCFG_CFGR1_MEM_MODE_1|SYSCFG_CFGR1_MEM_MODE_0))
+
+/**
+  * @brief  Return the boot mode as configured by user.
+  * @retval The boot mode as configured by user. The returned value can be one
+  *         of the following values @ref SYSCFG_BootMode
+  */
+#define __HAL_SYSCFG_GET_BOOT_MODE()           READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
+
+/** @brief  SYSCFG Break ECC lock.
+  *         Enable and lock the connection of Flash ECC error connection to TIM1 Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_ECC_LOCK()           SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
+
+
+/** @brief  SYSCFG Break Cortex-M0+ Lockup lock.
+  *         Enables and locks the connection of Cortex-M0+ LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
+
+#if defined(SYSCFG_CFGR2_PVDL)
+/** @brief  SYSCFG Break PVD lock.
+  *         Enables and locks the PVD connection with Timer1/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register
+  * @note   The selected configuration is locked and can be unlocked only by system reset
+  */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK()           SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
+#endif /* SYSCFG_CFGR2_PVDL */
+
+/** @brief  SYSCFG Break SRAM PARITY lock
+  *         Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/15/16/17
+  * @note   The selected configuration is locked and can only be unlocked by system reset
+  */
+#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK()    SET_BIT(SYSCFG->CFGR2,SYSCFG_CFGR2_SPL)
+
+/** @brief  Parity check on RAM disable macro
+  * @note   Disabling the parity check on RAM locks the configuration bit.
+  *         To re-enable the parity check on RAM perform a system reset.
+  */
+#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE()  (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SPF)
+
+/** @brief  Set the PEF bit to clear the SRAM Parity Error Flag.
+  */
+#define __HAL_SYSCFG_CLEAR_FLAG()               SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
+
+/** @brief  Fast-mode Plus driving capability enable/disable macros
+  * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO
+  */
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+                                                               }while(0U)
+
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+                                                               }while(0U)
+
+#if defined(SYSCFG_CDEN_SUPPORT)
+/** @brief  Clamping Diode on specific pins enable/disable macros
+  * @param __PIN__ This parameter can be a combination of values @ref SYSCFG_ClampingDiode
+  */
+#define __HAL_SYSCFG_CLAMPINGDIODE_ENABLE(__PIN__)  do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\
+                                                                SET_BIT(SYSCFG->CFGR2, (__PIN__));\
+                                                               }while(0U)
+
+#define __HAL_SYSCFG_CLAMPINGDIODE_DISABLE(__PIN__) do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\
+                                                                CLEAR_BIT(SYSCFG->CFGR2, (__PIN__));\
+                                                               }while(0U)
+#endif /* SYSCFG_CDEN_SUPPORT */
+
+/** @brief  ISR wrapper check
+  * @note Allow to determine interrupt source per line.
+  */
+#define __HAL_SYSCFG_GET_PENDING_IT(__SOURCE__)  \
+  (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFFU))
+
+/** @brief  selection of the modulation envelope signal macro, using bits [7:6] of SYSCFG_CFGR1 register
+  * @param __SOURCE__ This parameter can be a value of @ref HAL_IR_ENV_SEL
+  */
+#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__)  do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__)));\
+                                                         CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD);\
+                                                         SET_BIT(SYSCFG->CFGR1, (__SOURCE__));\
+                                                        }while(0U)
+
+#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION()  ((SYSCFG->CFGR1) & 0x000000C0U)
+
+/** @brief  IROut Polarity Selection, using bit[5] of SYSCFG_CFGR1 register
+  * @param __SEL__ This parameter can be a value of @ref HAL_IR_POL_SEL
+  */
+#define __HAL_SYSCFG_IRDA_OUT_POLARITY_SELECTION(__SEL__)  do { assert_param(IS_HAL_SYSCFG_IRDA_POL_SEL((__SEL__)));\
+                                                                CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL);\
+                                                                SET_BIT(SYSCFG->CFGR1,(__SEL__));\
+                                                              }while(0U)
+
+/**
+  * @brief  Return the IROut Polarity mode as configured by user.
+  * @retval The IROut polarity as configured by user. The returned value can be one
+  *         of @ref HAL_IR_POL_SEL
+  */
+#define __HAL_SYSCFG_GET_POLARITY()           READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL)
+
+/** @brief  Break input to TIM1/15/16/17 capability enable/disable macros
+  * @param __BREAK__ This parameter can be a value of @ref SYSCFG_Break
+  */
+#define __HAL_SYSCFG_BREAK_ENABLE(__BREAK__)     do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\
+                                                     SET_BIT(SYSCFG->CFGR2, (__BREAK__));\
+                                                    }while(0U)
+
+#define __HAL_SYSCFG_BREAK_DISABLE(__BREAK__)    do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\
+                                                     CLEAR_BIT(SYSCFG->CFGR2, (__BREAK__));\
+                                                    }while(0U)
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
+  * @{
+  */
+#if defined (PWR_PVD_SUPPORT)
+#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_SP)        || \
+                                            ((__CONFIG__) == SYSCFG_BREAK_PVD)       || \
+                                            ((__CONFIG__) == SYSCFG_BREAK_ECC)       || \
+                                            ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
+#else
+#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_SP)        || \
+                                            ((__CONFIG__) == SYSCFG_BREAK_ECC)       || \
+                                            ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
+#endif /* PWR_PVD_SUPPORT */
+
+#if defined(SYSCFG_CDEN_SUPPORT)
+#define IS_SYSCFG_CLAMPINGDIODE(__PIN__) ((((__PIN__) & SYSCFG_CDEN_PA1)  == SYSCFG_CDEN_PA1)  || \
+                                          (((__PIN__) & SYSCFG_CDEN_PA3)  == SYSCFG_CDEN_PA3)  || \
+                                          (((__PIN__) & SYSCFG_CDEN_PA5)  == SYSCFG_CDEN_PA5)  || \
+                                          (((__PIN__) & SYSCFG_CDEN_PA6)  == SYSCFG_CDEN_PA6)  || \
+                                          (((__PIN__) & SYSCFG_CDEN_PA13) == SYSCFG_CDEN_PA13) || \
+                                          (((__PIN__) & SYSCFG_CDEN_PB0)  == SYSCFG_CDEN_PB0)  || \
+                                          (((__PIN__) & SYSCFG_CDEN_PB1)  == SYSCFG_CDEN_PB1)  || \
+                                          (((__PIN__) & SYSCFG_CDEN_PB2)  == SYSCFG_CDEN_PB2))
+#endif /* SYSCFG_CDEN_SUPPORT */
+
+#if defined (USART4)
+#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL)   (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16)   || \
+                                           ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1)  || \
+                                           ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
+#else
+#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL)   (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16)   || \
+                                           ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1)  || \
+                                           ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART2))
+#endif /* USART4 */
+#define IS_HAL_SYSCFG_IRDA_POL_SEL(SEL)   (((SEL) == HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED)   || \
+                                           ((SEL) == HAL_SYSCFG_IRDA_POLARITY_INVERTED))
+
+#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
+#define IS_SYSCFG_DBATT_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_UCPD1_STROBE) || \
+                                            ((__CONFIG__) == SYSCFG_UCPD2_STROBE) || \
+                                            ((__CONFIG__) == (SYSCFG_UCPD1_STROBE | SYSCFG_UCPD2_STROBE)))
+#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
+#if defined(VREFBUF)
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
+
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
+                                                      ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
+
+#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
+#endif /* VREFBUF */
+
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9)  == SYSCFG_FASTMODEPLUS_PA9)  || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6)  == SYSCFG_FASTMODEPLUS_PB6)  || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7)  == SYSCFG_FASTMODEPLUS_PB7)  || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8)  == SYSCFG_FASTMODEPLUS_PB8)  || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9)  == SYSCFG_FASTMODEPLUS_PB9))
+
+#define IS_HAL_REMAP_PIN(RMP)               (((RMP) == SYSCFG_REMAP_PA11) || \
+                                             ((RMP) == SYSCFG_REMAP_PA12) || \
+                                             ((RMP) == (SYSCFG_REMAP_PA11 | SYSCFG_REMAP_PA12)))
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Private_Macros HAL Private Macros
+  * @{
+  */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
+                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+                           ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+  * @{
+  */
+
+/** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions
+  * @{
+  */
+
+/* Initialization and Configuration functions  ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group3 DBGMCU Control functions
+  * @{
+  */
+
+/* DBGMCU Peripheral Control functions  *****************************************/
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+
+/**
+  * @}
+  */
+
+/* Exported variables ---------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Variables
+  * @{
+  */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group4 SYSCFG configuration functions
+  * @{
+  */
+
+/* SYSCFG Control functions  ****************************************************/
+
+#if defined(VREFBUF)
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
+void HAL_SYSCFG_DisableVREFBUF(void);
+#endif /* VREFBUF */
+
+void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
+void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
+void HAL_SYSCFG_EnableRemap(uint32_t PinRemap);
+void HAL_SYSCFG_DisableRemap(uint32_t PinRemap);
+#if defined(SYSCFG_CDEN_SUPPORT)
+void HAL_SYSCFG_EnableClampingDiode(uint32_t PinConfig);
+void HAL_SYSCFG_DisableClampingDiode(uint32_t PinConfig);
+#endif /* SYSCFG_CDEN_SUPPORT */
+#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
+void HAL_SYSCFG_StrobeDBattpinsConfig(uint32_t ConfigDeadBattery);
+#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G0xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h

@@ -0,0 +1,387 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_CORTEX_H
+#define STM32G0xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal_def.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX CORTEX
+  * @brief CORTEX HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
+  * @{
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+  * @brief  MPU Region initialization structure
+  * @{
+  */
+typedef struct
+{
+  uint8_t Enable;                /*!< Specifies the status of the region.
+                                      This parameter can be a value of @ref CORTEX_MPU_Region_Enable                */
+  uint8_t Number;                /*!< Specifies the number of the region to protect.
+                                      This parameter can be a value of @ref CORTEX_MPU_Region_Number                */
+  uint32_t BaseAddress;          /*!< Specifies the base address of the region to protect.
+                                                                                                                    */
+  uint8_t Size;                  /*!< Specifies the size of the region to protect.
+                                      This parameter can be a value of @ref CORTEX_MPU_Region_Size                  */
+  uint8_t SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF   */
+  uint8_t TypeExtField;          /*!< Specifies the TEX field level.
+                                      This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                   */
+  uint8_t AccessPermission;      /*!< Specifies the region access permission type.
+                                      This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
+  uint8_t DisableExec;           /*!< Specifies the instruction access status.
+                                      This parameter can be a value of @ref CORTEX_MPU_Instruction_Access           */
+  uint8_t IsShareable;           /*!< Specifies the shareability status of the protected region.
+                                      This parameter can be a value of @ref CORTEX_MPU_Access_Shareable             */
+  uint8_t IsCacheable;           /*!< Specifies the cacheable status of the region protected.
+                                      This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable             */
+  uint8_t IsBufferable;          /*!< Specifies the bufferable status of the protected region.
+                                      This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable            */
+} MPU_Region_InitTypeDef;
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
+  * @{
+  */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8       0x00000000U
+#define SYSTICK_CLKSOURCE_HCLK            0x00000004U
+
+/**
+  * @}
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
+  * @{
+  */
+#define  MPU_HFNMI_PRIVDEF_NONE           0x00000000U
+#define  MPU_HARDFAULT_NMI                (MPU_CTRL_HFNMIENA_Msk)
+#define  MPU_PRIVILEGED_DEFAULT           (MPU_CTRL_PRIVDEFENA_Msk)
+#define  MPU_HFNMI_PRIVDEF                (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+  * @{
+  */
+#define  MPU_REGION_ENABLE                ((uint8_t)0x01)
+#define  MPU_REGION_DISABLE               ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+  * @{
+  */
+#define  MPU_INSTRUCTION_ACCESS_ENABLE    ((uint8_t)0x00)
+#define  MPU_INSTRUCTION_ACCESS_DISABLE   ((uint8_t)0x01)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+  * @{
+  */
+#define  MPU_ACCESS_SHAREABLE             ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_SHAREABLE         ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+  * @{
+  */
+#define  MPU_ACCESS_CACHEABLE             ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_CACHEABLE         ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+  * @{
+  */
+#define  MPU_ACCESS_BUFFERABLE            ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_BUFFERABLE        ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
+  * @{
+  */
+#define  MPU_TEX_LEVEL0                   ((uint8_t)0x00)
+#define  MPU_TEX_LEVEL1                   ((uint8_t)0x01)
+#define  MPU_TEX_LEVEL2                   ((uint8_t)0x02)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+  * @{
+  */
+#define   MPU_REGION_SIZE_256B            ((uint8_t)0x07)
+#define   MPU_REGION_SIZE_512B            ((uint8_t)0x08)
+#define   MPU_REGION_SIZE_1KB             ((uint8_t)0x09)
+#define   MPU_REGION_SIZE_2KB             ((uint8_t)0x0A)
+#define   MPU_REGION_SIZE_4KB             ((uint8_t)0x0B)
+#define   MPU_REGION_SIZE_8KB             ((uint8_t)0x0C)
+#define   MPU_REGION_SIZE_16KB            ((uint8_t)0x0D)
+#define   MPU_REGION_SIZE_32KB            ((uint8_t)0x0E)
+#define   MPU_REGION_SIZE_64KB            ((uint8_t)0x0F)
+#define   MPU_REGION_SIZE_128KB           ((uint8_t)0x10)
+#define   MPU_REGION_SIZE_256KB           ((uint8_t)0x11)
+#define   MPU_REGION_SIZE_512KB           ((uint8_t)0x12)
+#define   MPU_REGION_SIZE_1MB             ((uint8_t)0x13)
+#define   MPU_REGION_SIZE_2MB             ((uint8_t)0x14)
+#define   MPU_REGION_SIZE_4MB             ((uint8_t)0x15)
+#define   MPU_REGION_SIZE_8MB             ((uint8_t)0x16)
+#define   MPU_REGION_SIZE_16MB            ((uint8_t)0x17)
+#define   MPU_REGION_SIZE_32MB            ((uint8_t)0x18)
+#define   MPU_REGION_SIZE_64MB            ((uint8_t)0x19)
+#define   MPU_REGION_SIZE_128MB           ((uint8_t)0x1A)
+#define   MPU_REGION_SIZE_256MB           ((uint8_t)0x1B)
+#define   MPU_REGION_SIZE_512MB           ((uint8_t)0x1C)
+#define   MPU_REGION_SIZE_1GB             ((uint8_t)0x1D)
+#define   MPU_REGION_SIZE_2GB             ((uint8_t)0x1E)
+#define   MPU_REGION_SIZE_4GB             ((uint8_t)0x1F)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+  * @{
+  */
+#define  MPU_REGION_NO_ACCESS             ((uint8_t)0x00)
+#define  MPU_REGION_PRIV_RW               ((uint8_t)0x01)
+#define  MPU_REGION_PRIV_RW_URO           ((uint8_t)0x02)
+#define  MPU_REGION_FULL_ACCESS           ((uint8_t)0x03)
+#define  MPU_REGION_PRIV_RO               ((uint8_t)0x05)
+#define  MPU_REGION_PRIV_RO_URO           ((uint8_t)0x06)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+  * @{
+  */
+#define  MPU_REGION_NUMBER0               ((uint8_t)0x00)
+#define  MPU_REGION_NUMBER1               ((uint8_t)0x01)
+#define  MPU_REGION_NUMBER2               ((uint8_t)0x02)
+#define  MPU_REGION_NUMBER3               ((uint8_t)0x03)
+#define  MPU_REGION_NUMBER4               ((uint8_t)0x04)
+#define  MPU_REGION_NUMBER5               ((uint8_t)0x05)
+#define  MPU_REGION_NUMBER6               ((uint8_t)0x06)
+#define  MPU_REGION_NUMBER7               ((uint8_t)0x07)
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
+ *  @brief    Initialization and Configuration functions
+ * @{
+ */
+/* Initialization and Configuration functions *****************************/
+void HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   Cortex control functions
+ * @{
+ */
+/* Peripheral Control functions *************************************************/
+uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+
+#if (__MPU_PRESENT == 1U)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+  * @{
+  */
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)     ((PRIORITY) < 0x4U)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ)                   ((IRQ) > SysTick_IRQn)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE)             (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+                                                   ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1)
+#define IS_MPU_REGION_ENABLE(STATE)               (((STATE) == MPU_REGION_ENABLE) || \
+                                                   ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE)          (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+                                                   ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE)            (((STATE) == MPU_ACCESS_SHAREABLE) || \
+                                                   ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE)            (((STATE) == MPU_ACCESS_CACHEABLE) || \
+                                                   ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE)           (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+                                                   ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE)                    (((TYPE) == MPU_TEX_LEVEL0)  || \
+                                                   ((TYPE) == MPU_TEX_LEVEL1)  || \
+                                                   ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE)  (((TYPE) == MPU_REGION_NO_ACCESS)   || \
+                                                   ((TYPE) == MPU_REGION_PRIV_RW)     || \
+                                                   ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+                                                   ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+                                                   ((TYPE) == MPU_REGION_PRIV_RO)     || \
+                                                   ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER)              (((NUMBER) == MPU_REGION_NUMBER0) || \
+                                                   ((NUMBER) == MPU_REGION_NUMBER1) || \
+                                                   ((NUMBER) == MPU_REGION_NUMBER2) || \
+                                                   ((NUMBER) == MPU_REGION_NUMBER3) || \
+                                                   ((NUMBER) == MPU_REGION_NUMBER4) || \
+                                                   ((NUMBER) == MPU_REGION_NUMBER5) || \
+                                                   ((NUMBER) == MPU_REGION_NUMBER6) || \
+                                                   ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE)                  (((SIZE) == MPU_REGION_SIZE_256B)  || \
+                                                   ((SIZE) == MPU_REGION_SIZE_512B)  || \
+                                                   ((SIZE) == MPU_REGION_SIZE_1KB)   || \
+                                                   ((SIZE) == MPU_REGION_SIZE_2KB)   || \
+                                                   ((SIZE) == MPU_REGION_SIZE_4KB)   || \
+                                                   ((SIZE) == MPU_REGION_SIZE_8KB)   || \
+                                                   ((SIZE) == MPU_REGION_SIZE_16KB)  || \
+                                                   ((SIZE) == MPU_REGION_SIZE_32KB)  || \
+                                                   ((SIZE) == MPU_REGION_SIZE_64KB)  || \
+                                                   ((SIZE) == MPU_REGION_SIZE_128KB) || \
+                                                   ((SIZE) == MPU_REGION_SIZE_256KB) || \
+                                                   ((SIZE) == MPU_REGION_SIZE_512KB) || \
+                                                   ((SIZE) == MPU_REGION_SIZE_1MB)   || \
+                                                   ((SIZE) == MPU_REGION_SIZE_2MB)   || \
+                                                   ((SIZE) == MPU_REGION_SIZE_4MB)   || \
+                                                   ((SIZE) == MPU_REGION_SIZE_8MB)   || \
+                                                   ((SIZE) == MPU_REGION_SIZE_16MB)  || \
+                                                   ((SIZE) == MPU_REGION_SIZE_32MB)  || \
+                                                   ((SIZE) == MPU_REGION_SIZE_64MB)  || \
+                                                   ((SIZE) == MPU_REGION_SIZE_128MB) || \
+                                                   ((SIZE) == MPU_REGION_SIZE_256MB) || \
+                                                   ((SIZE) == MPU_REGION_SIZE_512MB) || \
+                                                   ((SIZE) == MPU_REGION_SIZE_1GB)   || \
+                                                   ((SIZE) == MPU_REGION_SIZE_2GB)   || \
+                                                   ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)      ((SUBREGION) < (uint16_t)0x00FFU)
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G0xx_HAL_CORTEX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h

@@ -0,0 +1,214 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_def.h
+  * @author  MCD Application Team
+  * @brief   This file contains HAL common defines, enumeration, macros and
+  *          structures definitions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_DEF
+#define STM32G0xx_HAL_DEF
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx.h"
+#include "Legacy/stm32_hal_legacy.h"   /* Aliases file for old names compatibility */
+#include <stddef.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  HAL Status structures definition
+  */
+typedef enum
+{
+  HAL_OK       = 0x00U,
+  HAL_ERROR    = 0x01U,
+  HAL_BUSY     = 0x02U,
+  HAL_TIMEOUT  = 0x03U
+} HAL_StatusTypeDef;
+
+/**
+  * @brief  HAL Lock structures definition
+  */
+typedef enum
+{
+  HAL_UNLOCKED = 0x00U,
+  HAL_LOCKED   = 0x01U
+} HAL_LockTypeDef;
+
+/* Exported macros -----------------------------------------------------------*/
+
+#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */
+
+#define HAL_MAX_DELAY      0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \
+                        do{                                                      \
+                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \
+                          } while(0U)
+
+/** @brief Reset the Handles State field.
+  * @param __HANDLE__ specifies the Peripheral Handle.
+  * @note  This macro can be used for the following purpose:
+  *          - When the Handle is declared as local variable; before passing it as parameter
+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+  *            to set to 0 the Handles "State" field.
+  *            Otherwise, "State" field may have any random value and the first time the function
+  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
+  *            (i.e. HAL_PPP_MspInit() will not be executed).
+  *          - When there is a need to reconfigure the low level hardware: instead of calling
+  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+  *            In this later function, when the Handles "State" field is set to 0, it will execute the function
+  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
+  * @retval None
+  */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
+
+#if (USE_RTOS == 1U)
+/* Reserved for future use */
+#error " USE_RTOS should be 0 in the current HAL release "
+#else
+#define __HAL_LOCK(__HANDLE__)                                           \
+                                do{                                        \
+                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
+                                    {                                      \
+                                       return HAL_BUSY;                    \
+                                    }                                      \
+                                    else                                   \
+                                    {                                      \
+                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
+                                    }                                      \
+                                  }while (0U)
+
+#define __HAL_UNLOCK(__HANDLE__)                                          \
+                                  do{                                       \
+                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \
+                                    }while (0U)
+#endif /* USE_RTOS */
+
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #ifndef __weak  
+    #define __weak  __attribute__((weak))
+  #endif                                
+  #ifndef __packed  
+    #define __packed  __attribute__((packed))
+  #endif 
+#elif  defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+#ifndef __weak
+#define __weak   __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+/* GNU Compiler */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+  #ifndef __ALIGN_BEGIN
+    #define __ALIGN_BEGIN
+  #endif
+  #ifndef __ALIGN_END
+    #define __ALIGN_END      __attribute__ ((aligned (4)))
+  #endif
+#elif defined   (__GNUC__) && !defined (__CC_ARM)  /* GNU Compiler */
+#ifndef __ALIGN_END
+#define __ALIGN_END    __attribute__ ((aligned (4U)))
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif /* __ALIGN_BEGIN */
+#else
+#ifndef __ALIGN_END
+#define __ALIGN_END
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+/* ARM Compiler */
+#if defined   (__CC_ARM)                           /* ARM Compiler V5 */
+#define __ALIGN_BEGIN    __align(4U)
+/* IAR Compiler */
+#elif defined (__ICCARM__)
+#define __ALIGN_BEGIN
+#endif /* __CC_ARM */
+#endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/**
+  * @brief  __RAM_FUNC definition
+  */
+#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+/* ARM Compiler V4/V5 and V6
+   --------------------------
+   RAM functions are defined using the toolchain options.
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const'
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog.
+*/
+#define __RAM_FUNC
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC __ramfunc
+
+#elif defined   (  __GNUC__  )
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC __attribute__((section(".RamFunc")))
+
+#endif
+
+/**
+  * @brief  __NOINLINE definition
+  */
+#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined   (  __GNUC__  )
+/* ARM V4/V5 and V6 & GNU Compiler
+   ------------------------------- 
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G0xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h

@@ -0,0 +1,803 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_DMA_H
+#define STM32G0xx_HAL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal_def.h"
+#include "stm32g0xx_ll_dma.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Types DMA Exported Types
+  * @{
+  */
+
+/**
+  * @brief  DMA Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Request;               /*!< Specifies the request selected for the specified channel.
+                                       This parameter can be a value of @ref DMA_request */
+
+  uint32_t Direction;             /*!< Specifies if the data will be transferred from memory to peripheral,
+                                       from memory to memory or from peripheral to memory.
+                                       This parameter can be a value of @ref DMA_Data_transfer_direction */
+
+  uint32_t PeriphInc;             /*!< Specifies whether the Peripheral address register should be incremented or not.
+                                       This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
+  uint32_t MemInc;                /*!< Specifies whether the memory address register should be incremented or not.
+                                       This parameter can be a value of @ref DMA_Memory_incremented_mode */
+
+  uint32_t PeriphDataAlignment;   /*!< Specifies the Peripheral data width.
+                                       This parameter can be a value of @ref DMA_Peripheral_data_size */
+
+  uint32_t MemDataAlignment;      /*!< Specifies the Memory data width.
+                                       This parameter can be a value of @ref DMA_Memory_data_size */
+
+  uint32_t Mode;                  /*!< Specifies the operation mode of the DMAy Channelx.
+                                       This parameter can be a value of @ref DMA_mode
+                                       @note The circular buffer mode cannot be used if the memory-to-memory
+                                             data transfer is configured on the selected Channel */
+
+  uint32_t Priority;              /*!< Specifies the software priority for the DMAy Channelx.
+                                       This parameter can be a value of @ref DMA_Priority_level */
+} DMA_InitTypeDef;
+
+/**
+  * @brief  HAL DMA State structures definition
+  */
+typedef enum
+{
+  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled    */
+  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use      */
+  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing                 */
+  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                      */
+} HAL_DMA_StateTypeDef;
+
+/**
+  * @brief  HAL DMA Error Code structure definition
+  */
+typedef enum
+{
+  HAL_DMA_FULL_TRANSFER           = 0x00U,  /*!< Full transfer     */
+  HAL_DMA_HALF_TRANSFER           = 0x01U   /*!< Half Transfer     */
+} HAL_DMA_LevelCompleteTypeDef;
+
+/**
+  * @brief  HAL DMA Callback ID structure definition
+  */
+typedef enum
+{
+  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,  /*!< Full transfer    */
+  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,  /*!< Half transfer    */
+  HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,  /*!< Error            */
+  HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,  /*!< Abort            */
+  HAL_DMA_XFER_ALL_CB_ID           = 0x04U   /*!< All              */
+
+} HAL_DMA_CallbackIDTypeDef;
+
+/**
+  * @brief  DMA handle Structure definition
+  */
+typedef struct __DMA_HandleTypeDef
+{
+  DMA_Channel_TypeDef             *Instance;                          /*!< Register base address                 */
+
+  DMA_InitTypeDef                 Init;                               /*!< DMA communication parameters          */
+
+  HAL_LockTypeDef                 Lock;                               /*!< DMA locking object                    */
+
+  __IO HAL_DMA_StateTypeDef       State;                              /*!< DMA transfer state                    */
+
+  void   *Parent;                                                     /*!< Parent object state                   */
+
+  void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma);        /*!< DMA transfer complete callback        */
+
+  void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma);    /*!< DMA Half transfer complete callback   */
+
+  void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma);       /*!< DMA transfer error callback           */
+
+  void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma);       /*!< DMA transfer abort callback           */
+
+  __IO uint32_t                   ErrorCode;                          /*!< DMA Error code                        */
+
+#if defined(DMA2)
+  DMA_TypeDef            *DmaBaseAddress;                             /*!< DMA Channel Base Address              */
+
+#endif
+  uint32_t                        ChannelIndex;                       /*!< DMA Channel Index                     */
+
+  DMAMUX_Channel_TypeDef           *DMAmuxChannel;                    /*!< Register base address                 */
+
+  DMAMUX_ChannelStatus_TypeDef     *DMAmuxChannelStatus;              /*!< DMAMUX Channels Status Base Address   */
+
+  uint32_t                         DMAmuxChannelStatusMask;           /*!< DMAMUX Channel Status Mask            */
+
+  DMAMUX_RequestGen_TypeDef        *DMAmuxRequestGen;                 /*!< DMAMUX request generator Base Address */
+
+  DMAMUX_RequestGenStatus_TypeDef  *DMAmuxRequestGenStatus;           /*!< DMAMUX request generator Address      */
+
+  uint32_t                         DMAmuxRequestGenStatusMask;        /*!< DMAMUX request generator Status mask  */
+} DMA_HandleTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+  * @{
+  */
+#define HAL_DMA_ERROR_NONE           0x00000000U       /*!< No error                                */
+#define HAL_DMA_ERROR_TE             0x00000001U       /*!< Transfer error                          */
+#define HAL_DMA_ERROR_NO_XFER        0x00000004U       /*!< Abort requested with no Xfer ongoing    */
+#define HAL_DMA_ERROR_TIMEOUT        0x00000020U       /*!< Timeout error                           */
+#define HAL_DMA_ERROR_PARAM          0x00000040U       /*!< Parameter error                         */
+#define HAL_DMA_ERROR_BUSY           0x00000080U       /*!< DMA Busy error                          */
+#define HAL_DMA_ERROR_NOT_SUPPORTED  0x00000100U       /*!< Not supported mode                      */
+#define HAL_DMA_ERROR_SYNC           0x00000200U       /*!< DMAMUX sync overrun error               */
+#define HAL_DMA_ERROR_REQGEN         0x00000400U       /*!< DMAMUX request generator overrun error  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_request DMA request
+  * @{
+  */
+#define DMA_REQUEST_MEM2MEM          LL_DMAMUX_REQ_MEM2MEM        /*!< memory to memory transfer  */
+#define DMA_REQUEST_GENERATOR0       LL_DMAMUX_REQ_GENERATOR0     /*!< DMAMUX request generator 0 */
+#define DMA_REQUEST_GENERATOR1       LL_DMAMUX_REQ_GENERATOR1     /*!< DMAMUX request generator 1 */
+#define DMA_REQUEST_GENERATOR2       LL_DMAMUX_REQ_GENERATOR2     /*!< DMAMUX request generator 2 */
+#define DMA_REQUEST_GENERATOR3       LL_DMAMUX_REQ_GENERATOR3     /*!< DMAMUX request generator 3 */
+#define DMA_REQUEST_ADC1             LL_DMAMUX_REQ_ADC1           /*!< DMAMUX ADC1 request        */
+#if defined(AES)
+#define DMA_REQUEST_AES_IN           LL_DMAMUX_REQ_AES_IN         /*!< DMAMUX AES_IN request      */
+#define DMA_REQUEST_AES_OUT          LL_DMAMUX_REQ_AES_OUT        /*!< DMAMUX AES_OUT request     */
+#endif
+#if defined(DAC1)
+#define DMA_REQUEST_DAC1_CH1         LL_DMAMUX_REQ_DAC1_CH1       /*!< DMAMUX DAC_CH1 request     */
+#define DMA_REQUEST_DAC1_CH2         LL_DMAMUX_REQ_DAC1_CH2       /*!< DMAMUX DAC_CH2 request     */
+#endif
+#define DMA_REQUEST_I2C1_RX          LL_DMAMUX_REQ_I2C1_RX        /*!< DMAMUX I2C1 RX request     */
+#define DMA_REQUEST_I2C1_TX          LL_DMAMUX_REQ_I2C1_TX        /*!< DMAMUX I2C1 TX request     */
+#define DMA_REQUEST_I2C2_RX          LL_DMAMUX_REQ_I2C2_RX        /*!< DMAMUX I2C2 RX request     */
+#define DMA_REQUEST_I2C2_TX          LL_DMAMUX_REQ_I2C2_TX        /*!< DMAMUX I2C2 TX request     */
+#if defined(LPUART1)
+#define DMA_REQUEST_LPUART1_RX       LL_DMAMUX_REQ_LPUART1_RX     /*!< DMAMUX LPUART1 RX request  */
+#define DMA_REQUEST_LPUART1_TX       LL_DMAMUX_REQ_LPUART1_TX     /*!< DMAMUX LPUART1 TX request  */
+#endif
+#define DMA_REQUEST_SPI1_RX          LL_DMAMUX_REQ_SPI1_RX        /*!< DMAMUX SPI1 RX request     */
+#define DMA_REQUEST_SPI1_TX          LL_DMAMUX_REQ_SPI1_TX        /*!< DMAMUX SPI1 TX request     */
+#define DMA_REQUEST_SPI2_RX          LL_DMAMUX_REQ_SPI2_RX        /*!< DMAMUX SPI2 RX request     */
+#define DMA_REQUEST_SPI2_TX          LL_DMAMUX_REQ_SPI2_TX        /*!< DMAMUX SPI2 TX request     */
+#define DMA_REQUEST_TIM1_CH1         LL_DMAMUX_REQ_TIM1_CH1       /*!< DMAMUX TIM1 CH1 request    */
+#define DMA_REQUEST_TIM1_CH2         LL_DMAMUX_REQ_TIM1_CH2       /*!< DMAMUX TIM1 CH2 request    */
+#define DMA_REQUEST_TIM1_CH3         LL_DMAMUX_REQ_TIM1_CH3       /*!< DMAMUX TIM1 CH3 request    */
+#define DMA_REQUEST_TIM1_CH4         LL_DMAMUX_REQ_TIM1_CH4       /*!< DMAMUX TIM1 CH4 request    */
+#define DMA_REQUEST_TIM1_TRIG_COM    LL_DMAMUX_REQ_TIM1_TRIG_COM  /*!< DMAMUX TIM1 TRIG COM request */
+#define DMA_REQUEST_TIM1_UP          LL_DMAMUX_REQ_TIM1_UP        /*!< DMAMUX TIM1 UP request     */
+#if defined(TIM2)
+#define DMA_REQUEST_TIM2_CH1         LL_DMAMUX_REQ_TIM2_CH1       /*!< DMAMUX TIM2 CH1 request    */
+#define DMA_REQUEST_TIM2_CH2         LL_DMAMUX_REQ_TIM2_CH2       /*!< DMAMUX TIM2 CH2 request    */
+#define DMA_REQUEST_TIM2_CH3         LL_DMAMUX_REQ_TIM2_CH3       /*!< DMAMUX TIM2 CH3 request    */
+#define DMA_REQUEST_TIM2_CH4         LL_DMAMUX_REQ_TIM2_CH4       /*!< DMAMUX TIM2 CH4 request    */
+#define DMA_REQUEST_TIM2_TRIG        LL_DMAMUX_REQ_TIM2_TRIG      /*!< DMAMUX TIM2 TRIG request   */
+#define DMA_REQUEST_TIM2_UP          LL_DMAMUX_REQ_TIM2_UP        /*!< DMAMUX TIM2 UP request     */
+#endif
+#define DMA_REQUEST_TIM3_CH1         LL_DMAMUX_REQ_TIM3_CH1       /*!< DMAMUX TIM3 CH1 request    */
+#define DMA_REQUEST_TIM3_CH2         LL_DMAMUX_REQ_TIM3_CH2       /*!< DMAMUX TIM3 CH2 request    */
+#define DMA_REQUEST_TIM3_CH3         LL_DMAMUX_REQ_TIM3_CH3       /*!< DMAMUX TIM3 CH3 request    */
+#define DMA_REQUEST_TIM3_CH4         LL_DMAMUX_REQ_TIM3_CH4       /*!< DMAMUX TIM3 CH4 request    */
+#define DMA_REQUEST_TIM3_TRIG        LL_DMAMUX_REQ_TIM3_TRIG      /*!< DMAMUX TIM3 TRIG request   */
+#define DMA_REQUEST_TIM3_UP          LL_DMAMUX_REQ_TIM3_UP        /*!< DMAMUX TIM3 UP request     */
+#if defined(TIM6)
+#define DMA_REQUEST_TIM6_UP          LL_DMAMUX_REQ_TIM6_UP        /*!< DMAMUX TIM6 UP request     */
+#endif
+#if defined(TIM7)
+#define DMA_REQUEST_TIM7_UP          LL_DMAMUX_REQ_TIM7_UP        /*!< DMAMUX TIM7 UP request     */
+#endif
+#if defined(TIM15)
+#define DMA_REQUEST_TIM15_CH1        LL_DMAMUX_REQ_TIM15_CH1      /*!< DMAMUX TIM15 CH1 request   */
+#define DMA_REQUEST_TIM15_CH2        LL_DMAMUX_REQ_TIM15_CH2      /*!< DMAMUX TIM15 CH2 request   */
+#define DMA_REQUEST_TIM15_TRIG_COM   LL_DMAMUX_REQ_TIM15_TRIG_COM /*!< DMAMUX TIM15 TRIG COM request */
+#define DMA_REQUEST_TIM15_UP         LL_DMAMUX_REQ_TIM15_UP       /*!< DMAMUX TIM15 UP request    */
+#endif
+#define DMA_REQUEST_TIM16_CH1        LL_DMAMUX_REQ_TIM16_CH1      /*!< DMAMUX TIM16 CH1 request   */
+#define DMA_REQUEST_TIM16_COM        LL_DMAMUX_REQ_TIM16_COM      /*!< DMAMUX TIM16 COM request   */
+#define DMA_REQUEST_TIM16_UP         LL_DMAMUX_REQ_TIM16_UP       /*!< DMAMUX TIM16 UP request    */
+#define DMA_REQUEST_TIM17_CH1        LL_DMAMUX_REQ_TIM17_CH1      /*!< DMAMUX TIM17 CH1 request   */
+#define DMA_REQUEST_TIM17_COM        LL_DMAMUX_REQ_TIM17_COM      /*!< DMAMUX TIM17 COM request   */
+#define DMA_REQUEST_TIM17_UP         LL_DMAMUX_REQ_TIM17_UP       /*!< DMAMUX TIM17 UP request    */
+#define DMA_REQUEST_USART1_RX        LL_DMAMUX_REQ_USART1_RX      /*!< DMAMUX USART1 RX request  */
+#define DMA_REQUEST_USART1_TX        LL_DMAMUX_REQ_USART1_TX      /*!< DMAMUX USART1 TX request  */
+#define DMA_REQUEST_USART2_RX        LL_DMAMUX_REQ_USART2_RX      /*!< DMAMUX USART2 RX request  */
+#define DMA_REQUEST_USART2_TX        LL_DMAMUX_REQ_USART2_TX      /*!< DMAMUX USART2 TX request  */
+#if defined(USART3)
+#define DMA_REQUEST_USART3_RX        LL_DMAMUX_REQ_USART3_RX      /*!< DMAMUX USART3 RX request  */
+#define DMA_REQUEST_USART3_TX        LL_DMAMUX_REQ_USART3_TX      /*!< DMAMUX USART3 TX request  */
+#endif
+#if defined(USART4)
+#define DMA_REQUEST_USART4_RX        LL_DMAMUX_REQ_USART4_RX      /*!< DMAMUX USART4 RX request  */
+#define DMA_REQUEST_USART4_TX        LL_DMAMUX_REQ_USART4_TX      /*!< DMAMUX USART4 TX request  */
+#endif
+#if defined(UCPD1)
+#define DMA_REQUEST_UCPD1_RX         LL_DMAMUX_REQ_UCPD1_RX       /*!< DMAMUX UCPD1 RX request  */
+#define DMA_REQUEST_UCPD1_TX         LL_DMAMUX_REQ_UCPD1_TX       /*!< DMAMUX UCPD1 TX request  */
+#endif
+#if defined(UCPD2)
+#define DMA_REQUEST_UCPD2_RX         LL_DMAMUX_REQ_UCPD2_RX       /*!< DMAMUX UCPD2 RX request  */
+#define DMA_REQUEST_UCPD2_TX         LL_DMAMUX_REQ_UCPD2_TX       /*!< DMAMUX UCPD2 TX request  */
+#endif
+                                          
+#if defined(I2C3)
+#define DMA_REQUEST_I2C3_RX          LL_DMAMUX_REQ_I2C3_RX        /*!< DMAMUX I2C3 RX request  */
+#define DMA_REQUEST_I2C3_TX          LL_DMAMUX_REQ_I2C3_TX        /*!< DMAMUX I2C3 TX request  */
+#endif
+
+#if defined(LPUART2)
+#define DMA_REQUEST_LPUART2_RX       LL_DMAMUX_REQ_LPUART2_RX     /*!< DMAMUX LPUART2 RX request  */
+#define DMA_REQUEST_LPUART2_TX       LL_DMAMUX_REQ_LPUART2_TX     /*!< DMAMUX LPUART2 TX request  */
+#endif
+
+#if defined(SPI3)
+#define DMA_REQUEST_SPI3_RX          LL_DMAMUX_REQ_SPI3_RX        /*!< DMAMUX SPI3 RX request     */
+#define DMA_REQUEST_SPI3_TX          LL_DMAMUX_REQ_SPI3_TX        /*!< DMAMUX SPI3 TX request     */
+#endif
+
+#if defined(TIM4)
+#define DMA_REQUEST_TIM4_CH1         LL_DMAMUX_REQ_TIM4_CH1       /*!< DMAMUX TIM4 CH1 request    */
+#define DMA_REQUEST_TIM4_CH2         LL_DMAMUX_REQ_TIM4_CH2       /*!< DMAMUX TIM4 CH2 request    */
+#define DMA_REQUEST_TIM4_CH3         LL_DMAMUX_REQ_TIM4_CH3       /*!< DMAMUX TIM4 CH3 request    */
+#define DMA_REQUEST_TIM4_CH4         LL_DMAMUX_REQ_TIM4_CH4       /*!< DMAMUX TIM4 CH4 request    */
+#define DMA_REQUEST_TIM4_TRIG        LL_DMAMUX_REQ_TIM4_TRIG      /*!< DMAMUX TIM4 TRIG request   */
+#define DMA_REQUEST_TIM4_UP          LL_DMAMUX_REQ_TIM4_UP        /*!< DMAMUX TIM4 UP request     */
+#endif
+
+#if defined(USART5)
+#define DMA_REQUEST_USART5_RX        LL_DMAMUX_REQ_USART5_RX      /*!< DMAMUX USART5 RX request  */
+#define DMA_REQUEST_USART5_TX        LL_DMAMUX_REQ_USART5_TX      /*!< DMAMUX USART5 TX request  */
+#endif
+
+#if defined(USART6)
+#define DMA_REQUEST_USART6_RX        LL_DMAMUX_REQ_USART6_RX      /*!< DMAMUX USART6 RX request  */
+#define DMA_REQUEST_USART6_TX        LL_DMAMUX_REQ_USART6_TX      /*!< DMAMUX USART6 TX request  */
+#endif
+
+
+#define DMA_MAX_REQUEST              LL_DMAMUX_MAX_REQ
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+  * @{
+  */
+#define DMA_PERIPH_TO_MEMORY         LL_DMA_DIRECTION_PERIPH_TO_MEMORY  /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH         LL_DMA_DIRECTION_MEMORY_TO_PERIPH  /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY         LL_DMA_DIRECTION_MEMORY_TO_MEMORY  /*!< Memory to memory direction     */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+  * @{
+  */
+#define DMA_PINC_ENABLE              LL_DMA_PERIPH_INCREMENT            /*!< Peripheral increment mode Enable  */
+#define DMA_PINC_DISABLE             LL_DMA_PERIPH_NOINCREMENT          /*!< Peripheral increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+  * @{
+  */
+#define DMA_MINC_ENABLE              LL_DMA_MEMORY_INCREMENT            /*!< Memory increment mode Enable  */
+#define DMA_MINC_DISABLE             LL_DMA_MEMORY_NOINCREMENT          /*!< Memory increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+  * @{
+  */
+#define DMA_PDATAALIGN_BYTE          LL_DMA_PDATAALIGN_BYTE             /*!< Peripheral data alignment : Byte     */
+#define DMA_PDATAALIGN_HALFWORD      LL_DMA_PDATAALIGN_HALFWORD         /*!< Peripheral data alignment : HalfWord */
+#define DMA_PDATAALIGN_WORD          LL_DMA_PDATAALIGN_WORD             /*!< Peripheral data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+  * @{
+  */
+#define DMA_MDATAALIGN_BYTE          LL_DMA_MDATAALIGN_BYTE             /*!< Memory data alignment : Byte     */
+#define DMA_MDATAALIGN_HALFWORD      LL_DMA_MDATAALIGN_HALFWORD         /*!< Memory data alignment : HalfWord */
+#define DMA_MDATAALIGN_WORD          LL_DMA_MDATAALIGN_WORD             /*!< Memory data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_mode DMA mode
+  * @{
+  */
+#define DMA_NORMAL                   LL_DMA_MODE_NORMAL                 /*!< Normal mode    */
+#define DMA_CIRCULAR                 LL_DMA_MODE_CIRCULAR               /*!< Circular mode  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+  * @{
+  */
+#define DMA_PRIORITY_LOW             LL_DMA_PRIORITY_LOW                /*!< Priority level : Low       */
+#define DMA_PRIORITY_MEDIUM          LL_DMA_PRIORITY_MEDIUM             /*!< Priority level : Medium    */
+#define DMA_PRIORITY_HIGH            LL_DMA_PRIORITY_HIGH               /*!< Priority level : High      */
+#define DMA_PRIORITY_VERY_HIGH       LL_DMA_PRIORITY_VERYHIGH           /*!< Priority level : Very_High */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+  * @{
+  */
+#define DMA_IT_TC                    DMA_CCR_TCIE                       /*!< Transfer Complete interrupt      */
+#define DMA_IT_HT                    DMA_CCR_HTIE                       /*!< Half Transfer Complete interrupt */
+#define DMA_IT_TE                    DMA_CCR_TEIE                       /*!< Transfer Error interrupt         */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+  * @{
+  */
+
+#define DMA_FLAG_GI1                 DMA_ISR_GIF1                       /*!< Global Interrupt flag for Channel 1  */
+#define DMA_FLAG_TC1                 DMA_ISR_TCIF1                      /*!< Transfer Complete flag for Channel 1 */
+#define DMA_FLAG_HT1                 DMA_ISR_HTIF1                      /*!< Half Transfer flag for Channel 1      */
+#define DMA_FLAG_TE1                 DMA_ISR_TEIF1                      /*!< Transfer Error flag for Channel 1     */
+#define DMA_FLAG_GI2                 DMA_ISR_GIF2                       /*!< Global Interrupt flag for Channel 2  */
+#define DMA_FLAG_TC2                 DMA_ISR_TCIF2                      /*!< Transfer Complete flag for Channel 2 */
+#define DMA_FLAG_HT2                 DMA_ISR_HTIF2                      /*!< Half Transfer flag for Channel 2      */
+#define DMA_FLAG_TE2                 DMA_ISR_TEIF2                      /*!< Transfer Error flag for Channel 2     */
+#define DMA_FLAG_GI3                 DMA_ISR_GIF3                       /*!< Global Interrupt flag for Channel 3  */
+#define DMA_FLAG_TC3                 DMA_ISR_TCIF3                      /*!< Transfer Complete flag for Channel 3 */
+#define DMA_FLAG_HT3                 DMA_ISR_HTIF3                      /*!< Half Transfer flag for Channel 3      */
+#define DMA_FLAG_TE3                 DMA_ISR_TEIF3                      /*!< Transfer Error flag for Channel 3     */
+#define DMA_FLAG_GI4                 DMA_ISR_GIF4                       /*!< Global Interrupt flag for Channel 4  */
+#define DMA_FLAG_TC4                 DMA_ISR_TCIF4                      /*!< Transfer Complete flag for Channel 4 */
+#define DMA_FLAG_HT4                 DMA_ISR_HTIF4                      /*!< Half Transfer flag for Channel 4      */
+#define DMA_FLAG_TE4                 DMA_ISR_TEIF4                      /*!< Transfer Error flag for Channel 4     */
+#define DMA_FLAG_GI5                 DMA_ISR_GIF5                       /*!< Global Interrupt flag for Channel 5  */
+#define DMA_FLAG_TC5                 DMA_ISR_TCIF5                      /*!< Transfer Complete flag for Channel 5 */
+#define DMA_FLAG_HT5                 DMA_ISR_HTIF5                      /*!< Half Transfer flag for Channel 5      */
+#define DMA_FLAG_TE5                 DMA_ISR_TEIF5                      /*!< Transfer Error for Channel 5          */
+#if defined(DMA1_Channel6)
+#define DMA_FLAG_GI6                 DMA_ISR_GIF6                       /*!< Global Interrupt flag for Channel 6  */
+#define DMA_FLAG_TC6                 DMA_ISR_TCIF6                      /*!< Transfer Complete flag for Channel 6 */
+#define DMA_FLAG_HT6                 DMA_ISR_HTIF6                      /*!< Half Transfer flag for Channel 6      */
+#define DMA_FLAG_TE6                 DMA_ISR_TEIF6                      /*!< Transfer Error flag for Channel 6     */
+#endif
+#if defined(DMA1_Channel7)
+#define DMA_FLAG_GI7                 DMA_ISR_GIF7                       /*!< Global Interrupt flag for Channel 7  */
+#define DMA_FLAG_TC7                 DMA_ISR_TCIF7                      /*!< Transfer Complete flag for Channel 7 */
+#define DMA_FLAG_HT7                 DMA_ISR_HTIF7                      /*!< Half Transfer flag for Channel 7      */
+#define DMA_FLAG_TE7                 DMA_ISR_TEIF7                      /*!< Transfer Error flag for Channel 7     */
+#endif
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @brief  Reset DMA handle state
+  * @param __HANDLE__ DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+  * @brief  Enable the specified DMA Channel.
+  * @param __HANDLE__ DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
+
+/**
+  * @brief  Disable the specified DMA Channel.
+  * @param __HANDLE__ DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
+
+/**
+  * @brief  Return the current DMA Channel transfer complete flag.
+  * @param __HANDLE__ DMA handle
+  * @retval The specified transfer complete flag index.
+  */
+#if defined(DMA2)
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+   DMA_FLAG_TC7)
+#else /* DMA1 */
+#if   defined(DMA1_Channel7)
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+   DMA_FLAG_TC7)
+#else
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+   DMA_FLAG_TC5)
+#endif
+#endif /* DMA2 */
+
+/**
+  * @brief  Return the current DMA Channel half transfer complete flag.
+  * @param __HANDLE__ DMA handle
+  * @retval The specified half transfer complete flag index.
+  */
+#if defined(DMA2)
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+   DMA_FLAG_HT7)
+#else /* DMA1 */
+#if   defined(DMA1_Channel7)
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+   DMA_FLAG_HT7)
+#else
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+   DMA_FLAG_HT5)
+#endif
+#endif /* DMA2 */
+
+/**
+  * @brief  Return the current DMA Channel transfer error flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#if defined(DMA2)
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+   DMA_FLAG_TE7)
+#else /* DMA1 */
+#if   defined(DMA1_Channel7)
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+   DMA_FLAG_TE7)
+#else
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+   DMA_FLAG_TE5)
+#endif
+#endif /* DMA2 */
+
+/**
+  * @brief  Return the current DMA Channel Global interrupt flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#if defined(DMA2)
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GI1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GI2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GI3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GI4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_GI5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\
+   DMA_FLAG_GI7)
+#else /* DMA1 */
+#if   defined(DMA1_Channel7)
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\
+   DMA_FLAG_GI7)
+#else
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\
+   DMA_FLAG_GI5)
+#endif
+#endif /* DMA2 */
+
+/**
+  * @brief  Get the DMA Channel pending flags.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCx:  Transfer complete flag
+  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+  *            @arg DMA_FLAG_TEx:  Transfer error flag
+  *            @arg DMA_FLAG_GIx:  Global interrupt flag
+  *         Where x can be 1 to max Channel supported by the product to select the DMA Channel flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#if defined(DMA2)
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
+ (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
+#else /* DMA1 */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)  (DMA1->ISR & (__FLAG__))
+#endif /* DMA2 */
+
+/**
+  * @brief  Clear the DMA Channel pending flags.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCx:  Transfer complete flag
+  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+  *            @arg DMA_FLAG_TEx:  Transfer error flag
+  *            @arg DMA_FLAG_GIx:  Global interrupt flag
+  *         Where x can be 1 to max Channel supported by the product to select the DMA Channel flag.
+  * @retval None
+  */
+#if defined(DMA2)
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
+ (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
+#else /* DMA1 */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR |= (__FLAG__))
+#endif /* DMA2 */
+
+/**
+  * @brief  Enable the specified DMA Channel interrupts.
+  * @param  __HANDLE__ DMA handle
+  * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified DMA Channel interrupts.
+  * @param  __HANDLE__ DMA handle
+  * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified DMA Channel interrupt is enabled or disabled.
+  * @param  __HANDLE__ DMA handle
+  * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
+  * @retval The state of DMA_IT (SET or RESET).
+  */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
+
+/**
+  * @brief  Returns the number of remaining data units in the current DMA Channel transfer.
+  * @param  __HANDLE__ DMA handle
+  * @retval The number of remaining data units in the current DMA Channel transfer.
+  */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
+
+/**
+  * @}
+  */
+
+/* Include DMA HAL Extension module */
+#include "stm32g0xx_hal_dma_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DMA_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State and Error functions ***************************************/
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+  * @{
+  */
+
+#define IS_DMA_DIRECTION(DIRECTION)             (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+                                                 ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
+                                                 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_BUFFER_SIZE(SIZE)                (((SIZE) >= 0x1U) && ((SIZE) < DMA_CNDTR_NDT))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE)      (((STATE) == DMA_PINC_ENABLE) || \
+                                                 ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE)          (((STATE) == DMA_MINC_ENABLE)  || \
+                                                 ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_ALL_REQUEST(REQUEST)             ((REQUEST) <= DMA_MAX_REQUEST)
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)       (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
+                                                 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+                                                 ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE)           (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
+                                                 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+                                                 ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE)                       (((MODE) == DMA_NORMAL )  || \
+                                                 ((MODE) == DMA_CIRCULAR))
+
+#define IS_DMA_PRIORITY(PRIORITY)               (((PRIORITY) == DMA_PRIORITY_LOW )   || \
+                                                 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+                                                 ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
+                                                 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G0xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h

@@ -0,0 +1,280 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_dma_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_DMA_EX_H
+#define STM32G0xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal_def.h"
+#include "stm32g0xx_ll_dmamux.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMAEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL DMAMUX Synchronization configuration structure definition
+  */
+typedef struct
+{
+  uint32_t SyncSignalID;        /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
+                                  This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */
+
+  uint32_t SyncPolarity;        /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
+                                  This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
+
+  FunctionalState SyncEnable;   /*!< Specifies if the synchronization shall be enabled or disabled
+                                  This parameter can take the value ENABLE or DISABLE */
+
+  FunctionalState EventEnable;  /*!< Specifies if an event shall be generated once the RequestNumber is reached.
+                                  This parameter can take the value ENABLE or DISABLE */
+
+  uint32_t RequestNumber;       /*!< Specifies the number of DMA request that will be authorized after a sync event
+                                  This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
+
+
+} HAL_DMA_MuxSyncConfigTypeDef;
+
+
+/**
+  * @brief  HAL DMAMUX request generator parameters structure definition
+  */
+typedef struct
+{
+  uint32_t SignalID;            /*!< Specifies the ID of the signal used for DMAMUX request generator
+                                  This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
+
+  uint32_t Polarity;            /*!< Specifies the polarity of the signal on which the request is generated.
+                                  This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
+
+  uint32_t RequestNumber;       /*!< Specifies the number of DMA request that will be generated after a signal event
+                                  This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
+
+} HAL_DMA_MuxRequestGeneratorConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
+  * @{
+  */
+
+/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
+  * @{
+  */
+#define HAL_DMAMUX1_SYNC_EXTI0            LL_DMAMUX_SYNC_EXTI_LINE0      /*!< Synchronization signal from EXTI Line0  */
+#define HAL_DMAMUX1_SYNC_EXTI1            LL_DMAMUX_SYNC_EXTI_LINE1      /*!< Synchronization signal from EXTI Line1  */
+#define HAL_DMAMUX1_SYNC_EXTI2            LL_DMAMUX_SYNC_EXTI_LINE2      /*!< Synchronization signal from EXTI Line2  */
+#define HAL_DMAMUX1_SYNC_EXTI3            LL_DMAMUX_SYNC_EXTI_LINE3      /*!< Synchronization signal from EXTI Line3  */
+#define HAL_DMAMUX1_SYNC_EXTI4            LL_DMAMUX_SYNC_EXTI_LINE4      /*!< Synchronization signal from EXTI Line4  */
+#define HAL_DMAMUX1_SYNC_EXTI5            LL_DMAMUX_SYNC_EXTI_LINE5      /*!< Synchronization signal from EXTI Line5  */
+#define HAL_DMAMUX1_SYNC_EXTI6            LL_DMAMUX_SYNC_EXTI_LINE6      /*!< Synchronization signal from EXTI Line6  */
+#define HAL_DMAMUX1_SYNC_EXTI7            LL_DMAMUX_SYNC_EXTI_LINE7      /*!< Synchronization signal from EXTI Line7  */
+#define HAL_DMAMUX1_SYNC_EXTI8            LL_DMAMUX_SYNC_EXTI_LINE8      /*!< Synchronization signal from EXTI Line8  */
+#define HAL_DMAMUX1_SYNC_EXTI9            LL_DMAMUX_SYNC_EXTI_LINE9      /*!< Synchronization signal from EXTI Line9  */
+#define HAL_DMAMUX1_SYNC_EXTI10           LL_DMAMUX_SYNC_EXTI_LINE10     /*!< Synchronization signal from EXTI Line10  */
+#define HAL_DMAMUX1_SYNC_EXTI11           LL_DMAMUX_SYNC_EXTI_LINE11     /*!< Synchronization signal from EXTI Line11  */
+#define HAL_DMAMUX1_SYNC_EXTI12           LL_DMAMUX_SYNC_EXTI_LINE12     /*!< Synchronization signal from EXTI Line12  */
+#define HAL_DMAMUX1_SYNC_EXTI13           LL_DMAMUX_SYNC_EXTI_LINE13     /*!< Synchronization signal from EXTI Line1 3 */
+#define HAL_DMAMUX1_SYNC_EXTI14           LL_DMAMUX_SYNC_EXTI_LINE14     /*!< Synchronization signal from EXTI Line1 4 */
+#define HAL_DMAMUX1_SYNC_EXTI15           LL_DMAMUX_SYNC_EXTI_LINE15     /*!< Synchronization signal from EXTI Line1 5 */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT  LL_DMAMUX_SYNC_DMAMUX_CH0      /*!< Synchronization signal from DMAMUX channel0 Event */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT  LL_DMAMUX_SYNC_DMAMUX_CH1      /*!< Synchronization signal from DMAMUX channel1 Event */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT  LL_DMAMUX_SYNC_DMAMUX_CH2      /*!< Synchronization signal from DMAMUX channel2 Event */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT  LL_DMAMUX_SYNC_DMAMUX_CH3      /*!< Synchronization signal from DMAMUX channel3 Event */
+#if defined(LPTIM1)
+#define HAL_DMAMUX1_SYNC_LPTIM1_OUT       LL_DMAMUX_SYNC_LPTIM1_OUT      /*!< Synchronization signal from LPTIM1 Output */
+#endif
+#if defined(LPTIM2)
+#define HAL_DMAMUX1_SYNC_LPTIM2_OUT       LL_DMAMUX_SYNC_LPTIM2_OUT      /*!< Synchronization signal from LPTIM2 Output */
+#endif
+#define HAL_DMAMUX1_SYNC_TIM14_OC         LL_DMAMUX_SYNC_TIM14_OC        /*!< Synchronization signal from TIM14 OC */
+
+#define HAL_DMAMUX1_MAX_SYNC              HAL_DMAMUX1_SYNC_TIM14_OC
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
+  * @{
+  */
+#define HAL_DMAMUX_SYNC_NO_EVENT          LL_DMAMUX_SYNC_NO_EVENT               /*!< block synchronization events                       */
+#define HAL_DMAMUX_SYNC_RISING            LL_DMAMUX_SYNC_POL_RISING             /*!< synchronize with rising edge events                */
+#define HAL_DMAMUX_SYNC_FALLING           LL_DMAMUX_SYNC_POL_FALLING            /*!< synchronize with falling edge events               */
+#define HAL_DMAMUX_SYNC_RISING_FALLING    LL_DMAMUX_SYNC_POL_RISING_FALLING     /*!< synchronize with rising and falling edge events    */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection
+  * @{
+  */
+#define HAL_DMAMUX1_REQ_GEN_EXTI0            LL_DMAMUX_REQ_GEN_EXTI_LINE0    /*!< Request signal generation from EXTI Line0  */
+#define HAL_DMAMUX1_REQ_GEN_EXTI1            LL_DMAMUX_REQ_GEN_EXTI_LINE1    /*!< Request signal generation from EXTI Line1  */
+#define HAL_DMAMUX1_REQ_GEN_EXTI2            LL_DMAMUX_REQ_GEN_EXTI_LINE2    /*!< Request signal generation from EXTI Line2  */
+#define HAL_DMAMUX1_REQ_GEN_EXTI3            LL_DMAMUX_REQ_GEN_EXTI_LINE3    /*!< Request signal generation from EXTI Line3  */
+#define HAL_DMAMUX1_REQ_GEN_EXTI4            LL_DMAMUX_REQ_GEN_EXTI_LINE4    /*!< Request signal generation from EXTI Line4  */
+#define HAL_DMAMUX1_REQ_GEN_EXTI5            LL_DMAMUX_REQ_GEN_EXTI_LINE5    /*!< Request signal generation from EXTI Line5  */
+#define HAL_DMAMUX1_REQ_GEN_EXTI6            LL_DMAMUX_REQ_GEN_EXTI_LINE6    /*!< Request signal generation from EXTI Line6  */
+#define HAL_DMAMUX1_REQ_GEN_EXTI7            LL_DMAMUX_REQ_GEN_EXTI_LINE7    /*!< Request signal generation from EXTI Line7  */
+#define HAL_DMAMUX1_REQ_GEN_EXTI8            LL_DMAMUX_REQ_GEN_EXTI_LINE8    /*!< Request signal generation from EXTI Line8  */
+#define HAL_DMAMUX1_REQ_GEN_EXTI9            LL_DMAMUX_REQ_GEN_EXTI_LINE9    /*!< Request signal generation from EXTI Line9  */
+#define HAL_DMAMUX1_REQ_GEN_EXTI10           LL_DMAMUX_REQ_GEN_EXTI_LINE10   /*!< Request signal generation from EXTI Line10 */
+#define HAL_DMAMUX1_REQ_GEN_EXTI11           LL_DMAMUX_REQ_GEN_EXTI_LINE11   /*!< Request signal generation from EXTI Line11 */
+#define HAL_DMAMUX1_REQ_GEN_EXTI12           LL_DMAMUX_REQ_GEN_EXTI_LINE12   /*!< Request signal generation from EXTI Line12 */
+#define HAL_DMAMUX1_REQ_GEN_EXTI13           LL_DMAMUX_REQ_GEN_EXTI_LINE13   /*!< Request signal generation from EXTI Line13 */
+#define HAL_DMAMUX1_REQ_GEN_EXTI14           LL_DMAMUX_REQ_GEN_EXTI_LINE14   /*!< Request signal generation from EXTI Line14 */
+#define HAL_DMAMUX1_REQ_GEN_EXTI15           LL_DMAMUX_REQ_GEN_EXTI_LINE15   /*!< Request signal generation from EXTI Line15 */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT  LL_DMAMUX_REQ_GEN_DMAMUX_CH0    /*!< Request signal generation from DMAMUX channel0 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT  LL_DMAMUX_REQ_GEN_DMAMUX_CH1    /*!< Request signal generation from DMAMUX channel1 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT  LL_DMAMUX_REQ_GEN_DMAMUX_CH2    /*!< Request signal generation from DMAMUX channel2 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT  LL_DMAMUX_REQ_GEN_DMAMUX_CH3    /*!< Request signal generation from DMAMUX channel3 Event */
+#if defined(LPTIM1)
+#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT       LL_DMAMUX_REQ_GEN_LPTIM1_OUT    /*!< Request signal generation from LPTIM1 Output */
+#endif
+#if defined(LPTIM2)
+#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT       LL_DMAMUX_REQ_GEN_LPTIM2_OUT    /*!< Request signal generation from LPTIM2 Output */
+#endif
+#define HAL_DMAMUX1_REQ_GEN_TIM14_OC         LL_DMAMUX_REQ_GEN_TIM14_OC      /*!< Request signal generation from TIM14 OC */
+
+#define HAL_DMAMUX1_MAX_REQ_GEN              HAL_DMAMUX1_REQ_GEN_TIM14_OC
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection
+  * @{
+  */
+#define HAL_DMAMUX_REQ_GEN_NO_EVENT       LL_DMAMUX_REQ_GEN_NO_EVENT            /*!< block request generator events                     */
+#define HAL_DMAMUX_REQ_GEN_RISING         LL_DMAMUX_REQ_GEN_POL_RISING          /*!< generate request on rising edge events             */
+#define HAL_DMAMUX_REQ_GEN_FALLING        LL_DMAMUX_REQ_GEN_POL_FALLING         /*!< generate request on falling edge events            */
+#define HAL_DMAMUX_REQ_GEN_RISING_FALLING LL_DMAMUX_REQ_GEN_POL_RISING_FALLING  /*!< generate request on rising and falling edge events */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMAEx_Exported_Functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup DMAEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* ------------------------- REQUEST -----------------------------------------*/
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
+                                                      HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
+/* -------------------------------------------------------------------------- */
+
+/* ------------------------- SYNCHRO -----------------------------------------*/
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
+/* -------------------------------------------------------------------------- */
+
+void              HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
+  * @brief    DMAEx private macros
+ * @{
+ */
+
+#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID)             (((SIGNAL_ID) == HAL_DMAMUX1_SYNC_EXTI0) || \
+                                                         (((SIGNAL_ID) >= HAL_DMAMUX1_SYNC_EXTI1) && \
+                                                          ((SIGNAL_ID) <= HAL_DMAMUX1_MAX_SYNC)))
+
+#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER)   (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
+
+#define IS_DMAMUX_SYNC_POLARITY(POLARITY)               (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
+                                                         ((POLARITY) == HAL_DMAMUX_SYNC_RISING)   || \
+                                                         ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)  || \
+                                                         ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
+
+#define IS_DMAMUX_SYNC_STATE(SYNC)                      (((SYNC) == DISABLE)   || ((SYNC) == ENABLE))
+
+#define IS_DMAMUX_SYNC_EVENT(EVENT)                     (((EVENT) == DISABLE)   || \
+                                                         ((EVENT) == ENABLE))
+
+#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID)      (((SIGNAL_ID) == HAL_DMAMUX1_REQ_GEN_EXTI0) || \
+                                                         (((SIGNAL_ID) >= HAL_DMAMUX1_REQ_GEN_EXTI1) && \
+                                                          ((SIGNAL_ID) <= HAL_DMAMUX1_MAX_REQ_GEN)))
+
+#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
+
+#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY)        (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT)|| \
+                                                         ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING)  || \
+                                                         ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
+                                                         ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G0xx_HAL_DMA_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h

@@ -0,0 +1,389 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_exti.h
+  * @author  MCD Application Team
+  * @brief   Header file of EXTI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_EXTI_H
+#define STM32G0xx_HAL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal_def.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup EXTI EXTI
+  * @brief EXTI HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Types EXTI Exported Types
+  * @{
+  */
+typedef enum
+{
+  HAL_EXTI_COMMON_CB_ID          = 0x00U,
+  HAL_EXTI_RISING_CB_ID          = 0x01U,
+  HAL_EXTI_FALLING_CB_ID         = 0x02U,
+} EXTI_CallbackIDTypeDef;
+
+
+/**
+  * @brief  EXTI Handle structure definition
+  */
+typedef struct
+{
+  uint32_t Line;                    /*!<  Exti line number */
+  void (* RisingCallback)(void);    /*!<  Exti rising callback */
+  void (* FallingCallback)(void);   /*!<  Exti falling callback */
+} EXTI_HandleTypeDef;
+
+/**
+  * @brief  EXTI Configuration structure definition
+  */
+typedef struct
+{
+  uint32_t Line;      /*!< The Exti line to be configured. This parameter
+                           can be a value of @ref EXTI_Line */
+  uint32_t Mode;      /*!< The Exit Mode to be configured for a core.
+                           This parameter can be a combination of @ref EXTI_Mode */
+  uint32_t Trigger;   /*!< The Exti Trigger to be configured. This parameter
+                           can be a value of @ref EXTI_Trigger */
+  uint32_t GPIOSel;   /*!< The Exti GPIO multiplexer selection to be configured.
+                           This parameter is only possible for line 0 to 15. It
+                           can be a value of @ref EXTI_GPIOSel */
+} EXTI_ConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Line  EXTI Line
+  * @{
+  */
+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | 0x00u)
+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | 0x01u)
+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | 0x02u)
+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | 0x03u)
+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | 0x04u)
+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | 0x05u)
+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | 0x06u)
+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | 0x07u)
+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | 0x08u)
+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | 0x09u)
+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | 0x0Au)
+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | 0x0Bu)
+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | 0x0Cu)
+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | 0x0Du)
+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | 0x0Eu)
+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | 0x0Fu)
+#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | 0x10u)
+#if defined(COMP1)
+#define EXTI_LINE_17                        (EXTI_CONFIG   | EXTI_REG1 | 0x11u)
+#else
+#define EXTI_LINE_17                        (EXTI_RESERVED | EXTI_REG1 | 0x11u)
+#endif
+#if defined(COMP2)
+#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_REG1 | 0x12u)
+#else
+#define EXTI_LINE_18                        (EXTI_RESERVED | EXTI_REG1 | 0x12u)
+#endif
+#define EXTI_LINE_19                        (EXTI_DIRECT   | EXTI_REG1 | 0x13u)
+#if defined(COMP3)
+#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_REG1 | 0x14u)
+#else
+#define EXTI_LINE_20                        (EXTI_RESERVED | EXTI_REG1 | 0x14u)
+#endif
+#define EXTI_LINE_21                        (EXTI_DIRECT   | EXTI_REG1 | 0x15u)
+#if defined(RCC_CCIPR_I2C2SEL)
+#define EXTI_LINE_22                        (EXTI_DIRECT   | EXTI_REG1 | 0x16u)
+#else
+#define EXTI_LINE_22                        (EXTI_RESERVED | EXTI_REG1 | 0x16u)
+#endif
+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | 0x17u)
+#if defined(RCC_CCIPR_USART3SEL)
+#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | 0x18u)
+#else
+#define EXTI_LINE_24                        (EXTI_RESERVED | EXTI_REG1 | 0x18u)
+#endif
+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | 0x19u)
+#if defined(RCC_CCIPR_USART2SEL)
+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | 0x1Au)
+#else
+#define EXTI_LINE_26                        (EXTI_RESERVED | EXTI_REG1 | 0x1Au)
+#endif
+#if defined(CEC)
+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | 0x1Bu)
+#else
+#define EXTI_LINE_27                        (EXTI_RESERVED | EXTI_REG1 | 0x1Bu)
+#endif
+#if defined(LPUART1)
+#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | 0x1Cu)
+#else
+#define EXTI_LINE_28                        (EXTI_RESERVED | EXTI_REG1 | 0x1Cu)
+#endif
+#if defined(LPTIM1)
+#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_REG1 | 0x1Du)
+#else
+#define EXTI_LINE_29                        (EXTI_RESERVED | EXTI_REG1 | 0x1Du)
+#endif
+#if defined(LPTIM2)
+#define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_REG1 | 0x1Eu)
+#else
+#define EXTI_LINE_30                        (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
+#endif
+#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | 0x1Fu)
+#if defined(UCPD1)
+#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | 0x00u)
+#else
+#define EXTI_LINE_32                        (EXTI_RESERVED | EXTI_REG2 | 0x00u)
+#endif
+#if defined(UCPD2)
+#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | 0x01u)
+#else
+#define EXTI_LINE_33                        (EXTI_RESERVED | EXTI_REG2 | 0x01u)
+#endif
+#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
+#define EXTI_LINE_34                        (EXTI_CONFIG   | EXTI_REG2 | 0x02u)
+#else
+#define EXTI_LINE_34                        (EXTI_RESERVED | EXTI_REG2 | 0x02u)
+#endif
+#if defined(LPUART2)
+#define EXTI_LINE_35                        (EXTI_DIRECT   | EXTI_REG2 | 0x03u)
+#else
+#define EXTI_LINE_35                        (EXTI_RESERVED | EXTI_REG2 | 0x03u)
+#endif
+#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
+#define EXTI_LINE_36                        (EXTI_DIRECT | EXTI_REG2 | 0x04u)
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Mode  EXTI Mode
+  * @{
+  */
+#define EXTI_MODE_NONE                      0x00000000u
+#define EXTI_MODE_INTERRUPT                 0x00000001u
+#define EXTI_MODE_EVENT                     0x00000002u
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Trigger  EXTI Trigger
+  * @{
+  */
+#define EXTI_TRIGGER_NONE                   0x00000000u
+#define EXTI_TRIGGER_RISING                 0x00000001u
+#define EXTI_TRIGGER_FALLING                0x00000002u
+#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
+  * @brief
+  * @{
+  */
+#define EXTI_GPIOA                          0x00000000u
+#define EXTI_GPIOB                          0x00000001u
+#define EXTI_GPIOC                          0x00000002u
+#define EXTI_GPIOD                          0x00000003u
+#if defined(GPIOE)
+#define EXTI_GPIOE                          0x00000004u
+#endif
+#define EXTI_GPIOF                          0x00000005u
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+/**
+  * @brief  EXTI Line property definition
+  */
+#define EXTI_PROPERTY_SHIFT                  24u
+#define EXTI_DIRECT                         (0x01uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_CONFIG                         (0x02uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO                           ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_RESERVED                       (0x08uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_PROPERTY_MASK                  (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
+
+/**
+  * @brief  EXTI Register and bit usage
+  */
+#define EXTI_REG_SHIFT                      16u
+#define EXTI_REG1                           (0x00uL << EXTI_REG_SHIFT)
+#define EXTI_REG2                           (0x01uL << EXTI_REG_SHIFT)
+#define EXTI_REG_MASK                       (EXTI_REG1 | EXTI_REG2)
+#define EXTI_PIN_MASK                       0x0000001Fu
+
+/**
+  * @brief  EXTI Mask for interrupt & event mode
+  */
+#define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
+
+/**
+  * @brief  EXTI Mask for trigger possibilities
+  */
+#define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+
+/**
+  * @brief  EXTI Line number
+  */
+#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
+#define EXTI_LINE_NB                        37uL
+#elif defined(STM32G0B0xx)
+#define EXTI_LINE_NB                        37uL
+#elif defined(STM32G081xx) || defined(STM32G071xx)
+#define EXTI_LINE_NB                        34uL
+#elif defined(STM32G070xx)
+#define EXTI_LINE_NB                        34uL
+#elif defined(STM32G041xx) || defined(STM32G031xx)
+#define EXTI_LINE_NB                        32uL
+#else
+#define EXTI_LINE_NB                        32uL
+#endif
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+  * @{
+  */
+#define IS_EXTI_LINE(__EXTI_LINE__)     ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
+                                        ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT)   || \
+                                         (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)   || \
+                                         (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))    && \
+                                         (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \
+                                         (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
+
+#define IS_EXTI_MODE(__MODE__)          ((((__MODE__) & EXTI_MODE_MASK) != 0x00u) && \
+                                         (((__MODE__) & ~EXTI_MODE_MASK) == 0x00u))
+
+#define IS_EXTI_TRIGGER(__EXTI_LINE__)  (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
+
+#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__)  (((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \
+                                              ((__EXTI_LINE__) == EXTI_TRIGGER_FALLING))
+
+#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__)   (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
+
+#if defined(GPIOE)
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOE) || \
+                                         ((__PORT__) == EXTI_GPIOF))
+#else
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOF))
+#endif
+
+#define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16u)
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
+  * @brief    EXTI Exported Functions
+  * @{
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
+  * @brief    Configuration functions
+  * @{
+  */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
+  * @brief    IO operation functions
+  * @{
+  */
+/* IO operation functions *****************************************************/
+void              HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
+uint32_t          HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void              HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G0xx_HAL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h

@@ -0,0 +1,119 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_flash_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_FLASH_EX_H
+#define STM32G0xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal_def.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASHEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
+  * @{
+  */
+/** @defgroup FLASHEx_Empty_Check FLASHEx Empty Check
+  * @{
+  */
+#define FLASH_PROG_NOT_EMPTY                0x00000000u          /*!< 1st location in Flash is programmed */
+#define FLASH_PROG_EMPTY                    FLASH_ACR_PROGEMPTY  /*!< 1st location in Flash is empty */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+  * @{
+  */
+
+/* Extended Program operation functions  *************************************/
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+void              HAL_FLASHEx_EnableDebugger(void);
+void              HAL_FLASHEx_DisableDebugger(void);
+uint32_t          HAL_FLASHEx_FlashEmptyCheck(void);
+void              HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty);
+#if defined(FLASH_SECURABLE_MEMORY_SUPPORT)
+void              HAL_FLASHEx_EnableSecMemProtection(uint32_t Banks);
+#endif
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
+  * @{
+  */
+#define FLASH_PCROP_GRANULARITY_OFFSET             9u                                        /*!< FLASH Code Readout Protection granularity offset */
+#define FLASH_PCROP_GRANULARITY                    (1UL << FLASH_PCROP_GRANULARITY_OFFSET)   /*!< FLASH Code Readout Protection granularity, 512 Bytes */
+/**
+  * @}
+  */
+
+
+/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
+  *  @{
+  */
+#define IS_FLASH_EMPTY_CHECK(__VALUE__)     (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY))
+void              FLASH_PageErase(uint32_t Banks, uint32_t Page);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G0xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h

@@ -0,0 +1,340 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_gpio.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_GPIO_H
+#define STM32G0xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal_def.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIO GPIO
+  * @brief GPIO HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+  * @{
+  */
+/**
+  * @brief   GPIO Init structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;        /*!< Specifies the GPIO pins to be configured.
+                           This parameter can be any value of @ref GPIO_pins */
+
+  uint32_t Mode;       /*!< Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref GPIO_mode */
+
+  uint32_t Pull;       /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                           This parameter can be a value of @ref GPIO_pull */
+
+  uint32_t Speed;      /*!< Specifies the speed for the selected pins.
+                           This parameter can be a value of @ref GPIO_speed */
+
+  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins
+                            This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
+} GPIO_InitTypeDef;
+
+/**
+  * @brief  GPIO Bit SET and Bit RESET enumeration
+  */
+typedef enum
+{
+  GPIO_PIN_RESET = 0U,
+  GPIO_PIN_SET
+} GPIO_PinState;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+/** @defgroup GPIO_pins GPIO pins
+  * @{
+  */
+#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
+#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
+#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
+#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
+#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
+#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
+#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
+#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
+#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
+#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
+#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
+#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
+#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
+#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
+#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
+#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
+#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
+
+#define GPIO_PIN_MASK              (0x0000FFFFu) /* PIN mask for assert test */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_mode GPIO mode
+  * @brief GPIO Configuration Mode
+  *        Elements values convention: 0xX0yz00YZ
+  *           - X  : GPIO mode or EXTI Mode
+  *           - y  : External IT or Event trigger detection
+  *           - z  : IO configuration on External IT or Event
+  *           - Y  : Output type (Push Pull or Open Drain)
+  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
+  * @{
+  */
+#define  GPIO_MODE_INPUT                        (0x00000000u)   /*!< Input Floating Mode                   */
+#define  GPIO_MODE_OUTPUT_PP                    (0x00000001u)   /*!< Output Push Pull Mode                 */
+#define  GPIO_MODE_OUTPUT_OD                    (0x00000011u)   /*!< Output Open Drain Mode                */
+#define  GPIO_MODE_AF_PP                        (0x00000002u)   /*!< Alternate Function Push Pull Mode     */
+#define  GPIO_MODE_AF_OD                        (0x00000012u)   /*!< Alternate Function Open Drain Mode    */
+#define  GPIO_MODE_ANALOG                       (0x00000003u)   /*!< Analog Mode  */
+#define  GPIO_MODE_IT_RISING                    (0x10110000u)   /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define  GPIO_MODE_IT_FALLING                   (0x10210000u)   /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define  GPIO_MODE_IT_RISING_FALLING            (0x10310000u)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+#define  GPIO_MODE_EVT_RISING                   (0x10120000u)   /*!< External Event Mode with Rising edge trigger detection               */
+#define  GPIO_MODE_EVT_FALLING                  (0x10220000u)   /*!< External Event Mode with Falling edge trigger detection              */
+#define  GPIO_MODE_EVT_RISING_FALLING           (0x10320000u)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_speed GPIO speed
+  * @brief GPIO Output Maximum frequency
+  * @{
+  */
+#define  GPIO_SPEED_FREQ_LOW        (0x00000000u)  /*!< Low speed       */
+#define  GPIO_SPEED_FREQ_MEDIUM     (0x00000001u)  /*!< Medium speed    */
+#define  GPIO_SPEED_FREQ_HIGH       (0x00000002u)  /*!< High speed      */
+#define  GPIO_SPEED_FREQ_VERY_HIGH  (0x00000003u)  /*!< Very high speed */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_pull GPIO pull
+  * @brief GPIO Pull-Up or Pull-Down Activation
+  * @{
+  */
+#define  GPIO_NOPULL        (0x00000000u)   /*!< No Pull-up or Pull-down activation  */
+#define  GPIO_PULLUP        (0x00000001u)   /*!< Pull-up activation                  */
+#define  GPIO_PULLDOWN      (0x00000002u)   /*!< Pull-down activation                */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Check whether the specified EXTI line is rising edge asserted or not.
+  * @param  __EXTI_LINE__ specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__)         (EXTI->RPR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clear the EXTI line rising pending bits.
+  * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__)       (EXTI->RPR1 = (__EXTI_LINE__))
+
+/**
+  * @brief  Check whether the specified EXTI line is falling edge asserted or not.
+  * @param  __EXTI_LINE__ specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__)        (EXTI->FPR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clear the EXTI line falling pending bits.
+  * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__)      (EXTI->FPR1 = (__EXTI_LINE__))
+
+/**
+  * @brief  Check whether the specified EXTI line is asserted or not.
+  * @param __EXTI_LINE__ specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)         (__HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) || \
+                                                       __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__))
+
+/**
+  * @brief  Clear the EXTI's line pending bits.
+  * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)         \
+  do {                                                  \
+    __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__);     \
+    __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__);    \
+  } while(0)
+
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @param __EXTI_LINE__ specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__)  (EXTI->SWIER1 |= (__EXTI_LINE__))
+
+/**
+  * @brief  Check whether the specified EXTI line flag is set or not.
+  * @param  __EXTI_LINE__ specifies the EXTI line flag to check.
+  *         This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__)       __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)
+
+/**
+  * @brief  Clear the EXTI line pending flags.
+  * @param  __EXTI_LINE__ specifies the EXTI lines flags to clear.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__)     __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+  * @{
+  */
+#define IS_GPIO_PIN_ACTION(ACTION)  (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+
+#define IS_GPIO_PIN(__PIN__)        ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\
+                                     (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u))
+
+#define IS_GPIO_MODE(__MODE__)      (((__MODE__) == GPIO_MODE_INPUT)              ||\
+                                     ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
+                                     ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
+                                     ((__MODE__) == GPIO_MODE_AF_PP)              ||\
+                                     ((__MODE__) == GPIO_MODE_AF_OD)              ||\
+                                     ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
+                                     ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
+                                     ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
+                                     ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\
+                                     ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\
+                                     ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
+                                     ((__MODE__) == GPIO_MODE_ANALOG))
+
+#define IS_GPIO_SPEED(__SPEED__)    (((__SPEED__) == GPIO_SPEED_FREQ_LOW)    ||\
+                                     ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
+                                     ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)   ||\
+                                     ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_GPIO_PULL(__PULL__)      (((__PULL__) == GPIO_NOPULL)   ||\
+                                     ((__PULL__) == GPIO_PULLUP)   || \
+                                     ((__PULL__) == GPIO_PULLDOWN))
+/**
+  * @}
+  */
+
+/* Include GPIO HAL Extended module */
+#include "stm32g0xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+ *  @brief    GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+void              HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
+ *  @brief    IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void              HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void              HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void              HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void              HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin);
+void              HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G0xx_HAL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h

@@ -0,0 +1,838 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_gpio_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_GPIO_EX_H
+#define STM32G0xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal_def.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIOEx GPIOEx
+  * @brief GPIO Extended HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
+  * @{
+  */
+#if defined (STM32G0C1xx) || defined (STM32G0B1xx)
+/*------------------------- STM32G0C1xx / STM32G0B1xx ------------------------*/
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_CEC           ((uint8_t)0x00)  /*!< CEC Alternate Function mapping */
+#define GPIO_AF0_CRS           ((uint8_t)0x00)  /*!< CRS Alternate Function mapping */
+#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00)  /*!< EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_IR            ((uint8_t)0x00)  /*!< IR Alternate Function mapping */
+#define GPIO_AF0_LPTIM1        ((uint8_t)0x00)  /*!< LPTIM1 Alternate Function mapping */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /*!< MCO (MCO1) Alternate Function mapping */
+#define GPIO_AF0_OSC           ((uint8_t)0x00)  /*!< OSC (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF0_OSC32         ((uint8_t)0x00)  /*!< OSC32 (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /*!< SWJ (SWD) Alternate Function mapping */
+#define GPIO_AF0_SPI1          ((uint8_t)0x00)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF0_SPI2          ((uint8_t)0x00)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF0_TIM14         ((uint8_t)0x00)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF0_TIM15         ((uint8_t)0x00)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF0_TIM16         ((uint8_t)0x00)  /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF0_TIM17         ((uint8_t)0x00)  /*!< TIM17 Alternate Function mapping */
+#define GPIO_AF0_USART1        ((uint8_t)0x00)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF0_USART2        ((uint8_t)0x00)  /*!< USART2 Alternate Function mapping */
+#define GPIO_AF0_USART3        ((uint8_t)0x00)  /*!< USART3 Alternate Function mapping */
+#define GPIO_AF0_USART4        ((uint8_t)0x00)  /*!< USART4 Alternate Function mapping */
+#define GPIO_AF0_UCPD1         ((uint8_t)0x00)  /*!< UCPD1 Alternate Function mapping */
+#define GPIO_AF0_UCPD2         ((uint8_t)0x00)  /*!< UCPD2 Alternate Function mapping */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_CEC           ((uint8_t)0x01)  /*!< CEC Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT      ((uint8_t)0x01)  /*!< EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /*!< IR Alternate Function mapping */
+#define GPIO_AF1_LPTIM2        ((uint8_t)0x01)  /*!< LPTIM2 Alternate Function mapping */
+#define GPIO_AF1_LPUART1       ((uint8_t)0x01)  /*!< LPUART1 Alternate Function mapping */
+#define GPIO_AF1_LPUART2       ((uint8_t)0x01)  /*!< LPUART2 Alternate Function mapping */
+#define GPIO_AF1_OSC           ((uint8_t)0x01)  /*!< OSC (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF1_SPI1          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF1_SPI2          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM3          ((uint8_t)0x01)  /*!< TIM3 Alternate Function mapping */
+#define GPIO_AF1_USART1        ((uint8_t)0x01)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2        ((uint8_t)0x01)  /*!< USART2 Alternate Function mapping */
+#define GPIO_AF1_USART4        ((uint8_t)0x01)  /*!< USART4 Alternate Function mapping */
+#define GPIO_AF1_UCPD1         ((uint8_t)0x01)  /*!< UCPD1 Alternate Function mapping */
+#define GPIO_AF1_UCPD2         ((uint8_t)0x01)  /*!< UCPD2 Alternate Function mapping */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_LPTIM1        ((uint8_t)0x02)  /*!< LPTIM1 Alternate Function mapping */
+#define GPIO_AF2_LPTIM2        ((uint8_t)0x02)  /*!< LPTIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /*!< TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /*!< TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM14         ((uint8_t)0x02)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF2_TIM15         ((uint8_t)0x02)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM16         ((uint8_t)0x02)  /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17         ((uint8_t)0x02)  /*!< TIM17 Alternate Function mapping */
+#define GPIO_AF2_USB           ((uint8_t)0x02)  /*!< USB Alternate Function mapping */
+
+
+/**
+  * @brief   AF 3 selection
+  */
+#define GPIO_AF3_FDCAN1        ((uint8_t)0x03)  /*!< FDCAN1 Alternate Function mapping */
+#define GPIO_AF3_FDCAN2        ((uint8_t)0x03)  /*!< FDCAN2 Alternate Function mapping */
+#define GPIO_AF3_LPUART2       ((uint8_t)0x03)  /*!< LPUART2 Alternate Function mapping */
+#define GPIO_AF3_USART5        ((uint8_t)0x03)  /*!< USART5 Alternate Function mapping */
+#define GPIO_AF3_USART6        ((uint8_t)0x03)  /*!< USART6 Alternate Function mapping */
+#define GPIO_AF3_MCO2          ((uint8_t)0x03)  /*!< MCO2 Alternate Function mapping */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_CRS           ((uint8_t)0x04)  /*!< CRS Alternate Function mapping */
+#define GPIO_AF4_SPI2          ((uint8_t)0x04)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF4_SPI3          ((uint8_t)0x04)  /*!< SPI3 Alternate Function mapping */
+#define GPIO_AF4_TIM14         ((uint8_t)0x04)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF4_TIM15         ((uint8_t)0x04)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF4_USART1        ((uint8_t)0x04)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF4_USART3        ((uint8_t)0x04)  /*!< USART3 Alternate Function mapping */
+#define GPIO_AF4_USART4        ((uint8_t)0x04)  /*!< USART4 Alternate Function mapping */
+#define GPIO_AF4_USART6        ((uint8_t)0x04)  /*!< USART6 Alternate Function mapping */
+#define GPIO_AF4_UCPD1         ((uint8_t)0x04)  /*!< UCPD1 Alternate Function mapping */
+#define GPIO_AF4_UCPD2         ((uint8_t)0x04)  /*!< UCPD2 Alternate Function mapping */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_LPTIM1        ((uint8_t)0x05)  /*!< LPTIM1 Alternate Function mapping */
+#define GPIO_AF5_LPTIM2        ((uint8_t)0x05)  /*!< LPTIM2 Alternate Function mapping */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF5_TIM1          ((uint8_t)0x05)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF5_TIM15         ((uint8_t)0x05)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF5_TIM16         ((uint8_t)0x05)  /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17         ((uint8_t)0x05)  /*!< TIM17 Alternate Function mapping */
+#define GPIO_AF5_USART3        ((uint8_t)0x05)  /*!< USART3 Alternate Function mapping */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_I2C1          ((uint8_t)0x06)  /*!< I2C1 Alternate Function mapping */
+#define GPIO_AF6_I2C2          ((uint8_t)0x06)  /*!< I2C2 Alternate Function mapping */
+#define GPIO_AF6_I2C3          ((uint8_t)0x06)  /*!< I2C3 Alternate Function mapping */
+#define GPIO_AF6_LPUART1       ((uint8_t)0x06)  /*!< LPUART1 Alternate Function mapping */
+#define GPIO_AF6_UCPD1         ((uint8_t)0x06)  /*!< UCPD1 Alternate Function mapping */
+#define GPIO_AF6_UCPD2         ((uint8_t)0x06)  /*!< UCPD2 Alternate Function mapping */
+#define GPIO_AF6_USB           ((uint8_t)0x06)  /*!< USB Alternate Function mapping */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_COMP1         ((uint8_t)0x07)  /*!< COMP1 Alternate Function mapping */
+#define GPIO_AF7_COMP2         ((uint8_t)0x07)  /*!< COMP2 Alternate Function mapping */
+#define GPIO_AF7_COMP3         ((uint8_t)0x07)  /*!< COMP3 Alternate Function mapping */
+#define GPIO_AF7_EVENTOUT      ((uint8_t)0x07)  /*!< EVENTOUT Alternate Function mapping */
+
+/**
+  * @brief   AF 8 selection
+  */
+#define GPIO_AF8_I2C2          ((uint8_t)0x08)  /*!< I2C2 Alternate Function mapping */
+#define GPIO_AF8_USART5        ((uint8_t)0x08)  /*!< USART5 Alternate Function mapping */
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /*!< USART5 Alternate Function mapping */
+
+/**
+  * @brief   AF 9 selection
+  */
+#define GPIO_AF9_I2C3          ((uint8_t)0x09)  /*!< I2C3 Alternate Function mapping */
+#define GPIO_AF9_SPI3          ((uint8_t)0x09)  /*!< SPI3 Alternate Function mapping */
+#define GPIO_AF9_TIM4          ((uint8_t)0x09)  /*!< TIM4 Alternate Function mapping */
+
+/**
+  * @brief   AF 10 selection
+  */
+#define GPIO_AF10_LPUART2      ((uint8_t)0x0A)  /*!< LPUART2 Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x0A)
+
+#endif
+
+#if defined (STM32G0B0xx)
+/*------------------------- STM32G0B0xx ------------------------*/
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_CRS           ((uint8_t)0x00)  /*!< CRS Alternate Function mapping */
+#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00)  /*!< EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_IR            ((uint8_t)0x00)  /*!< IR Alternate Function mapping */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /*!< MCO (MCO1) Alternate Function mapping */
+#define GPIO_AF0_OSC           ((uint8_t)0x00)  /*!< OSC (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF0_OSC32         ((uint8_t)0x00)  /*!< OSC32 (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /*!< SWJ (SWD) Alternate Function mapping */
+#define GPIO_AF0_SPI1          ((uint8_t)0x00)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF0_SPI2          ((uint8_t)0x00)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF0_TIM14         ((uint8_t)0x00)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF0_TIM15         ((uint8_t)0x00)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF0_TIM16         ((uint8_t)0x00)  /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF0_TIM17         ((uint8_t)0x00)  /*!< TIM17 Alternate Function mapping */
+#define GPIO_AF0_USART1        ((uint8_t)0x00)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF0_USART2        ((uint8_t)0x00)  /*!< USART2 Alternate Function mapping */
+#define GPIO_AF0_USART3        ((uint8_t)0x00)  /*!< USART3 Alternate Function mapping */
+#define GPIO_AF0_USART4        ((uint8_t)0x00)  /*!< USART4 Alternate Function mapping */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_EVENTOUT      ((uint8_t)0x01)  /*!< EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /*!< IR Alternate Function mapping */
+#define GPIO_AF1_OSC           ((uint8_t)0x01)  /*!< OSC (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF1_SPI1          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF1_SPI2          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM3          ((uint8_t)0x01)  /*!< TIM3 Alternate Function mapping */
+#define GPIO_AF1_USART1        ((uint8_t)0x01)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2        ((uint8_t)0x01)  /*!< USART2 Alternate Function mapping */
+#define GPIO_AF1_USART4        ((uint8_t)0x01)  /*!< USART4 Alternate Function mapping */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /*!< TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM14         ((uint8_t)0x02)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF2_TIM15         ((uint8_t)0x02)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM16         ((uint8_t)0x02)  /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17         ((uint8_t)0x02)  /*!< TIM17 Alternate Function mapping */
+#define GPIO_AF2_USB           ((uint8_t)0x02)  /*!< USB Alternate Function mapping */
+
+
+/**
+  * @brief   AF 3 selection
+  */
+#define GPIO_AF3_USART5        ((uint8_t)0x03)  /*!< USART5 Alternate Function mapping */
+#define GPIO_AF3_USART6        ((uint8_t)0x03)  /*!< USART6 Alternate Function mapping */
+#define GPIO_AF3_MCO2          ((uint8_t)0x03)  /*!< MCO2 Alternate Function mapping */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_CRS           ((uint8_t)0x04)  /*!< CRS Alternate Function mapping */
+#define GPIO_AF4_SPI2          ((uint8_t)0x04)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF4_SPI3          ((uint8_t)0x04)  /*!< SPI3 Alternate Function mapping */
+#define GPIO_AF4_TIM14         ((uint8_t)0x04)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF4_TIM15         ((uint8_t)0x04)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF4_USART1        ((uint8_t)0x04)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF4_USART3        ((uint8_t)0x04)  /*!< USART3 Alternate Function mapping */
+#define GPIO_AF4_USART4        ((uint8_t)0x04)  /*!< USART4 Alternate Function mapping */
+#define GPIO_AF4_USART6        ((uint8_t)0x04)  /*!< USART6 Alternate Function mapping */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF5_TIM1          ((uint8_t)0x05)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF5_TIM15         ((uint8_t)0x05)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF5_TIM16         ((uint8_t)0x05)  /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17         ((uint8_t)0x05)  /*!< TIM17 Alternate Function mapping */
+#define GPIO_AF5_USART3        ((uint8_t)0x05)  /*!< USART3 Alternate Function mapping */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_I2C1          ((uint8_t)0x06)  /*!< I2C1 Alternate Function mapping */
+#define GPIO_AF6_I2C2          ((uint8_t)0x06)  /*!< I2C2 Alternate Function mapping */
+#define GPIO_AF6_I2C3          ((uint8_t)0x06)  /*!< I2C3 Alternate Function mapping */
+#define GPIO_AF6_USB           ((uint8_t)0x06)  /*!< USB Alternate Function mapping */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_EVENTOUT      ((uint8_t)0x07)  /*!< EVENTOUT Alternate Function mapping */
+
+/**
+  * @brief   AF 8 selection
+  */
+#define GPIO_AF8_I2C2          ((uint8_t)0x08)  /*!< I2C2 Alternate Function mapping */
+#define GPIO_AF8_USART5        ((uint8_t)0x08)  /*!< USART5 Alternate Function mapping */
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /*!< USART5 Alternate Function mapping */
+
+/**
+  * @brief   AF 9 selection
+  */
+#define GPIO_AF9_I2C3          ((uint8_t)0x09)  /*!< I2C3 Alternate Function mapping */
+#define GPIO_AF9_SPI3          ((uint8_t)0x09)  /*!< SPI3 Alternate Function mapping */
+#define GPIO_AF9_TIM4          ((uint8_t)0x09)  /*!< TIM4 Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x09)
+
+#endif
+
+
+#if defined (STM32G081xx) || defined (STM32G071xx)
+/*------------------------- STM32G081xx / STM32G071xx ------------------------*/
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_CEC           ((uint8_t)0x00)  /*!< CEC Alternate Function mapping */
+#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00)  /*!< EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_IR            ((uint8_t)0x00)  /*!< IR Alternate Function mapping */
+#define GPIO_AF0_LPTIM1        ((uint8_t)0x00)  /*!< LPTIM1 Alternate Function mapping */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /*!< MCO (MCO1) Alternate Function mapping */
+#define GPIO_AF0_OSC           ((uint8_t)0x00)  /*!< OSC (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF0_OSC32         ((uint8_t)0x00)  /*!< OSC32 (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /*!< SWJ (SWD) Alternate Function mapping */
+#define GPIO_AF0_SPI1          ((uint8_t)0x00)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF0_SPI2          ((uint8_t)0x00)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF0_TIM14         ((uint8_t)0x00)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF0_USART1        ((uint8_t)0x00)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF0_USART2        ((uint8_t)0x00)  /*!< USART2 Alternate Function mapping */
+#define GPIO_AF0_USART3        ((uint8_t)0x00)  /*!< USART3 Alternate Function mapping */
+#define GPIO_AF0_UCPD1         ((uint8_t)0x00)  /*!< UCPD1 Alternate Function mapping */
+#define GPIO_AF0_UCPD2         ((uint8_t)0x00)  /*!< UCPD2 Alternate Function mapping */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_CEC           ((uint8_t)0x01)  /*!< CEC Alternate Function mapping */
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /*!< IR Alternate Function mapping */
+#define GPIO_AF1_LPUART1       ((uint8_t)0x01)  /*!< LPUART1 Alternate Function mapping */
+#define GPIO_AF1_OSC           ((uint8_t)0x01)  /*!< OSC (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF1_SPI1          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF1_SPI2          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM3          ((uint8_t)0x01)  /*!< TIM3 Alternate Function mapping */
+#define GPIO_AF1_USART1        ((uint8_t)0x01)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2        ((uint8_t)0x01)  /*!< USART2 Alternate Function mapping */
+#define GPIO_AF1_USART4        ((uint8_t)0x01)  /*!< USART4 Alternate Function mapping */
+#define GPIO_AF1_UCPD1         ((uint8_t)0x01)  /*!< UCPD1 Alternate Function mapping */
+#define GPIO_AF1_UCPD2         ((uint8_t)0x01)  /*!< UCPD2 Alternate Function mapping */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_LPTIM1        ((uint8_t)0x02)  /*!< LPTIM1 Alternate Function mapping */
+#define GPIO_AF2_LPTIM2        ((uint8_t)0x02)  /*!< LPTIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /*!< TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM14         ((uint8_t)0x02)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF2_TIM15         ((uint8_t)0x02)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM16         ((uint8_t)0x02)  /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17         ((uint8_t)0x02)  /*!< TIM17 Alternate Function mapping */
+
+/**
+  * @brief   AF 3 selection
+  */
+#define GPIO_AF3_UCPD1         ((uint8_t)0x03)  /*!< UCPD1 Alternate Function mapping */
+#define GPIO_AF3_UCPD2         ((uint8_t)0x03)  /*!< UCPD2 Alternate Function mapping */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_SPI2          ((uint8_t)0x04)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF4_TIM14         ((uint8_t)0x04)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF4_TIM15         ((uint8_t)0x04)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF4_USART1        ((uint8_t)0x04)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF4_USART3        ((uint8_t)0x04)  /*!< USART3 Alternate Function mapping */
+#define GPIO_AF4_USART4        ((uint8_t)0x04)  /*!< USART4 Alternate Function mapping */
+#define GPIO_AF4_UCPD1         ((uint8_t)0x04)  /*!< UCPD1 Alternate Function mapping */
+#define GPIO_AF4_UCPD2         ((uint8_t)0x04)  /*!< UCPD2 Alternate Function mapping */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_LPTIM1        ((uint8_t)0x05)  /*!< LPTIM1 Alternate Function mapping */
+#define GPIO_AF5_LPTIM2        ((uint8_t)0x05)  /*!< LPTIM2 Alternate Function mapping */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF5_TIM1          ((uint8_t)0x05)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF5_TIM15         ((uint8_t)0x05)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF5_TIM16         ((uint8_t)0x05)  /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17         ((uint8_t)0x05)  /*!< TIM17 Alternate Function mapping */
+#define GPIO_AF5_USART3        ((uint8_t)0x05)  /*!< USART3 Alternate Function mapping */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_I2C1          ((uint8_t)0x06)  /*!< I2C1 Alternate Function mapping */
+#define GPIO_AF6_I2C2          ((uint8_t)0x06)  /*!< I2C2 Alternate Function mapping */
+#define GPIO_AF6_LPUART1       ((uint8_t)0x06)  /*!< LPUART1 Alternate Function mapping */
+#define GPIO_AF6_UCPD1         ((uint8_t)0x06)  /*!< UCPD1 Alternate Function mapping */
+#define GPIO_AF6_UCPD2         ((uint8_t)0x06)  /*!< UCPD2 Alternate Function mapping */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_COMP1         ((uint8_t)0x07)  /*!< COMP1 Alternate Function mapping */
+#define GPIO_AF7_COMP2         ((uint8_t)0x07)  /*!< COMP2 Alternate Function mapping */
+#define GPIO_AF7_EVENTOUT      ((uint8_t)0x07)  /*!< EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
+
+#endif /* STM32G081xx || STM32G071xx */
+
+#if defined (STM32G070xx)
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00)  /*!< EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_IR            ((uint8_t)0x00)  /*!< IR Alternate Function mapping */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /*!< MCO (MCO1) Alternate Function mapping */
+#define GPIO_AF0_OSC           ((uint8_t)0x00)  /*!< OSC (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF0_OSC32         ((uint8_t)0x00)  /*!< OSC32 (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /*!< SWJ (SWD) Alternate Function mapping */
+#define GPIO_AF0_SPI1          ((uint8_t)0x00)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF0_SPI2          ((uint8_t)0x00)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF0_TIM14         ((uint8_t)0x00)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF0_USART1        ((uint8_t)0x00)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF0_USART2        ((uint8_t)0x00)  /*!< USART2 Alternate Function mapping */
+#define GPIO_AF0_USART3        ((uint8_t)0x00)  /*!< USART3 Alternate Function mapping */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /*!< IR Alternate Function mapping */
+#define GPIO_AF1_OSC           ((uint8_t)0x01)  /*!< OSC (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF1_SPI1          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF1_SPI2          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM3          ((uint8_t)0x01)  /*!< TIM3 Alternate Function mapping */
+#define GPIO_AF1_USART1        ((uint8_t)0x01)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2        ((uint8_t)0x01)  /*!< USART2 Alternate Function mapping */
+#define GPIO_AF1_USART4        ((uint8_t)0x01)  /*!< USART4 Alternate Function mapping */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM14         ((uint8_t)0x02)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF2_TIM15         ((uint8_t)0x02)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM16         ((uint8_t)0x02)  /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17         ((uint8_t)0x02)  /*!< TIM17 Alternate Function mapping */
+
+/**
+  * @brief   AF 3 selection
+  */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_SPI2          ((uint8_t)0x04)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF4_TIM14         ((uint8_t)0x04)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF4_TIM15         ((uint8_t)0x04)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF4_USART1        ((uint8_t)0x04)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF4_USART3        ((uint8_t)0x04)  /*!< USART3 Alternate Function mapping */
+#define GPIO_AF4_USART4        ((uint8_t)0x04)  /*!< USART4 Alternate Function mapping */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF5_TIM1          ((uint8_t)0x05)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF5_TIM15         ((uint8_t)0x05)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF5_TIM16         ((uint8_t)0x05)  /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17         ((uint8_t)0x05)  /*!< TIM17 Alternate Function mapping */
+#define GPIO_AF5_USART3        ((uint8_t)0x05)  /*!< USART3 Alternate Function mapping */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_I2C1          ((uint8_t)0x06)  /*!< I2C1 Alternate Function mapping */
+#define GPIO_AF6_I2C2          ((uint8_t)0x06)  /*!< I2C2 Alternate Function mapping */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_EVENTOUT      ((uint8_t)0x07)  /*!< EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
+
+#endif /* STM32G070xx */
+
+#if defined (STM32G051xx) || defined (STM32G061xx)
+/*------------------------- STM32G061xx / STM32G051xx ------------------------*/
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00)  /*!< EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_IR            ((uint8_t)0x00)  /*!< IR Alternate Function mapping */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /*!< MCO (MCO1) Alternate Function mapping */
+#define GPIO_AF0_OSC           ((uint8_t)0x00)  /*!< OSC (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF0_OSC32         ((uint8_t)0x00)  /*!< OSC32 (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /*!< SWJ (SWD) Alternate Function mapping */
+#define GPIO_AF0_SPI1          ((uint8_t)0x00)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF0_SPI2          ((uint8_t)0x00)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF0_TIM14         ((uint8_t)0x00)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF0_USART1        ((uint8_t)0x00)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF0_USART2        ((uint8_t)0x00)  /*!< USART2 Alternate Function mapping */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /*!< IR Alternate Function mapping */
+#define GPIO_AF1_LPUART1       ((uint8_t)0x01)  /*!< LPUART1 Alternate Function mapping */
+#define GPIO_AF1_OSC           ((uint8_t)0x01)  /*!< OSC (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF1_SPI2          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM3          ((uint8_t)0x01)  /*!< TIM3 Alternate Function mapping */
+#define GPIO_AF1_USART1        ((uint8_t)0x01)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2        ((uint8_t)0x01)  /*!< USART2 Alternate Function mapping */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /*!< TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM14         ((uint8_t)0x02)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF2_TIM15         ((uint8_t)0x02)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM16         ((uint8_t)0x02)  /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17         ((uint8_t)0x02)  /*!< TIM17 Alternate Function mapping */
+
+/**
+  * @brief   AF 3 selection
+  */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_SPI2          ((uint8_t)0x04)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF4_TIM14         ((uint8_t)0x04)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF4_TIM15         ((uint8_t)0x04)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF4_USART1        ((uint8_t)0x04)  /*!< USART1 Alternate Function mapping */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_LPTIM1        ((uint8_t)0x05)  /*!< LPTIM1 Alternate Function mapping */
+#define GPIO_AF5_LPTIM2        ((uint8_t)0x05)  /*!< LPTIM2 Alternate Function mapping */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF5_TIM1          ((uint8_t)0x05)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF5_TIM15         ((uint8_t)0x05)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF5_TIM16         ((uint8_t)0x05)  /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17         ((uint8_t)0x05)  /*!< TIM17 Alternate Function mapping */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_I2C1          ((uint8_t)0x06)  /*!< I2C1 Alternate Function mapping */
+#define GPIO_AF6_I2C2          ((uint8_t)0x06)  /*!< I2C2 Alternate Function mapping */
+#define GPIO_AF6_LPUART1       ((uint8_t)0x06)  /*!< LPUART1 Alternate Function mapping */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_COMP1         ((uint8_t)0x07)  /*!< COMP1 Alternate Function mapping */
+#define GPIO_AF7_COMP2         ((uint8_t)0x07)  /*!< COMP2 Alternate Function mapping */
+#define GPIO_AF7_EVENTOUT      ((uint8_t)0x07)  /*!< EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
+
+#endif /* STM32G051xx || STM32G061xx */
+
+#if defined (STM32G050xx)
+/*------------------------- STM32G050xx --------------------------------------*/
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00)  /*!< EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_IR            ((uint8_t)0x00)  /*!< IR Alternate Function mapping */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /*!< MCO (MCO1) Alternate Function mapping */
+#define GPIO_AF0_OSC           ((uint8_t)0x00)  /*!< OSC (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF0_OSC32         ((uint8_t)0x00)  /*!< OSC32 (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /*!< SWJ (SWD) Alternate Function mapping */
+#define GPIO_AF0_SPI1          ((uint8_t)0x00)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF0_SPI2          ((uint8_t)0x00)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF0_TIM14         ((uint8_t)0x00)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF0_USART1        ((uint8_t)0x00)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF0_USART2        ((uint8_t)0x00)  /*!< USART2 Alternate Function mapping */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /*!< IR Alternate Function mapping */
+#define GPIO_AF1_OSC           ((uint8_t)0x01)  /*!< OSC (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF1_SPI2          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM3          ((uint8_t)0x01)  /*!< TIM3 Alternate Function mapping */
+#define GPIO_AF1_USART1        ((uint8_t)0x01)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2        ((uint8_t)0x01)  /*!< USART2 Alternate Function mapping */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM14         ((uint8_t)0x02)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF2_TIM15         ((uint8_t)0x02)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM16         ((uint8_t)0x02)  /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17         ((uint8_t)0x02)  /*!< TIM17 Alternate Function mapping */
+
+/**
+  * @brief   AF 3 selection
+  */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_SPI2          ((uint8_t)0x04)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF4_TIM14         ((uint8_t)0x04)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF4_TIM15         ((uint8_t)0x04)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF4_USART1        ((uint8_t)0x04)  /*!< USART1 Alternate Function mapping */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF5_TIM1          ((uint8_t)0x05)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF5_TIM15         ((uint8_t)0x05)  /*!< TIM15 Alternate Function mapping */
+#define GPIO_AF5_TIM16         ((uint8_t)0x05)  /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17         ((uint8_t)0x05)  /*!< TIM17 Alternate Function mapping */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_I2C1          ((uint8_t)0x06)  /*!< I2C1 Alternate Function mapping */
+#define GPIO_AF6_I2C2          ((uint8_t)0x06)  /*!< I2C2 Alternate Function mapping */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_EVENTOUT      ((uint8_t)0x07)  /*!< EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
+
+#endif /* STM32G050xx */
+
+#if defined (STM32G031xx) || defined (STM32G041xx)
+/*------------------------- STM32G041xx / STM32G031xx ------------------------*/
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00)  /*!< EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_IR            ((uint8_t)0x00)  /*!< IR Alternate Function mapping */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /*!< MCO (MCO1) Alternate Function mapping */
+#define GPIO_AF0_OSC           ((uint8_t)0x00)  /*!< OSC (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF0_OSC32         ((uint8_t)0x00)  /*!< OSC32 (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /*!< SWJ (SWD) Alternate Function mapping */
+#define GPIO_AF0_SPI1          ((uint8_t)0x00)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF0_SPI2          ((uint8_t)0x00)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF0_TIM14         ((uint8_t)0x00)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF0_USART1        ((uint8_t)0x00)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF0_USART2        ((uint8_t)0x00)  /*!< USART2 Alternate Function mapping */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /*!< IR Alternate Function mapping */
+#define GPIO_AF1_LPUART1       ((uint8_t)0x01)  /*!< LPUART1 Alternate Function mapping */
+#define GPIO_AF1_OSC           ((uint8_t)0x01)  /*!< OSC (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF1_SPI2          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM3          ((uint8_t)0x01)  /*!< TIM3 Alternate Function mapping */
+#define GPIO_AF1_USART1        ((uint8_t)0x01)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2        ((uint8_t)0x01)  /*!< USART2 Alternate Function mapping */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /*!< TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM14         ((uint8_t)0x02)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF2_TIM16         ((uint8_t)0x02)  /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17         ((uint8_t)0x02)  /*!< TIM17 Alternate Function mapping */
+
+/**
+  * @brief   AF 3 selection
+  */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_SPI2          ((uint8_t)0x04)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF4_TIM14         ((uint8_t)0x04)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF4_USART1        ((uint8_t)0x04)  /*!< USART1 Alternate Function mapping */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_LPTIM1        ((uint8_t)0x05)  /*!< LPTIM1 Alternate Function mapping */
+#define GPIO_AF5_LPTIM2        ((uint8_t)0x05)  /*!< LPTIM2 Alternate Function mapping */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF5_TIM1          ((uint8_t)0x05)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF5_TIM16         ((uint8_t)0x05)  /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17         ((uint8_t)0x05)  /*!< TIM17 Alternate Function mapping */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_I2C1          ((uint8_t)0x06)  /*!< I2C1 Alternate Function mapping */
+#define GPIO_AF6_I2C2          ((uint8_t)0x06)  /*!< I2C2 Alternate Function mapping */
+#define GPIO_AF6_LPUART1       ((uint8_t)0x06)  /*!< LPUART1 Alternate Function mapping */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_EVENTOUT      ((uint8_t)0x07)  /*!< EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
+
+#endif /* STM32G031xx || STM32G041xx */
+
+#if defined (STM32G030xx)
+/*------------------------- STM32G030xx --------------------------------------*/
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_EVENTOUT      ((uint8_t)0x00)  /*!< EVENTOUT Alternate Function mapping */
+#define GPIO_AF0_IR            ((uint8_t)0x00)  /*!< IR Alternate Function mapping */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /*!< MCO (MCO1) Alternate Function mapping */
+#define GPIO_AF0_OSC           ((uint8_t)0x00)  /*!< OSC (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF0_OSC32         ((uint8_t)0x00)  /*!< OSC32 (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /*!< SWJ (SWD) Alternate Function mapping */
+#define GPIO_AF0_SPI1          ((uint8_t)0x00)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF0_SPI2          ((uint8_t)0x00)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF0_TIM14         ((uint8_t)0x00)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF0_USART1        ((uint8_t)0x00)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF0_USART2        ((uint8_t)0x00)  /*!< USART2 Alternate Function mapping */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /*!< IR Alternate Function mapping */
+#define GPIO_AF1_OSC           ((uint8_t)0x01)  /*!< OSC (By pass and Enable) Alternate Function mapping */
+#define GPIO_AF1_SPI2          ((uint8_t)0x01)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM3          ((uint8_t)0x01)  /*!< TIM3 Alternate Function mapping */
+#define GPIO_AF1_USART1        ((uint8_t)0x01)  /*!< USART1 Alternate Function mapping */
+#define GPIO_AF1_USART2        ((uint8_t)0x01)  /*!< USART2 Alternate Function mapping */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM14         ((uint8_t)0x02)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF2_TIM16         ((uint8_t)0x02)  /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM17         ((uint8_t)0x02)  /*!< TIM17 Alternate Function mapping */
+
+/**
+  * @brief   AF 3 selection
+  */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_SPI2          ((uint8_t)0x04)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF4_TIM14         ((uint8_t)0x04)  /*!< TIM14 Alternate Function mapping */
+#define GPIO_AF4_USART1        ((uint8_t)0x04)  /*!< USART1 Alternate Function mapping */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */
+#define GPIO_AF5_TIM1          ((uint8_t)0x05)  /*!< TIM1 Alternate Function mapping */
+#define GPIO_AF5_TIM16         ((uint8_t)0x05)  /*!< TIM16 Alternate Function mapping */
+#define GPIO_AF5_TIM17         ((uint8_t)0x05)  /*!< TIM17 Alternate Function mapping */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_I2C1          ((uint8_t)0x06)  /*!< I2C1 Alternate Function mapping */
+#define GPIO_AF6_I2C2          ((uint8_t)0x06)  /*!< I2C2 Alternate Function mapping */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_EVENTOUT      ((uint8_t)0x07)  /*!< EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)         ((AF) <= (uint8_t)0x07)
+
+#endif /* STM32G030xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
+  * @{
+  */
+
+/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
+* @{
+  */
+#if defined(GPIOE)   
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\
+                                      ((__GPIOx__) == (GPIOB))? 1uL :\
+                                      ((__GPIOx__) == (GPIOC))? 2uL :\
+                                      ((__GPIOx__) == (GPIOD))? 3uL :\
+                                      ((__GPIOx__) == (GPIOE))? 4uL : 5uL)
+#else
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0uL :\
+                                      ((__GPIOx__) == (GPIOB))? 1uL :\
+                                      ((__GPIOx__) == (GPIOC))? 2uL :\
+                                      ((__GPIOx__) == (GPIOD))? 3uL : 5uL)
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G0xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h

@@ -0,0 +1,782 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_i2c.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_I2C_H
+#define STM32G0xx_HAL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal_def.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+  * @{
+  */
+
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+  * @brief  I2C Configuration Structure definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
+                                  This parameter calculated by referring to I2C initialization
+                                         section in Reference manual */
+
+  uint32_t OwnAddress1;         /*!< Specifies the first device own address.
+                                  This parameter can be a 7-bit or 10-bit address. */
+
+  uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_ADDRESSING_MODE */
+
+  uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
+
+  uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
+                                  This parameter can be a 7-bit address. */
+
+  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
+                                  This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
+
+  uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
+                                  This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
+
+  uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
+                                  This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
+
+} I2C_InitTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+  * @brief  HAL State structure definition
+  * @note  HAL I2C State value coding follow below described bitmap :\n
+  *          b7-b6  Error information\n
+  *             00 : No Error\n
+  *             01 : Abort (Abort user request on going)\n
+  *             10 : Timeout\n
+  *             11 : Error\n
+  *          b5     Peripheral initialization status\n
+  *             0  : Reset (peripheral not initialized)\n
+  *             1  : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
+  *          b4     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b3\n
+  *             0  : Ready or Busy (No Listen mode ongoing)\n
+  *             1  : Listen (peripheral in Address Listen Mode)\n
+  *          b2     Intrinsic process state\n
+  *             0  : Ready\n
+  *             1  : Busy (peripheral busy with some configuration or internal operations)\n
+  *          b1     Rx state\n
+  *             0  : Ready (no Rx operation ongoing)\n
+  *             1  : Busy (Rx operation ongoing)\n
+  *          b0     Tx state\n
+  *             0  : Ready (no Tx operation ongoing)\n
+  *             1  : Busy (Tx operation ongoing)
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
+  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
+  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
+  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
+  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
+  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
+  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
+  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
+  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
+
+} HAL_I2C_StateTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition
+  * @brief  HAL Mode structure definition
+  * @note  HAL I2C Mode value coding follow below described bitmap :\n
+  *          b7     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b6\n
+  *             0  : None\n
+  *             1  : Memory (HAL I2C communication is in Memory Mode)\n
+  *          b5\n
+  *             0  : None\n
+  *             1  : Slave (HAL I2C communication is in Slave Mode)\n
+  *          b4\n
+  *             0  : None\n
+  *             1  : Master (HAL I2C communication is in Master Mode)\n
+  *          b3-b2-b1-b0  (not used)\n
+  *             xxxx : Should be set to 0000
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
+  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
+  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
+  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
+
+} HAL_I2C_ModeTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition
+  * @brief  I2C Error Code definition
+  * @{
+  */
+#define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
+#define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
+#define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
+#define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
+#define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
+#define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
+#define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
+#define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
+#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)    /*!< DMA Parameter Error   */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define HAL_I2C_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+#define HAL_I2C_ERROR_INVALID_PARAM     (0x00000200U)    /*!< Invalid Parameters error  */
+/**
+  * @}
+  */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
+  * @brief  I2C handle Structure definition
+  * @{
+  */
+typedef struct __I2C_HandleTypeDef
+{
+  I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
+
+  I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
+
+  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
+
+  uint16_t                   XferSize;       /*!< I2C transfer size                         */
+
+  __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
+
+  __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
+                                                  be a value of @ref I2C_XFEROPTIONS */
+
+  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
+
+  HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);  /*!< I2C transfer IRQ handler function pointer */
+
+  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
+
+  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
+
+  HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
+
+  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
+
+  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
+
+  __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
+
+  __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Tx Transfer completed callback */
+  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Rx Transfer completed callback */
+  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Tx Transfer completed callback  */
+  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Rx Transfer completed callback  */
+  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);             /*!< I2C Listen Complete callback              */
+  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Tx Transfer completed callback */
+  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Rx Transfer completed callback */
+  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);                  /*!< I2C Error callback                        */
+  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Abort callback                        */
+
+  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< I2C Slave Address Match callback */
+
+  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);                /*!< I2C Msp Init callback                     */
+  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Msp DeInit callback                   */
+
+#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
+} I2C_HandleTypeDef;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL I2C Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */
+  HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */
+  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */
+  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */
+  HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */
+  HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */
+  HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */
+  HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */
+  HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */
+
+  HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */
+  HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */
+
+} HAL_I2C_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL I2C Callback pointer definition
+  */
+typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
+typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+  * @{
+  */
+
+/** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
+  * @{
+  */
+#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
+#define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME_NO_STOP          ((uint32_t)I2C_SOFTEND_MODE)
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define  I2C_OTHER_FRAME                (0x000000AAU)
+#define  I2C_OTHER_AND_LAST_FRAME       (0x0000AA00U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
+  * @{
+  */
+#define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
+#define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLE         (0x00000000U)
+#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
+  * @{
+  */
+#define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
+#define I2C_OA2_MASK01                  ((uint8_t)0x01U)
+#define I2C_OA2_MASK02                  ((uint8_t)0x02U)
+#define I2C_OA2_MASK03                  ((uint8_t)0x03U)
+#define I2C_OA2_MASK04                  ((uint8_t)0x04U)
+#define I2C_OA2_MASK05                  ((uint8_t)0x05U)
+#define I2C_OA2_MASK06                  ((uint8_t)0x06U)
+#define I2C_OA2_MASK07                  ((uint8_t)0x07U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
+  * @{
+  */
+#define I2C_GENERALCALL_DISABLE         (0x00000000U)
+#define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
+  * @{
+  */
+#define I2C_NOSTRETCH_DISABLE           (0x00000000U)
+#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
+/**
+  * @}
+  */
+
+/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
+  * @{
+  */
+#define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
+#define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
+  * @{
+  */
+#define I2C_DIRECTION_TRANSMIT          (0x00000000U)
+#define I2C_DIRECTION_RECEIVE           (0x00000001U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
+  * @{
+  */
+#define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
+#define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
+#define  I2C_SOFTEND_MODE               (0x00000000U)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
+  * @{
+  */
+#define  I2C_NO_STARTSTOP               (0x00000000U)
+#define  I2C_GENERATE_STOP              (uint32_t)(0x80000000U | I2C_CR2_STOP)
+#define  I2C_GENERATE_START_READ        (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+#define  I2C_GENERATE_START_WRITE       (uint32_t)(0x80000000U | I2C_CR2_START)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+  * @brief I2C Interrupt definition
+  *        Elements values convention: 0xXXXXXXXX
+  *           - XXXXXXXX  : Interrupt control mask
+  * @{
+  */
+#define I2C_IT_ERRI                     I2C_CR1_ERRIE
+#define I2C_IT_TCI                      I2C_CR1_TCIE
+#define I2C_IT_STOPI                    I2C_CR1_STOPIE
+#define I2C_IT_NACKI                    I2C_CR1_NACKIE
+#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
+#define I2C_IT_RXI                      I2C_CR1_RXIE
+#define I2C_IT_TXI                      I2C_CR1_TXIE
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+  * @{
+  */
+#define I2C_FLAG_TXE                    I2C_ISR_TXE
+#define I2C_FLAG_TXIS                   I2C_ISR_TXIS
+#define I2C_FLAG_RXNE                   I2C_ISR_RXNE
+#define I2C_FLAG_ADDR                   I2C_ISR_ADDR
+#define I2C_FLAG_AF                     I2C_ISR_NACKF
+#define I2C_FLAG_STOPF                  I2C_ISR_STOPF
+#define I2C_FLAG_TC                     I2C_ISR_TC
+#define I2C_FLAG_TCR                    I2C_ISR_TCR
+#define I2C_FLAG_BERR                   I2C_ISR_BERR
+#define I2C_FLAG_ARLO                   I2C_ISR_ARLO
+#define I2C_FLAG_OVR                    I2C_ISR_OVR
+#define I2C_FLAG_PECERR                 I2C_ISR_PECERR
+#define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
+#define I2C_FLAG_ALERT                  I2C_ISR_ALERT
+#define I2C_FLAG_BUSY                   I2C_ISR_BUSY
+#define I2C_FLAG_DIR                    I2C_ISR_DIR
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+  * @{
+  */
+
+/** @brief Reset I2C handle state.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \
+                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;       \
+                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
+                                                                  } while(0)
+#else
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+#endif
+
+/** @brief  Enable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief  Disable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief  Check whether the specified I2C interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified I2C flag is set or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
+  *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
+  *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *            @arg @ref I2C_FLAG_BUSY    Bus busy
+  *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
+  *
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define I2C_FLAG_MASK  (0x0001FFFFU)
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+/** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *
+  * @retval None
+  */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
+                                                                                 : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+
+/** @brief  Enable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))
+
+/** @brief  Disable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+/**
+  * @}
+  */
+
+/* Include I2C HAL Extended module */
+#include "stm32g0xx_hal_i2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions******************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* IO operation functions  ****************************************************/
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+/******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+
+/******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+  * @{
+  */
+/* Peripheral State, Mode and Error functions  *********************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
+uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macro I2C Private Macros
+  * @{
+  */
+
+#define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
+                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
+                                         ((MASK) == I2C_OA2_MASK01) || \
+                                         ((MASK) == I2C_OA2_MASK02) || \
+                                         ((MASK) == I2C_OA2_MASK03) || \
+                                         ((MASK) == I2C_OA2_MASK04) || \
+                                         ((MASK) == I2C_OA2_MASK05) || \
+                                         ((MASK) == I2C_OA2_MASK06) || \
+                                         ((MASK) == I2C_OA2_MASK07))
+
+#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
+                                         ((CALL) == I2C_GENERALCALL_ENABLE))
+
+#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+
+#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+
+#define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
+                                         ((MODE) == I2C_AUTOEND_MODE) || \
+                                         ((MODE) == I2C_SOFTEND_MODE))
+
+#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
+                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
+                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
+                                         ((REQUEST) == I2C_NO_STARTSTOP))
+
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
+                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
+                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
+                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
+                                                   ((REQUEST) == I2C_LAST_FRAME)           || \
+                                                   ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \
+                                                   IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \
+                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
+
+#define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+
+#define I2C_GET_ADDR_MATCH(__HANDLE__)            ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
+#define I2C_GET_DIR(__HANDLE__)                   ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
+#define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
+#define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
+
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32g0xx_hal_i2c.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32G0xx_HAL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h

@@ -0,0 +1,166 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_i2c_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_I2C_EX_H
+#define STM32G0xx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal_def.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2CEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
+  * @{
+  */
+#define I2C_ANALOGFILTER_ENABLE         0x00000000U
+#define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
+/**
+  * @}
+  */
+
+/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
+  * @{
+  */
+#define I2C_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */
+#define I2C_FASTMODEPLUS_PA9            SYSCFG_CFGR1_I2C_PA9_FMP                        /*!< Enable Fast Mode Plus on PA9       */
+#define I2C_FASTMODEPLUS_PA10           SYSCFG_CFGR1_I2C_PA10_FMP                       /*!< Enable Fast Mode Plus on PA10      */
+#define I2C_FASTMODEPLUS_PB6            SYSCFG_CFGR1_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
+#define I2C_FASTMODEPLUS_PB7            SYSCFG_CFGR1_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
+#define I2C_FASTMODEPLUS_PB8            SYSCFG_CFGR1_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
+#define I2C_FASTMODEPLUS_PB9            SYSCFG_CFGR1_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
+#define I2C_FASTMODEPLUS_I2C1           SYSCFG_CFGR1_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
+#define I2C_FASTMODEPLUS_I2C2           SYSCFG_CFGR1_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
+#if defined(SYSCFG_CFGR1_I2C3_FMP)
+#define I2C_FASTMODEPLUS_I2C3           SYSCFG_CFGR1_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C3           (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported  */
+#endif
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
+  * @brief    Extended features functions
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
+  * @{
+  */
+#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
+                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
+
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
+                                         ((((__CONFIG__) & (I2C_FASTMODEPLUS_PA9))  == I2C_FASTMODEPLUS_PA9)     || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PA10)) == I2C_FASTMODEPLUS_PA10)    || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB6))  == I2C_FASTMODEPLUS_PB6)     || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7))  == I2C_FASTMODEPLUS_PB7)     || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8))  == I2C_FASTMODEPLUS_PB8)     || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9))  == I2C_FASTMODEPLUS_PB9)     || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)    || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)    || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)))
+
+
+
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32g0xx_hal_i2c_ex.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G0xx_HAL_I2C_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_iwdg.h

@@ -0,0 +1,242 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_iwdg.h
+  * @author  MCD Application Team
+  * @brief   Header file of IWDG HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_IWDG_H
+#define STM32G0xx_HAL_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal_def.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup IWDG IWDG
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Types IWDG Exported Types
+  * @{
+  */
+
+/**
+  * @brief  IWDG Init structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
+                            This parameter can be a value of @ref IWDG_Prescaler */
+
+  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+  uint32_t Window;     /*!< Specifies the window value to be compared to the down-counter.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+} IWDG_InitTypeDef;
+
+/**
+  * @brief  IWDG Handle Structure definition
+  */
+typedef struct
+{
+  IWDG_TypeDef                 *Instance;  /*!< Register base address    */
+
+  IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
+} IWDG_HandleTypeDef;
+
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
+  * @{
+  */
+
+/** @defgroup IWDG_Prescaler IWDG Prescaler
+  * @{
+  */
+#define IWDG_PRESCALER_4                0x00000000u                                     /*!< IWDG prescaler set to 4   */
+#define IWDG_PRESCALER_8                IWDG_PR_PR_0                                    /*!< IWDG prescaler set to 8   */
+#define IWDG_PRESCALER_16               IWDG_PR_PR_1                                    /*!< IWDG prescaler set to 16  */
+#define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 32  */
+#define IWDG_PRESCALER_64               IWDG_PR_PR_2                                    /*!< IWDG prescaler set to 64  */
+#define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)                   /*!< IWDG prescaler set to 256 */
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Window_option IWDG Window option
+  * @{
+  */
+#define IWDG_WINDOW_DISABLE             IWDG_WINR_WIN
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable the IWDG peripheral.
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
+
+/**
+  * @brief  Reload IWDG counter with value defined in the reload register
+  *         (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
+  * @{
+  */
+
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
+  * @{
+  */
+/* Initialization/Start functions  ********************************************/
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_Private_Constants IWDG Private Constants
+  * @{
+  */
+
+/**
+  * @brief  IWDG Key Register BitMask
+  */
+#define IWDG_KEY_RELOAD                 0x0000AAAAu  /*!< IWDG Reload Counter Enable   */
+#define IWDG_KEY_ENABLE                 0x0000CCCCu  /*!< IWDG Peripheral Enable       */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555u  /*!< IWDG KR Write Access Enable  */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000u  /*!< IWDG KR Write Access Disable */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Macros IWDG Private Macros
+  * @{
+  */
+
+/**
+  * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+
+/**
+  * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+  * @param  __HANDLE__  IWDG handle
+  * @retval None
+  */
+#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
+
+/**
+  * @brief  Check IWDG prescaler value.
+  * @param  __PRESCALER__  IWDG prescaler value
+  * @retval None
+  */
+#define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_256))
+
+/**
+  * @brief  Check IWDG reload value.
+  * @param  __RELOAD__  IWDG reload value
+  * @retval None
+  */
+#define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)
+
+/**
+  * @brief  Check IWDG window value.
+  * @param  __WINDOW__  IWDG window value
+  * @retval None
+  */
+#define IS_IWDG_WINDOW(__WINDOW__)            ((__WINDOW__) <= IWDG_WINR_WIN)
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G0xx_HAL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h

@@ -0,0 +1,328 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_PWR_H
+#define STM32G0xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal_def.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWR PWR
+  * @brief PWR HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PWR_Exported_Types PWR Exported Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+/** @defgroup PWR_WakeUp_Pins  PWR WakeUp pins
+  * @{
+  */
+#define PWR_WAKEUP_PIN1                     PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level detection) */
+#define PWR_WAKEUP_PIN2                     PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level detection) */
+#if defined(PWR_CR3_EWUP3)
+#define PWR_WAKEUP_PIN3                     PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level detection) */
+#endif
+#define PWR_WAKEUP_PIN4                     PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level detection) */
+#if defined(PWR_CR3_EWUP5)
+#define PWR_WAKEUP_PIN5                     PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level detection) */
+#endif
+#define PWR_WAKEUP_PIN6                     PWR_CR3_EWUP6  /*!< Wakeup pin 6 (with high level detection) */
+#define PWR_WAKEUP_PIN1_HIGH                PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level detection) */
+#define PWR_WAKEUP_PIN2_HIGH                PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level detection) */
+#if defined(PWR_CR3_EWUP3)
+#define PWR_WAKEUP_PIN3_HIGH                PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level detection) */
+#endif
+#define PWR_WAKEUP_PIN4_HIGH                PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level detection) */
+#if defined(PWR_CR3_EWUP5)
+#define PWR_WAKEUP_PIN5_HIGH                PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level detection) */
+#endif
+#define PWR_WAKEUP_PIN6_HIGH                PWR_CR3_EWUP6  /*!< Wakeup pin 6 (with high level detection) */
+#define PWR_WAKEUP_PIN1_LOW                 ((PWR_CR4_WP1 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level detection) */
+#define PWR_WAKEUP_PIN2_LOW                 ((PWR_CR4_WP2 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level detection) */
+#if defined(PWR_CR3_EWUP3)
+#define PWR_WAKEUP_PIN3_LOW                 ((PWR_CR4_WP3 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level detection) */
+#endif
+#define PWR_WAKEUP_PIN4_LOW                 ((PWR_CR4_WP4 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level detection) */
+#if defined(PWR_CR3_EWUP5)
+#define PWR_WAKEUP_PIN5_LOW                 ((PWR_CR4_WP5 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level detection) */
+#endif
+#define PWR_WAKEUP_PIN6_LOW                 ((PWR_CR4_WP6 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP6) /*!< Wakeup pin 6 (with low level detection) */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Low_Power_Mode_Selection  PWR Low Power Mode Selection
+  * @{
+  */
+#define PWR_LOWPOWERMODE_STOP0              (0x00000000u)                       /*!< Stop 0: stop mode with main regulator */
+#define PWR_LOWPOWERMODE_STOP1              (PWR_CR1_LPMS_0)                    /*!< Stop 1: stop mode with low power regulator */
+#define PWR_LOWPOWERMODE_STANDBY            (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1)   /*!< Standby mode */
+#if defined(PWR_SHDW_SUPPORT)
+#define PWR_LOWPOWERMODE_SHUTDOWN           (PWR_CR1_LPMS_2)                    /*!< Shutdown mode */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode  PWR regulator mode
+  * @{
+  */
+#define PWR_MAINREGULATOR_ON                (0x00000000u)  /*!< Regulator in main mode      */
+#define PWR_LOWPOWERREGULATOR_ON            PWR_CR1_LPR    /*!< Regulator in low-power mode */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_SLEEP_mode_entry  PWR SLEEP mode entry
+  * @{
+  */
+#define PWR_SLEEPENTRY_WFI                  ((uint8_t)0x01u)        /*!< Wait For Interruption instruction to enter Sleep mode */
+#define PWR_SLEEPENTRY_WFE                  ((uint8_t)0x02u)        /*!< Wait For Event instruction to enter Sleep mode        */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_STOP_mode_entry  PWR STOP mode entry
+  * @{
+  */
+#define PWR_STOPENTRY_WFI                   ((uint8_t)0x01u)        /*!< Wait For Interruption instruction to enter Stop mode */
+#define PWR_STOPENTRY_WFE                   ((uint8_t)0x02u)        /*!< Wait For Event instruction to enter Stop mode        */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag  PWR Status Flags
+  * @brief  Elements values convention: 0000 00XX 000Y YYYYb
+  *           - Y YYYY  : Flag position in the XX register (5 bits)
+  *           - XX  : Status register (2 bits)
+  *                 - 01: SR1 register
+  *                 - 10: SR2 register
+  *         The only exception is PWR_FLAG_WU, encompassing all
+  *         wake-up flags and set to PWR_SR1_WUF.
+  * @{
+  */
+#define PWR_FLAG_WUF1                       (0x00010000u | PWR_SR1_WUF1)      /*!< Wakeup event on wakeup pin 1 */
+#define PWR_FLAG_WUF2                       (0x00010000u | PWR_SR1_WUF2)      /*!< Wakeup event on wakeup pin 2 */
+#if defined(PWR_CR3_EWUP3)
+#define PWR_FLAG_WUF3                       (0x00010000u | PWR_SR1_WUF3)      /*!< Wakeup event on wakeup pin 3 */
+#endif
+#define PWR_FLAG_WUF4                       (0x00010000u | PWR_SR1_WUF4)      /*!< Wakeup event on wakeup pin 4 */
+#if defined(PWR_CR3_EWUP5)
+#define PWR_FLAG_WUF5                       (0x00010000u | PWR_SR1_WUF5)      /*!< Wakeup event on wakeup pin 5 */
+#endif
+#define PWR_FLAG_WUF6                       (0x00010000u | PWR_SR1_WUF6)      /*!< Wakeup event on wakeup pin 6 */
+#define PWR_FLAG_WUF                        (0x00010000u | PWR_SR1_WUF)       /*!< Wakeup event on all wakeup pin  */
+#define PWR_FLAG_SB                         (0x00010000u | PWR_SR1_SBF)       /*!< Standby flag */
+#define PWR_FLAG_WUFI                       (0x00010000u | PWR_SR1_WUFI)      /*!< Wakeup on internal wakeup line */
+#define PWR_FLAG_FLASH_READY                (0x00020000u | PWR_SR2_FLASH_RDY) /*!< Flash ready */
+#define PWR_FLAG_REGLPS                     (0x00020000u | PWR_SR2_REGLPS)    /*!< Regulator Low Power started */
+#define PWR_FLAG_REGLPF                     (0x00020000u | PWR_SR2_REGLPF)    /*!< Regulator Low Power flag */
+#if defined(PWR_PVD_SUPPORT)
+#define PWR_FLAG_PVDO                       (0x00020000u | PWR_SR2_PVDO)      /*!< Power Voltage Detector output */
+#endif
+#if defined(PWR_PVM_SUPPORT)
+#define PWR_FLAG_PVMO_USB                   (0x00020000u | PWR_SR2_PVMO_USB)  /*!< Power Voltage Monitoring output */
+#endif
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macros  PWR Exported Macros
+  * @{
+  */
+/** @brief  Check whether or not a specific PWR flag is set.
+  * @param  __FLAG__  specifies the flag to check.
+  *         This parameter can be one a combination of following values:
+  *            @arg PWR_FLAG_WUF1: Wake Up Flag 1. Indicates that a wakeup event
+  *                  was received from the WKUP pin 1.
+  *            @arg PWR_FLAG_WUF2: Wake Up Flag 2. Indicates that a wakeup event
+  *                  was received from the WKUP pin 2.
+  *            @arg PWR_FLAG_WUF3: Wake Up Flag 3. Indicates that a wakeup event
+  *                  was received from the WKUP pin 3. (*)
+  *            @arg PWR_FLAG_WUF4: Wake Up Flag 4. Indicates that a wakeup event
+  *                  was received from the WKUP pin 4.
+  *            @arg PWR_FLAG_WUF5: Wake Up Flag 5. Indicates that a wakeup event
+  *                  was received from the WKUP pin 5. (*)
+  *            @arg PWR_FLAG_WUF6: Wake Up Flag 6. Indicates that a wakeup event
+  *                  was received from the WKUP pin 6.
+  *            @arg PWR_FLAG_SB: StandBy Flag. Indicates that the system
+  *                  entered StandBy mode.
+  *            @arg PWR_FLAG_WUFI: Wake-Up Flag Internal. Set when a wakeup is
+  *                 detected on the internal wakeup line.
+  *         OR a combination of following values:
+  *            @arg PWR_FLAG_FLASH_READY: Flash is ready. Indicates whether flash
+  *                 can be used or not
+  *            @arg PWR_FLAG_REGLPS: Low Power Regulator Started. Indicates whether
+  *                 or not the low-power regulator is ready.
+  *            @arg PWR_FLAG_REGLPF: Low Power Regulator Flag. Indicates whether the
+  *                 regulator is ready in main mode or is in low-power mode.
+  * @if defined(STM32G081xx)
+  *            @arg PWR_FLAG_PVDO: Power Voltage Detector Output. Indicates whether
+  *                 VDD voltage is below or above the selected PVD threshold.
+  * @endif
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_FLAG(__FLAG__)        (((__FLAG__) & 0x00010000u) ?\
+                                            ((PWR->SR1 & ((__FLAG__) & ~0x00030000u)) == ((__FLAG__) & ~0x00030000u)) :\
+                                            ((PWR->SR2 & ((__FLAG__) & ~0x00030000u)) == ((__FLAG__) & ~0x00030000u)))
+
+/** @brief  Clear a specific PWR flag.
+  * @param  __FLAG__  specifies the flag to clear.
+  *         This parameter can be a combination of following values:
+  *            @arg PWR_FLAG_WUF1: Wake Up Flag 1. Indicates that a wakeup event
+  *                  was received from the WKUP pin 1.
+  *            @arg PWR_FLAG_WUF2: Wake Up Flag 2. Indicates that a wakeup event
+  *                  was received from the WKUP pin 2.
+  *            @arg PWR_FLAG_WUF3: Wake Up Flag 3. Indicates that a wakeup event
+  *                  was received from the WKUP pin 3. (*)
+  *            @arg PWR_FLAG_WUF4: Wake Up Flag 4. Indicates that a wakeup event
+  *                  was received from the WKUP pin 4.
+  *            @arg PWR_FLAG_WUF5: Wake Up Flag 5. Indicates that a wakeup event
+  *                  was received from the WKUP pin 5. (*)
+  *            @arg PWR_FLAG_WUF6: Wake Up Flag 6. Indicates that a wakeup event
+  *                  was received from the WKUP pin 6.
+  *            @arg PWR_FLAG_WUF: Encompasses all Wake Up Flags.
+  *            @arg PWR_FLAG_SB: Standby Flag. Indicates that the system
+  *                  entered Standby mode.
+  * @retval None
+  */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__)      (PWR->SCR = (__FLAG__))
+
+/**
+  * @}
+  */
+
+/* Private constants-------------------------------------------------------*/
+/** @defgroup PWR_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
+  * @{
+  */
+#define PWR_WUP_POLARITY_SHIFT              0x08u   /*!< Internal constant used to retrieve wakeup pin polariry */
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup PWR_Private_Macros  PWR Private Macros
+  * @{
+  */
+
+#define IS_PWR_WAKEUP_PIN(PIN)                    ((((PIN) & ((PWR_CR4_WP << 8U) | (PWR_CR3_EWUP))) != 0x00000000u) && \
+                                                   (((PIN) & ~((PWR_CR4_WP << 8U) | (PWR_CR3_EWUP))) == 0x00000000u))
+
+#define IS_PWR_REGULATOR(REGULATOR)               (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+                                                   ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+
+#define IS_PWR_SLEEP_ENTRY(ENTRY)                 (((ENTRY) == PWR_SLEEPENTRY_WFI) || \
+                                                   ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+#define IS_PWR_STOP_ENTRY(ENTRY)                  (((ENTRY) == PWR_STOPENTRY_WFI) || \
+                                                   ((ENTRY) == PWR_STOPENTRY_WFE))
+/**
+  * @}
+  */
+
+/* Include PWR HAL Extended module */
+#include "stm32g0xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWR_Exported_Functions  PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_Exported_Functions_Group1  Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions *******************************/
+void              HAL_PWR_DeInit(void);
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Functions_Group2  Peripheral Control functions
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+void              HAL_PWR_EnableBkUpAccess(void);
+void              HAL_PWR_DisableBkUpAccess(void);
+
+/* WakeUp pins configuration functions ****************************************/
+void              HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
+void              HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes configuration functions ************************************/
+void              HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void              HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void              HAL_PWR_EnterSTANDBYMode(void);
+void              HAL_PWR_EnableSleepOnExit(void);
+void              HAL_PWR_DisableSleepOnExit(void);
+void              HAL_PWR_EnableSEVOnPend(void);
+void              HAL_PWR_DisableSEVOnPend(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32G0xx_HAL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h

@@ -0,0 +1,643 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_pwr_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_PWR_EX_H
+#define STM32G0xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal_def.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWREx PWREx
+  * @brief PWR Extended HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
+  * @{
+  */
+
+#if defined(PWR_PVM_SUPPORT)
+/**
+  * @brief  PWR PVM configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PVMType;   /*!< PVMType: Specifies which voltage is monitored and against which threshold.
+                           This parameter can be a value of @ref PWREx_PVM_Type.
+                           @arg @ref PWR_PVM_USB Peripheral Voltage Monitoring USB enable */
+
+  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref PWREx_PVM_Mode. */
+}PWR_PVMTypeDef;
+#endif
+
+#if defined(PWR_PVD_SUPPORT)
+/**
+  * @brief  PWR PVD configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PVDLevel;    /*!< PVDLevel: Specifies the PVD detection level.
+                              This parameter can be a value or a combination of
+                              @ref PWR_PVD_detection_level. */
+
+  uint32_t Mode;        /*!< Mode: Specifies the operating mode for the selected pins.
+                              This parameter can be a value of @ref PWR_PVD_Mode. */
+}PWR_PVDTypeDef;
+#endif
+
+/**
+  * @}
+  */
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Constants  PWR Extended Exported Constants
+  * @{
+  */
+#if defined(PWR_PVD_SUPPORT)
+/** @defgroup PWR_PVD_detection_level  Programmable Voltage Detection levels
+  * @note   see datasheet for selection voltage value
+  * @{
+  */
+#define PWR_PVDLEVEL_RISING_0               (0x00000000u)                                           /*!< PVD threshold level 0 for rising detection */
+#define PWR_PVDLEVEL_RISING_1               (PWR_CR2_PVDRT_0)                                       /*!< PVD threshold level 1 for rising detection */
+#define PWR_PVDLEVEL_RISING_2               (PWR_CR2_PVDRT_1)                                       /*!< PVD threshold level 2 for rising detection */
+#define PWR_PVDLEVEL_RISING_3               (PWR_CR2_PVDRT_0 | PWR_CR2_PVDRT_1)                     /*!< PVD threshold level 3 for rising detection */
+#define PWR_PVDLEVEL_RISING_4               (PWR_CR2_PVDRT_2)                                       /*!< PVD threshold level 4 for rising detection */
+#define PWR_PVDLEVEL_RISING_5               (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_0)                     /*!< PVD threshold level 5 for rising detection */
+#define PWR_PVDLEVEL_RISING_6               (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1)                     /*!< PVD threshold level 6 for rising detection */
+#define PWR_PVDLEVEL_FALLING_0              (0x00000000u)                                           /*!< PVD threshold level 0 for falling detection */
+#define PWR_PVDLEVEL_FALLING_1              (PWR_CR2_PVDFT_0)                                       /*!< PVD threshold level 1 for falling detection */
+#define PWR_PVDLEVEL_FALLING_2              (PWR_CR2_PVDFT_1)                                       /*!< PVD threshold level 2 for falling detection */
+#define PWR_PVDLEVEL_FALLING_3              (PWR_CR2_PVDFT_0 | PWR_CR2_PVDFT_1)                     /*!< PVD threshold level 3 for falling detection */
+#define PWR_PVDLEVEL_FALLING_4              (PWR_CR2_PVDFT_2)                                       /*!< PVD threshold level 4 for falling detection */
+#define PWR_PVDLEVEL_FALLING_5              (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_0)                     /*!< PVD threshold level 5 for falling detection */
+#define PWR_PVDLEVEL_FALLING_6              (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_1)                     /*!< PVD threshold level 6 for falling detection */
+#define PWR_PVDLEVEL_0                      (PWR_PVDLEVEL_RISING_0 | PWR_PVDLEVEL_FALLING_0)        /*!< same PVD threshold level 0 on rising & falling */
+#define PWR_PVDLEVEL_1                      (PWR_PVDLEVEL_RISING_1 | PWR_PVDLEVEL_FALLING_1)        /*!< same PVD threshold level 1 on rising & falling */
+#define PWR_PVDLEVEL_2                      (PWR_PVDLEVEL_RISING_2 | PWR_PVDLEVEL_FALLING_2)        /*!< same PVD threshold level 2 on rising & falling */
+#define PWR_PVDLEVEL_3                      (PWR_PVDLEVEL_RISING_3 | PWR_PVDLEVEL_FALLING_3)        /*!< same PVD threshold level 3 on rising & falling */
+#define PWR_PVDLEVEL_4                      (PWR_PVDLEVEL_RISING_4 | PWR_PVDLEVEL_FALLING_4)        /*!< same PVD threshold level 4 on rising & falling */
+#define PWR_PVDLEVEL_5                      (PWR_PVDLEVEL_RISING_5 | PWR_PVDLEVEL_FALLING_5)        /*!< same PVD threshold level 5 on rising & falling */
+#define PWR_PVDLEVEL_6                      (PWR_PVDLEVEL_RISING_6 | PWR_PVDLEVEL_FALLING_6)        /*!< same PVD threshold level 6 on rising & falling */
+#define PWR_PVDLEVEL_7                      (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0)   /*!< External input analog voltage (compared internally to VREFINT) */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PVD_Mode  PWR PVD interrupt and event mode
+  * @{
+  */
+#define PWR_PVD_MODE_NORMAL                 (0x00000000u)  /*!< basic mode is used */
+#define PWR_PVD_MODE_IT_RISING              (0x00010001u)  /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING             (0x00010002u)  /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING      (0x00010003u)  /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING           (0x00020001u)  /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING          (0x00020002u)  /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING   (0x00020003u)  /*!< Event Mode with Rising/Falling edge trigger detection */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PVD_EXTI_LINE  PWR PVD external interrupt line
+  * @{
+  */
+#define PWR_EXTI_LINE_PVD                   (EXTI_IMR1_IM16)  /*!< External interrupt line 16 connected to PVD */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PVD_EVENT_LINE  PWR PVD event line
+  * @{
+  */
+#define PWR_EVENT_LINE_PVD                  (EXTI_EMR1_EM16)  /*!< Event line 16 connected to PVD */
+/**
+  * @}
+  */
+#endif
+
+#if defined(PWR_PVM_SUPPORT)
+/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
+  * @{
+  */
+#define PWR_PVM_USB                  PWR_CR2_PVMEN_USB  /*!< Peripheral Voltage Monitoring enable for USB peripheral: Enable to keep the USB peripheral voltage monitoring under control (power domain Vddio2) */
+/**
+  * @}
+  */
+/** @defgroup PWREx_PVM_Mode  PWR PVM interrupt and event mode
+  * @{
+  */
+#define PWR_PVM_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< basic mode is used */
+#define PWR_PVM_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVM_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVM_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVM_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVM_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVM_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */
+/**
+  * @}
+  */
+/** @defgroup PWR_PVM_EXTI_LINE  PWR PVM external interrupt line
+  * @{
+  */
+#define PWR_EXTI_LINE_PVM                   (EXTI_IMR2_IM34)  /*!< External interrupt line 34 connected to PVM */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PVM_EVENT_LINE  PWR PVM event line
+  * @{
+  */
+#define PWR_EVENT_LINE_PVM                  (EXTI_EMR2_EM34)  /*!< Event line 34 connected to PVM */
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup PWREx_VBAT_Battery_Charging_Selection  PWR battery charging resistor selection
+  * @{
+  */
+#define PWR_BATTERY_CHARGING_RESISTOR_5     (0x00000000u)   /*!< VBAT charging through a 5 kOhms resistor   */
+#define PWR_BATTERY_CHARGING_RESISTOR_1_5   PWR_CR4_VBRS    /*!< VBAT charging through a 1.5 kOhms resistor */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_GPIO_Bit_Number  GPIO bit position
+  * @brief    for I/O pull up/down setting in standby/shutdown mode
+  * @{
+  */
+#define PWR_GPIO_BIT_0                      PWR_PUCRB_PU0   /*!< GPIO port I/O pin 0  */
+#define PWR_GPIO_BIT_1                      PWR_PUCRB_PU1   /*!< GPIO port I/O pin 1  */
+#define PWR_GPIO_BIT_2                      PWR_PUCRB_PU2   /*!< GPIO port I/O pin 2  */
+#define PWR_GPIO_BIT_3                      PWR_PUCRB_PU3   /*!< GPIO port I/O pin 3  */
+#define PWR_GPIO_BIT_4                      PWR_PUCRB_PU4   /*!< GPIO port I/O pin 4  */
+#define PWR_GPIO_BIT_5                      PWR_PUCRB_PU5   /*!< GPIO port I/O pin 5  */
+#define PWR_GPIO_BIT_6                      PWR_PUCRB_PU6   /*!< GPIO port I/O pin 6  */
+#define PWR_GPIO_BIT_7                      PWR_PUCRB_PU7   /*!< GPIO port I/O pin 7  */
+#define PWR_GPIO_BIT_8                      PWR_PUCRB_PU8   /*!< GPIO port I/O pin 8  */
+#define PWR_GPIO_BIT_9                      PWR_PUCRB_PU9   /*!< GPIO port I/O pin 9  */
+#define PWR_GPIO_BIT_10                     PWR_PUCRB_PU10  /*!< GPIO port I/O pin 10 */
+#define PWR_GPIO_BIT_11                     PWR_PUCRB_PU11  /*!< GPIO port I/O pin 11 */
+#define PWR_GPIO_BIT_12                     PWR_PUCRB_PU12  /*!< GPIO port I/O pin 12 */
+#define PWR_GPIO_BIT_13                     PWR_PUCRB_PU13  /*!< GPIO port I/O pin 13 */
+#define PWR_GPIO_BIT_14                     PWR_PUCRB_PU14  /*!< GPIO port I/O pin 14 */
+#define PWR_GPIO_BIT_15                     PWR_PUCRB_PU15  /*!< GPIO port I/O pin 15 */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_GPIO_Port  GPIO Port
+  * @{
+  */
+#define PWR_GPIO_A                          (0x00000000u)  /*!< GPIO port A */
+#define PWR_GPIO_B                          (0x00000001u)  /*!< GPIO port B */
+#define PWR_GPIO_C                          (0x00000002u)  /*!< GPIO port C */
+#define PWR_GPIO_D                          (0x00000003u)  /*!< GPIO port D */
+#if defined (GPIOE)
+#define PWR_GPIO_E                          (0x00000004u)  /*!< GPIO port E */
+#endif
+#define PWR_GPIO_F                          (0x00000005u)  /*!< GPIO port F */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Flash_PowerDown  Flash Power Down modes
+  * @{
+  */
+#define PWR_FLASHPD_LPRUN                   PWR_CR1_FPD_LPRUN  /*!< Enable Flash power down in low power run mode */
+#define PWR_FLASHPD_LPSLEEP                 PWR_CR1_FPD_LPSLP  /*!< Enable Flash power down in low power sleep mode */
+#define PWR_FLASHPD_STOP                    PWR_CR1_FPD_STOP   /*!< Enable Flash power down in stop mode */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_Regulator_Voltage_Scale  PWR Regulator voltage scale
+  * @{
+  */
+#define PWR_REGULATOR_VOLTAGE_SCALE1        PWR_CR1_VOS_0  /*!< Voltage scaling range 1 */
+#define PWR_REGULATOR_VOLTAGE_SCALE2        PWR_CR1_VOS_1  /*!< Voltage scaling range 2 */
+/**
+  * @}
+  */
+
+/** @addtogroup PWR_Flag  PWR Status Flags
+  * @brief  Elements values convention: 0000 00XX 000Y YYYYb
+  *           - Y YYYY  : Flag position in the XX register (5 bits)
+  *           - XX  : Status register (2 bits)
+  *                 - 01: SR1 register
+  *                 - 10: SR2 register
+  *         The only exception is PWR_FLAG_WU, encompassing all
+  *         wake-up flags and set to PWR_SR1_WUF.
+  * @{
+  */
+#if defined(PWR_PVM_SUPPORT)
+#define PWR_FLAG_PVMOUSB                    (0x00020000u | PWR_SR2_PVMO_USB)   /*!< USB Peripheral Voltage Monitoring output */
+#endif
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @addtogroup PWREx_Exported_Macros  PWR Extended Exported Macros
+  * @{
+  */
+#if defined(PWR_PVD_SUPPORT)
+/**
+  * @brief Enable the PVD Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT()            SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT()           CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()         SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()        CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief  Enable the PVD Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                   \
+    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0U)
+
+/**
+  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                    \
+    __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0U)
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT()        SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Check whether or not the PVD EXTI interrupt Rising flag is set.
+  * @retval EXTI PVD Line Status.
+  */
+#define __HAL_PWR_PVD_EXTI_GET_RISING_FLAG()      (EXTI->RPR1 & PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Check whether or not the PVD EXTI interrupt Falling flag is set.
+  * @retval EXTI PVD Line Status.
+  */
+#define __HAL_PWR_PVD_EXTI_GET_FALLING_FLAG()     (EXTI->FPR1 & PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Clear the PVD EXTI interrupt Rising flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG()    WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Clear the PVD EXTI interrupt Falling flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG()   WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD)
+#endif
+
+#if defined(PWR_PVM_SUPPORT)
+/**
+  * @brief Enable the PVM Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM_EXTI_ENABLE_IT()            SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM)
+
+/**
+  * @brief Disable the PVM Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM_EXTI_DISABLE_IT()           CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM)
+
+/**
+  * @brief Enable the PVM Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM_EXTI_ENABLE_EVENT()         SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM)
+
+/**
+  * @brief Disable the PVM Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM_EXTI_DISABLE_EVENT()        CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM)
+
+/**
+  * @brief Enable the PVM Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM)
+
+/**
+  * @brief Disable the PVM Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM)
+
+/**
+  * @brief Enable the PVM Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM)
+
+/**
+  * @brief Disable the PVM Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM)
+
+/**
+  * @brief  Enable the PVM Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                   \
+    __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0U)
+
+/**
+  * @brief Disable the PVM Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                    \
+    __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0U)
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM_EXTI_GENERATE_SWIT()        SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM)
+
+/**
+  * @brief Check whether or not the PVM EXTI interrupt Rising flag is set.
+  * @retval EXTI PVM Line Status.
+  */
+#define __HAL_PWR_PVM_EXTI_GET_RISING_FLAG()      (EXTI->RPR2 & PWR_EXTI_LINE_PVM)
+
+/**
+  * @brief Check whether or not the PVM EXTI interrupt Falling flag is set.
+  * @retval EXTI PVM Line Status.
+  */
+#define __HAL_PWR_PVM_EXTI_GET_FALLING_FLAG()     (EXTI->FPR2 & PWR_EXTI_LINE_PVM)
+
+/**
+  * @brief Clear the PVM EXTI interrupt Rising flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVM_EXTI_CLEAR_RISING_FLAG()    WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM)
+
+/**
+  * @brief Clear the PVM EXTI interrupt Falling flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG()   WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM)
+#endif
+/**
+  * @}
+  */
+
+/* Private define ------------------------------------------------------------*/
+/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
+  * @{
+  */
+
+/** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
+  * @{
+  */
+#define PVM_MODE_IT               ((uint32_t)0x00010000)  /*!< Mask for interruption yielded by PVM threshold crossing */
+#define PVM_MODE_EVT              ((uint32_t)0x00020000)  /*!< Mask for event yielded by PVM threshold crossing        */
+#define PVM_RISING_EDGE           ((uint32_t)0x00000001)  /*!< Mask for rising edge set as PVM trigger                 */
+#define PVM_FALLING_EDGE          ((uint32_t)0x00000002)  /*!< Mask for falling edge set as PVM trigger                */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup  PWREx_Private_Macros   PWR Extended Private Macros
+  * @{
+  */
+
+#define IS_PWR_BATTERY_RESISTOR_SELECT(__RESISTOR__) (((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_5) || \
+                                                      ((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
+
+#define IS_PWR_GPIO_BIT_NUMBER(__BIT_NUMBER__)  ((((__BIT_NUMBER__) & 0x0000FFFFu) != 0x00u) && \
+                                                 (((__BIT_NUMBER__) & 0xFFFF0000u) == 0x00u))
+#if defined (GPIOE)
+#define IS_PWR_GPIO(__GPIO__)               (((__GPIO__) == PWR_GPIO_A) || \
+                                             ((__GPIO__) == PWR_GPIO_B) || \
+                                             ((__GPIO__) == PWR_GPIO_C) || \
+                                             ((__GPIO__) == PWR_GPIO_D) || \
+                                             ((__GPIO__) == PWR_GPIO_E) || \
+                                             ((__GPIO__) == PWR_GPIO_F))
+#else
+#define IS_PWR_GPIO(__GPIO__)               (((__GPIO__) == PWR_GPIO_A) || \
+                                             ((__GPIO__) == PWR_GPIO_B) || \
+                                             ((__GPIO__) == PWR_GPIO_C) || \
+                                             ((__GPIO__) == PWR_GPIO_D) || \
+                                             ((__GPIO__) == PWR_GPIO_F))
+#endif
+
+#define IS_PWR_FLASH_POWERDOWN(__MODE__)    ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP | PWR_FLASHPD_STOP)) != 0x00u) && \
+                                             (((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP | PWR_FLASHPD_STOP)) == 0x00u))
+
+#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
+
+#if defined(PWR_PVD_SUPPORT)
+#define IS_PWR_PVD_LEVEL(LEVEL)                   (((LEVEL) & ~(PWR_CR2_PVDRT | PWR_CR2_PVDFT)) == 0x00000000u)
+
+#define IS_PWR_PVD_MODE(MODE)                     (((MODE) == PWR_PVD_MODE_NORMAL)              || \
+                                                   ((MODE) == PWR_PVD_MODE_IT_RISING)           || \
+                                                   ((MODE) == PWR_PVD_MODE_IT_FALLING)          || \
+                                                   ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)   || \
+                                                   ((MODE) == PWR_PVD_MODE_EVENT_RISING)        || \
+                                                   ((MODE) == PWR_PVD_MODE_EVENT_FALLING)       || \
+                                                   ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))
+#endif
+
+#if defined(PWR_PVM_SUPPORT)
+#define IS_PWR_PVM_TYPE(TYPE) ((TYPE) == PWR_PVM_USB)
+
+#define IS_PWR_PVM_MODE(MODE)  (((MODE) == PWR_PVM_MODE_NORMAL)              ||\
+                                ((MODE) == PWR_PVM_MODE_IT_RISING)           ||\
+                                ((MODE) == PWR_PVM_MODE_IT_FALLING)          ||\
+                                ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING)   ||\
+                                ((MODE) == PWR_PVM_MODE_EVENT_RISING)        ||\
+                                ((MODE) == PWR_PVM_MODE_EVENT_FALLING)       ||\
+                                ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
+#endif
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Functions  PWR Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group1  Extended Peripheral Control functions
+  * @{
+  */
+
+/* Peripheral Control functions  **********************************************/
+void              HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
+void              HAL_PWREx_DisableBatteryCharging(void);
+#if defined(PWR_CR3_ENB_ULP)
+void              HAL_PWREx_EnablePORMonitorSampling(void);
+void              HAL_PWREx_DisablePORMonitorSampling(void);
+#endif
+void              HAL_PWREx_EnableInternalWakeUpLine(void);
+void              HAL_PWREx_DisableInternalWakeUpLine(void);
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
+void              HAL_PWREx_EnablePullUpPullDownConfig(void);
+void              HAL_PWREx_DisablePullUpPullDownConfig(void);
+#if defined(PWR_CR3_RRS)
+void              HAL_PWREx_EnableSRAMRetention(void);
+void              HAL_PWREx_DisableSRAMRetention(void);
+#endif
+void              HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode);
+void              HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode);
+uint32_t          HAL_PWREx_GetVoltageRange(void);
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
+#if defined(PWR_PVD_SUPPORT)
+/* Power voltage detection configuration functions ****************************/
+HAL_StatusTypeDef HAL_PWREx_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+void              HAL_PWREx_EnablePVD(void);
+void              HAL_PWREx_DisablePVD(void);
+#endif
+#if defined(PWR_PVM_SUPPORT)
+/* Power voltage monitoring configuration functions ***************************/
+void HAL_PWREx_EnableVddIO2(void);
+void HAL_PWREx_DisableVddIO2(void);
+void HAL_PWREx_EnableVddUSB(void);
+void HAL_PWREx_DisableVddUSB(void);
+void HAL_PWREx_EnablePVMUSB(void);
+void HAL_PWREx_DisablePVMUSB(void);
+HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
+#endif
+
+/* Low Power modes configuration functions ************************************/
+void              HAL_PWREx_EnableLowPowerRunMode(void);
+HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
+#if defined(PWR_SHDW_SUPPORT)
+void              HAL_PWREx_EnterSHUTDOWNMode(void);
+#endif
+
+#if defined(PWR_PVD_SUPPORT) && defined(PWR_PVM_SUPPORT)
+void              HAL_PWREx_PVD_PVM_IRQHandler(void);
+void              HAL_PWREx_PVD_PVM_Rising_Callback(void);
+void              HAL_PWREx_PVD_PVM_Falling_Callback(void);
+#elif defined(PWR_PVD_SUPPORT)
+void              HAL_PWREx_PVD_IRQHandler(void);
+void              HAL_PWREx_PVD_Rising_Callback(void);
+void              HAL_PWREx_PVD_Falling_Callback(void);
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32G0xx_HAL_PWR_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h

@@ -0,0 +1,496 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_tim_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_TIM_EX_H
+#define STM32G0xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal_def.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIMEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
+  * @{
+  */
+
+/**
+  * @brief  TIM Hall sensor Configuration Structure definition
+  */
+
+typedef struct
+{
+  uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint32_t IC1Filter;           /*!< Specifies the input capture filter.
+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+
+/**
+  * @brief  TIM Break/Break2 input configuration
+  */
+typedef struct
+{
+  uint32_t Source;         /*!< Specifies the source of the timer break input.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source */
+  uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
+  uint32_t Polarity;       /*!< Specifies the break input source polarity.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */
+}
+TIMEx_BreakInputConfigTypeDef;
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup TIMEx_Remap TIM Extended Remapping
+  * @{
+  */
+#define TIM_TIM1_ETR_GPIO           0x00000000U                                 /* !< TIM1_ETR is connected to GPIO */
+#if defined(COMP1) && defined(COMP2)
+#define TIM_TIM1_ETR_COMP1          TIM1_AF1_ETRSEL_0                           /* !< TIM1_ETR is connected to COMP1 output */
+#define TIM_TIM1_ETR_COMP2          TIM1_AF1_ETRSEL_1                           /* !< TIM1_ETR is connected to COMP2 output */
+#endif /* COMP1 && COMP2 */
+#define TIM_TIM1_ETR_ADC1_AWD1      (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)     /* !< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ETR_ADC1_AWD2      TIM1_AF1_ETRSEL_2                           /* !< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ETR_ADC1_AWD3      (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)     /* !< TIM1_ETR is connected to ADC1 AWD3 */
+#if defined(COMP3)
+#define TIM_TIM1_ETR_COMP3          (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)     /* !< TIM1_ETR is connected to COMP3 output */
+#endif
+#if defined(TIM2)
+#define TIM_TIM2_ETR_GPIO           0x00000000U                                 /* !< TIM2_ETR is connected to GPIO      */
+#define TIM_TIM2_ETR_COMP1          TIM2_AF1_ETRSEL_0                           /* !< TIM2_ETR is connected to COMP1 output */
+#define TIM_TIM2_ETR_COMP2          TIM2_AF1_ETRSEL_1                           /* !< TIM2_ETR is connected to COMP2 output */
+#define TIM_TIM2_ETR_LSE            (TIM2_AF1_ETRSEL_1 | TIM2_AF1_ETRSEL_0)     /* !< TIM2_ETR is connected to LSE */
+#if defined(COMP3)
+#define TIM_TIM2_ETR_MCO            TIM2_AF1_ETRSEL_2                           /* !< TIM2_ETR is connected to MCO */
+#define TIM_TIM2_ETR_MCO2           (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)     /* !< TIM2_ETR is connected to MCO2 */
+#define TIM_TIM2_ETR_COMP3          (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)     /* !< TIM2_ETR is connected to COMP3 output */
+#endif
+#endif /*  TIM2 */
+#if defined(TIM3)
+#define TIM_TIM3_ETR_GPIO           0x00000000U                                 /* !< TIM3_ETR is connected to GPIO */
+#if defined(COMP1) && defined(COMP2)
+#define TIM_TIM3_ETR_COMP1          TIM3_AF1_ETRSEL_0                           /* !< TIM3_ETR is connected to COMP1 output */
+#define TIM_TIM3_ETR_COMP2          TIM3_AF1_ETRSEL_1                           /* !< TIM3_ETR is connected to COMP2 output */
+#endif /* COMP1 && COMP2 */
+#if defined(COMP3)
+#define TIM_TIM3_ETR_COMP3          (TIM3_AF1_ETRSEL_1 | TIM3_AF1_ETRSEL_0)     /* !< TIM3_ETR is connected to COMP3 output */
+#endif /* COMP3 */
+#endif /* TIM3 */
+#if defined(TIM4)
+#define TIM_TIM4_ETR_GPIO           0x00000000U                                 /* !< TIM4_ETR is connected to GPIO */
+#if defined(COMP1) && defined(COMP2)
+#define TIM_TIM4_ETR_COMP1          TIM4_AF1_ETRSEL_0                           /* !< TIM4_ETR is connected to COMP1 output */
+#define TIM_TIM4_ETR_COMP2          TIM4_AF1_ETRSEL_1                           /* !< TIM4_ETR is connected to COMP2 output */
+#endif /* COMP1 && COMP2 */
+#if defined(COMP3)
+#define TIM_TIM4_ETR_COMP3          (TIM4_AF1_ETRSEL_1 | TIM4_AF1_ETRSEL_0)     /* !< TIM4_ETR is connected to COMP3 output */
+#endif /* COMP3 */
+#endif /* TIM4 */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input TIM Extended Break input
+  * @{
+  */
+#define TIM_BREAKINPUT_BRK     0x00000001U                                      /* !< Timer break input  */
+#define TIM_BREAKINPUT_BRK2    0x00000002U                                      /* !< Timer break2 input */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_BKIN     0x00000001U                               /* !< An external source (GPIO) is connected to the BKIN pin  */
+#if defined(COMP1) && defined(COMP2)
+#define TIM_BREAKINPUTSOURCE_COMP1    0x00000002U                               /* !< The COMP1 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP2    0x00000004U                               /* !< The COMP2 output is connected to the break input */
+#endif /* COMP1 && COMP2 */
+#if defined(COMP3)
+#define TIM_BREAKINPUTSOURCE_COMP3    0x00000008U                               /* !< The COMP3 output is connected to the break input */
+#endif /* COMP3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_DISABLE     0x00000000U                            /* !< Break input source is disabled */
+#define TIM_BREAKINPUTSOURCE_ENABLE      0x00000001U                            /* !< Break input source is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW     0x00000001U                       /* !< Break input source is active low */
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    0x00000000U                       /* !< Break input source is active_high */
+/**
+  * @}
+  */
+
+/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection
+  * @{
+  */
+#define TIM_TIM1_TI1_GPIO                     0x00000000U                       /* !< TIM1_TI1 is connected to GPIO */
+#if defined(COMP1)
+#define TIM_TIM1_TI1_COMP1                    0x00000001U                       /* !< TIM1_TI1 is connected to COMP1 OUT */
+#endif /* COMP1 */
+
+#define TIM_TIM1_TI2_GPIO                     0x00000000U                       /* !< TIM1_TI2 is connected to GPIO */
+#if defined(COMP2)
+#define TIM_TIM1_TI2_COMP2                    0x00000100U                       /* !< TIM1_TI2 is connected to COMP2 OUT */
+#endif /* COMP2 */
+
+#define TIM_TIM1_TI3_GPIO                     0x00000000U                       /* !< TIM1_TI3 is connected to GPIO */
+#if defined(COMP3)
+#define TIM_TIM1_TI3_COMP3                    0x00010000U                       /* !< TIM1_TI3 is connected to COMP3 OUT */
+#endif /* COMP3 */
+
+#if defined(TIM2)
+#define TIM_TIM2_TI1_GPIO                     0x00000000U                       /* !< TIM2_TI1 is connected to GPIO */
+#define TIM_TIM2_TI1_COMP1                    0x00000001U                       /* !< TIM2_TI1 is connected to COMP1 OUT */
+
+#define TIM_TIM2_TI2_GPIO                     0x00000000U                       /* !< TIM2_TI2 is connected to GPIO */
+#define TIM_TIM2_TI2_COMP2                    0x00000100U                       /* !< TIM2_TI2 is connected to COMP2 OUT */
+
+#define TIM_TIM2_TI3_GPIO                     0x00000000U                       /* !< TIM2_TI3 is connected to GPIO */
+#if defined(COMP3)
+#define TIM_TIM2_TI3_COMP3                    0x00010000U                       /* !< TIM2_TI3 is connected to COMP3 OUT */
+#endif /* COMP3 */
+#endif /* TIM2 */
+
+#define TIM_TIM3_TI1_GPIO                     0x00000000U                       /* !< TIM3_TI1 is connected to GPIO */
+#if defined(COMP1)
+#define TIM_TIM3_TI1_COMP1                    0x00000001U                       /* !< TIM3_TI1 is connected to COMP1 OUT */
+#endif /* COMP1 */
+
+#define TIM_TIM3_TI2_GPIO                     0x00000000U                       /* !< TIM3_TI2 is connected to GPIO */
+#if defined(COMP2)
+#define TIM_TIM3_TI2_COMP2                    0x00000100U                       /* !< TIM3_TI2 is connected to COMP2 OUT */
+#endif /* COMP2 */
+
+#define TIM_TIM3_TI3_GPIO                     0x00000000U                       /* !< TIM3_TI3 is connected to GPIO */
+#if defined(COMP3)
+#define TIM_TIM3_TI3_COMP3                    0x00010000U                       /* !< TIM3_TI3 is connected to COMP3 OUT */
+#endif /* COMP3 */
+
+#if defined(TIM4)
+#define TIM_TIM4_TI1_GPIO                     0x00000000U                       /* !< TIM4_TI1 is connected to GPIO */
+#if defined(COMP1)
+#define TIM_TIM4_TI1_COMP1                    0x00000001U                       /* !< TIM4_TI1 is connected to COMP1 OUT */
+#endif /* COMP1 */
+
+#define TIM_TIM4_TI2_GPIO                     0x00000000U                       /* !< TIM4_TI2 is connected to GPIO */
+#if defined(COMP2)
+#define TIM_TIM4_TI2_COMP2                    0x00000100U                       /* !< TIM4_TI2 is connected to COMP2 OUT */
+#endif /* COMP2 */
+
+#define TIM_TIM4_TI3_GPIO                     0x00000000U                       /* !< TIM4_TI3 is connected to GPIO */
+#if defined(COMP3)
+#define TIM_TIM4_TI3_COMP3                    0x00010000U                       /* !< TIM4_TI3 is connected to COMP3 OUT */
+#endif /* COMP3 */
+#endif /* TIM4 */
+
+#define TIM_TIM14_TI1_GPIO                    0x00000000U                       /* !< TIM14_TI1 is connected to GPIO */
+#define TIM_TIM14_TI1_RTC                     0x00000001U                       /* !< TIM14_TI1 is connected to RTC clock */
+#define TIM_TIM14_TI1_HSE_32                  0x00000002U                       /* !< TIM14_TI1 is connected to HSE div 32 */
+#define TIM_TIM14_TI1_MCO                     0x00000003U                       /* !< TIM14_TI1 is connected to MCO */
+#if defined(RCC_MCO2_SUPPORT)
+#define TIM_TIM14_TI1_MCO2                    0x00000004U                       /* !< TIM14_TI1 is connected to MCO2 */
+#endif
+
+#if defined(TIM15)
+#define TIM_TIM15_TI1_GPIO                    0x00000000U                       /* !< TIM15_TI1 is connected to GPIO */
+#define TIM_TIM15_TI1_TIM2_CH1                0x00000001U                       /* !< TIM15_TI1 is connected to TIM2 CH1 */
+#define TIM_TIM15_TI1_TIM3_CH1                0x00000002U                       /* !< TIM15_TI1 is connected to TIM3 CH1 */
+
+#define TIM_TIM15_TI2_GPIO                    0x00000000U                       /* !< TIM15_TI2 is connected to GPIO */
+#define TIM_TIM15_TI2_TIM2_CH2                0x00000100U                       /* !< TIM15_TI2 is connected to TIM2 CH2 */
+#define TIM_TIM15_TI2_TIM3_CH2                0x00000200U                       /* !< TIM15_TI2 is connected to TIM3 CH2 */
+#endif /* TIM15 */
+
+#define TIM_TIM16_TI1_GPIO                    0x00000000U                       /* !< TIM16_TI1 is connected to GPIO */
+#define TIM_TIM16_TI1_LSI                     0x00000001U                       /* !< TIM16_TI1 is connected to LSI */
+#define TIM_TIM16_TI1_LSE                     0x00000002U                       /* !< TIM16_TI1 is connected to LSE */
+#define TIM_TIM16_TI1_RTC_WAKEUP              0x00000003U                       /* !< TIM16_TI1 is connected to TRC wakeup interrupt */
+#if defined(RCC_MCO2_SUPPORT)
+#define TIM_TIM16_TI1_MCO2                    0x00000004U                       /* !< TIM16_TI1 is connected to MCO2 */
+#endif
+
+#define TIM_TIM17_TI1_GPIO                    0x00000000U                       /* !< TIM17_TI1 is connected to GPIO */
+#if defined(RCC_HSI48_SUPPORT)
+#define TIM_TIM17_TI1_HSI48                   0x00000001U                       /* !< TIM17_TI1 is connected to HSI48/256 */
+#endif
+#define TIM_TIM17_TI1_HSE_32                  0x00000002U                       /* !< TIM17_TI1 is connected to HSE div 32 */
+#define TIM_TIM17_TI1_MCO                     0x00000003U                       /* !< TIM17_TI1 is connected to MCO */
+#if defined(RCC_MCO2_SUPPORT)
+#define TIM_TIM17_TI1_MCO2                    0x00000004U                       /* !< TIM17_TI1 is connected to MCO2 */
+#endif
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+  * @{
+  */
+#define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U))
+
+#define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
+                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
+
+#if defined(COMP1) && defined(COMP2) && defined(COMP3)
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3))
+#elif defined(COMP1) && defined(COMP2)
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))
+#else
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  ((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)
+#endif /* COMP1 && COMP2 && COMP3 */
+
+#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
+                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
+
+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
+                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
+
+#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U))
+
+/**
+  * @}
+  */
+/* End of private macro ------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  *  @brief    Timer Hall Sensor functions
+  * @{
+  */
+/*  Timer Hall Sensor functions  **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  * @{
+  */
+/*  Timer Complementary Output Compare functions  *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  *  @brief    Timer Complementary PWM functions
+  * @{
+  */
+/*  Timer Complementary PWM functions  ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  *  @brief    Timer Complementary One Pulse functions
+  * @{
+  */
+/*  Timer Complementary One Pulse functions  **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  * @{
+  */
+/* Extended Control functions  ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
+                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);
+
+HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  * @{
+  */
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  * @{
+  */
+/* Extended Peripheral State functions  ***************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim,  uint32_t ChannelN);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
+  * @{
+  */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32G0xx_HAL_TIM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h

@@ -0,0 +1,770 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_uart_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of UART HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_UART_EX_H
+#define STM32G0xx_HAL_UART_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal_def.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup UARTEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  UART wake up from stop mode parameters
+  */
+typedef struct
+{
+  uint32_t WakeUpEvent;        /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
+                                    This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
+                                    If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
+                                    be filled up. */
+
+  uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.
+                                    This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */
+
+  uint8_t Address;             /*!< UART/USART node address (7-bit long max). */
+} UART_WakeUpTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
+  * @{
+  */
+
+/** @defgroup UARTEx_Word_Length UARTEx Word Length
+  * @{
+  */
+#define UART_WORDLENGTH_7B          USART_CR1_M1   /*!< 7-bit long UART frame */
+#define UART_WORDLENGTH_8B          0x00000000U    /*!< 8-bit long UART frame */
+#define UART_WORDLENGTH_9B          USART_CR1_M0   /*!< 9-bit long UART frame */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
+  * @{
+  */
+#define UART_ADDRESS_DETECT_4B      0x00000000U      /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_7B      USART_CR2_ADDM7  /*!< 7-bit long wake-up address */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
+  * @brief    UART FIFO mode
+  * @{
+  */
+#define UART_FIFOMODE_DISABLE       0x00000000U       /*!< FIFO mode disable */
+#define UART_FIFOMODE_ENABLE        USART_CR1_FIFOEN  /*!< FIFO mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
+  * @brief    UART TXFIFO threshold level
+  * @{
+  */
+#define UART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TXFIFO reaches 1/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TXFIFO reaches 1/2 of its depth */
+#define UART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TXFIFO reaches 7/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty            */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
+  * @brief    UART RXFIFO threshold level
+  * @{
+  */
+#define UART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RXFIFO FIFO reaches 1/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RXFIFO FIFO reaches 1/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RXFIFO FIFO reaches 1/2 of its depth */
+#define UART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RXFIFO FIFO reaches 7/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full             */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UARTEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+                                   uint32_t DeassertionTime);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group2
+  * @{
+  */
+
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
+
+void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
+void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group3
+  * @{
+  */
+
+/* Peripheral Control functions  **********************************************/
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
+  * @{
+  */
+
+#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
+/** @brief  Report the UART clock source.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __CLOCKSOURCE__ output variable.
+  * @retval UART clocking source, written in __CLOCKSOURCE__.
+  */
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+      {                                                       \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART4)                 \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART5)                 \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART6)                 \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART2)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART2_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART2CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART2CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART2CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART2CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#elif defined(STM32G0B0xx)
+/** @brief  Report the UART clock source.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __CLOCKSOURCE__ output variable.
+  * @retval UART clocking source, written in __CLOCKSOURCE__.
+  */
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+      {                                                       \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART4)                 \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART5)                 \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART6)                 \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#elif defined(STM32G081xx) || defined(STM32G071xx)
+/** @brief  Report the UART clock source.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __CLOCKSOURCE__ output variable.
+  * @retval UART clocking source, written in __CLOCKSOURCE__.
+  */
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART4)                 \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#elif defined(STM32G070xx)
+/** @brief  Report the UART clock source.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __CLOCKSOURCE__ output variable.
+  * @retval UART clocking source, written in __CLOCKSOURCE__.
+  */
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART4)                 \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#elif defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G051xx) || defined(STM32G061xx)
+/** @brief  Report the UART clock source.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __CLOCKSOURCE__ output variable.
+  * @retval UART clocking source, written in __CLOCKSOURCE__.
+  */
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#elif defined(STM32G030xx) || defined(STM32G050xx)
+/** @brief  Report the UART clock source.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __CLOCKSOURCE__ output variable.
+  * @retval UART clocking source, written in __CLOCKSOURCE__.
+  */
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;             \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#endif
+
+/** @brief  Report the UART mask to apply to retrieve the received data
+  *         according to the word length and to the parity bits activation.
+  * @note   If PCE = 1, the parity bit is not included in the data extracted
+  *         by the reception API().
+  *         This masking operation is not carried out in the case of
+  *         DMA transfers.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
+  */
+#define UART_MASK_COMPUTATION(__HANDLE__)                             \
+  do {                                                                \
+    if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)          \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x01FFU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x00FFU ;                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x00FFU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x007FU ;                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x007FU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x003FU ;                                \
+      }                                                               \
+    }                                                                 \
+    else                                                              \
+    {                                                                 \
+      (__HANDLE__)->Mask = 0x0000U;                                   \
+    }                                                                 \
+  } while(0U)
+
+/**
+  * @brief Ensure that UART frame length is valid.
+  * @param __LENGTH__ UART frame length.
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
+                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \
+                                         ((__LENGTH__) == UART_WORDLENGTH_9B))
+
+/**
+  * @brief Ensure that UART wake-up address length is valid.
+  * @param __ADDRESS__ UART wake-up address length.
+  * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
+  */
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
+                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
+
+/**
+  * @brief Ensure that UART TXFIFO threshold level is valid.
+  * @param __THRESHOLD__ UART TXFIFO threshold level.
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
+
+/**
+  * @brief Ensure that UART RXFIFO threshold level is valid.
+  * @param __THRESHOLD__ UART RXFIFO threshold level.
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G0xx_HAL_UART_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c

@@ -0,0 +1,759 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal.c
+  * @author  MCD Application Team
+  * @brief   HAL module driver.
+  *          This is the common part of the HAL initialization
+  *
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The common HAL driver contains a set of generic and common APIs that can be
+    used by the PPP peripheral drivers and the user to start using the HAL.
+    [..]
+    The HAL contains two APIs categories:
+         (+) Common HAL APIs
+         (+) Services HAL APIs
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HAL
+  * @brief HAL module driver
+  * @{
+  */
+
+#ifdef HAL_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup HAL_Private_Constants HAL Private Constants
+  * @{
+  */
+/**
+  * @brief STM32G0xx HAL Driver version number
+  */
+#define __STM32G0xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
+#define __STM32G0xx_HAL_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
+#define __STM32G0xx_HAL_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
+#define __STM32G0xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32G0xx_HAL_VERSION         ((__STM32G0xx_HAL_VERSION_MAIN << 24U)\
+                                        |(__STM32G0xx_HAL_VERSION_SUB1 << 16U)\
+                                        |(__STM32G0xx_HAL_VERSION_SUB2 << 8U )\
+                                        |(__STM32G0xx_HAL_VERSION_RC))
+
+#if defined(VREFBUF)
+#define VREFBUF_TIMEOUT_VALUE     10U   /*!<  10 ms */
+#endif /* VREFBUF */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Exported variables ---------------------------------------------------------*/
+/** @defgroup HAL_Exported_Variables HAL Exported Variables
+  * @{
+  */
+__IO uint32_t uwTick;
+uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group1
+ *  @brief    HAL Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+           ##### HAL Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the Flash interface the NVIC allocation and initial time base
+          clock configuration.
+      (+) De-initialize common part of the HAL.
+      (+) Configure the time base source to have 1ms time base with a dedicated
+          Tick interrupt priority.
+        (++) SysTick timer is used by default as source of time base, but user
+             can eventually implement his proper time base source (a general purpose
+             timer for example or other time source), keeping in mind that Time base
+             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+             handled in milliseconds basis.
+        (++) Time base configuration function (HAL_InitTick ()) is called automatically
+             at the beginning of the program after reset by HAL_Init() or at any time
+             when clock is configured, by HAL_RCC_ClockConfig().
+        (++) Source of time base is configured  to generate interrupts at regular
+             time intervals. Care must be taken if HAL_Delay() is called from a
+             peripheral ISR process, the Tick interrupt line must have higher priority
+            (numerically lower) than the peripheral interrupt. Otherwise the caller
+            ISR process will be blocked.
+       (++) functions affecting time base configurations are declared as __weak
+             to make  override possible  in case of other  implementations in user file.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the Flash prefetch and the Instruction cache,
+  *         the time base source, NVIC and any required global low level hardware
+  *         by calling the HAL_MspInit() callback function to be optionally defined in user file
+  *         stm32g0xx_hal_msp.c.
+  *
+  * @note   HAL_Init() function is called at the beginning of program after reset and before
+  *         the clock configuration.
+  *
+  * @note   In the default implementation the System Timer (Systick) is used as source of time base.
+  *         The Systick configuration is based on HSI clock, as HSI is the clock
+  *         used after a system Reset.
+  *         Once done, time base tick starts incrementing: the tick variable counter is incremented
+  *         each 1ms in the SysTick_Handler() interrupt handler.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_Init(void)
+{
+  HAL_StatusTypeDef  status = HAL_OK;
+
+  /* Configure Flash prefetch, Instruction cache             */
+  /* Default configuration at reset is:                      */
+  /* - Prefetch disabled                                     */
+  /* - Instruction cache enabled                             */
+
+#if (INSTRUCTION_CACHE_ENABLE == 0U)
+  __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+#endif /* INSTRUCTION_CACHE_ENABLE */
+
+#if (PREFETCH_ENABLE != 0U)
+  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+  /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+  /* Init the low level hardware */
+  HAL_MspInit();
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  This function de-Initializes common part of the HAL and stops the source of time base.
+  * @note   This function is optional.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+  /* Reset of all peripherals */
+  __HAL_RCC_APB1_FORCE_RESET();
+  __HAL_RCC_APB1_RELEASE_RESET();
+
+  __HAL_RCC_APB2_FORCE_RESET();
+  __HAL_RCC_APB2_RELEASE_RESET();
+
+  __HAL_RCC_AHB_FORCE_RESET();
+  __HAL_RCC_AHB_RELEASE_RESET();
+
+  __HAL_RCC_IOP_FORCE_RESET();
+  __HAL_RCC_IOP_RELEASE_RESET();
+
+  /* De-Init the low level hardware */
+  HAL_MspDeInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the MSP.
+  * @retval None
+  */
+__weak void HAL_MspInit(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the MSP.
+  * @retval None
+  */
+__weak void HAL_MspDeInit(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief This function configures the source of the time base:
+  *        The time source is configured  to have 1ms time base with a dedicated
+  *        Tick interrupt priority.
+  * @note This function is called  automatically at the beginning of program after
+  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
+  * @note In the default implementation, SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals.
+  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+  *       The SysTick interrupt must have higher priority (numerically lower)
+  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+  *       The function is declared as __weak  to be overwritten  in case of other
+  *       implementation  in user file.
+  * @param TickPriority Tick interrupt priority.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  HAL_StatusTypeDef  status = HAL_OK;
+
+  /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/ 
+  if ((uint32_t)uwTickFreq != 0U)
+  {
+    /*Configure the SysTick to have interrupt in 1ms time basis*/
+    if (HAL_SYSTICK_Config(SystemCoreClock / (1000U /(uint32_t)uwTickFreq)) == 0U)
+    {
+      /* Configure the SysTick IRQ priority */
+      if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+      {
+        HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+        uwTickPrio = TickPriority;
+      }
+      else
+      {
+        status = HAL_ERROR;
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group2
+ *  @brief    HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### HAL Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Provide a tick value in millisecond
+      (+) Provide a blocking delay in millisecond
+      (+) Suspend the time base source interrupt
+      (+) Resume the time base source interrupt
+      (+) Get the HAL API driver version
+      (+) Get the device identifier
+      (+) Get the device revision identifier
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief This function is called to increment  a global variable "uwTick"
+  *        used as application time base.
+  * @note In the default implementation, this variable is incremented each 1ms
+  *       in SysTick ISR.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *      implementations in user file.
+  * @retval None
+  */
+__weak void HAL_IncTick(void)
+{
+  uwTick += (uint32_t)uwTickFreq;
+}
+
+/**
+  * @brief Provides a tick value in millisecond.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval tick value
+  */
+__weak uint32_t HAL_GetTick(void)
+{
+  return uwTick;
+}
+
+/**
+  * @brief This function returns a tick priority.
+  * @retval tick priority
+  */
+uint32_t HAL_GetTickPrio(void)
+{
+  return uwTickPrio;
+}
+
+/**
+  * @brief Set new tick Freq.
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+{
+  HAL_StatusTypeDef status  = HAL_OK;
+  HAL_TickFreqTypeDef prevTickFreq;
+  assert_param(IS_TICKFREQ(Freq));
+
+  if (uwTickFreq != Freq)
+  {
+    /* Back up uwTickFreq frequency */
+    prevTickFreq = uwTickFreq;
+
+    /* Update uwTickFreq global variable used by HAL_InitTick() */
+    uwTickFreq = Freq;
+
+    /* Apply the new tick Freq  */
+    status = HAL_InitTick(uwTickPrio);
+    if (status != HAL_OK)
+    {
+      /* Restore previous tick frequency */
+      uwTickFreq = prevTickFreq;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief return tick frequency.
+  * @retval tick period in Hz
+  */
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+{
+  return uwTickFreq;
+}
+
+/**
+  * @brief This function provides minimum delay (in milliseconds) based
+  *        on variable incremented.
+  * @note In the default implementation , SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals where uwTick
+  *       is incremented.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @param Delay  specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+__weak void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += (uint32_t)(uwTickFreq);
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
+  {
+  }
+}
+
+/**
+  * @brief Suspend Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+  *       is called, the SysTick interrupt will be disabled and so Tick increment
+  *       is suspended.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_SuspendTick(void)
+{
+  /* Disable SysTick Interrupt */
+  CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief Resume Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+  *       is called, the SysTick interrupt will be enabled and so Tick increment
+  *       is resumed.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_ResumeTick(void)
+{
+  /* Enable SysTick Interrupt */
+  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Returns the HAL revision
+  * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+  */
+uint32_t HAL_GetHalVersion(void)
+{
+  return __STM32G0xx_HAL_VERSION;
+}
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @retval Device revision identifier
+  */
+uint32_t HAL_GetREVID(void)
+{
+  return ((DBG->IDCODE & DBG_IDCODE_REV_ID) >> 16U);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @retval Device identifier
+  */
+uint32_t HAL_GetDEVID(void)
+{
+  return ((DBG->IDCODE) & DBG_IDCODE_DEV_ID);
+}
+
+/**
+  * @brief  Returns first word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw0(void)
+{
+  return (READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+  * @brief  Returns second word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw1(void)
+{
+  return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+  * @brief  Returns third word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw2(void)
+{
+  return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group3
+ *  @brief    HAL Debug functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### HAL Debug functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Enable/Disable Debug module during STOP mode
+      (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable the Debug Module during STOP mode
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGStopMode(void)
+{
+  SET_BIT(DBG->CR, DBG_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Disable the Debug Module during STOP mode
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBG->CR, DBG_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STANDBY mode
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBG->CR, DBG_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Disable the Debug Module during STANDBY mode
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBG->CR, DBG_CR_DBG_STANDBY);
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group4
+ *  @brief    SYSCFG configuration functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### HAL SYSCFG configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Enable/Disable Pin remap
+      (+) Configure the Voltage reference buffer
+      (+) Enable/Disable the Voltage reference buffer
+      (+) Enable/Disable the I/O analog switch voltage booster
+      (+) Enable/Disable dead battery behavior(*)
+      (+) Configure Clamping Diode on specific pins(*)
+   (*) Feature not available on all devices
+
+@endverbatim
+  * @{
+  */
+#if defined(VREFBUF)
+/**
+  * @brief Configure the internal voltage reference buffer voltage scale.
+  * @param  VoltageScaling specifies the output voltage to achieve
+  *         This parameter can be one of the following values:
+  *         @arg @ref SYSCFG_VREFBUF_VoltageScale
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
+
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
+}
+
+/**
+  * @brief Configure the internal voltage reference buffer high impedance mode.
+  * @param  Mode specifies the high impedance mode
+  *          This parameter can be one of the following values:
+  *          @arg @ref SYSCFG_VREFBUF_HighImpedance
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
+
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
+}
+
+/**
+  * @brief  Tune the Internal Voltage Reference buffer (VREFBUF).
+  * @note   VrefBuf voltage scale is calibrated in production for each device,
+  *         using voltage scale 1. This calibration value is loaded
+  *         as default trimming value at device power up.
+  *         This trimming value can be fine tuned for voltage scales 0 and 1
+  *         using this function.
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
+
+  MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
+}
+
+/**
+  * @brief  Enable the Internal Voltage Reference buffer (VREFBUF).
+  * @retval HAL_OK/HAL_TIMEOUT
+  */
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
+{
+  uint32_t  tickstart;
+
+  SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+
+  /* Wait for VRR bit  */
+  while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0x00U)
+  {
+    if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Internal Voltage Reference buffer (VREFBUF).
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_DisableVREFBUF(void)
+{
+  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+#endif /* VREFBUF */
+
+/**
+  * @brief  Enable the I/O analog switch voltage booster
+  * @retval None
+  */
+void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void)
+{
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+  * @brief  Disable the I/O analog switch voltage booster
+  * @retval None
+  */
+void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+  * @brief  Enable the remap on PA11_PA12
+  * @param  PinRemap specifies which pins have to be remapped
+  *         This parameter can be any combination of the following values:
+  *         @arg @ref SYSCFG_REMAP_PA11
+  *         @arg @ref SYSCFG_REMAP_PA12
+  * @retval None
+  */
+void HAL_SYSCFG_EnableRemap(uint32_t PinRemap)
+{
+  /* Check the parameter */
+  assert_param(IS_HAL_REMAP_PIN(PinRemap));
+  SET_BIT(SYSCFG->CFGR1, PinRemap);
+}
+
+/**
+  * @brief  Disable the remap on PA11_PA12
+  * @param  PinRemap specifies which pins will behave normally
+  *         This parameter can be any combination of the following values:
+  *         @arg @ref SYSCFG_REMAP_PA11
+  *         @arg @ref SYSCFG_REMAP_PA12
+  * @retval None
+  */
+void HAL_SYSCFG_DisableRemap(uint32_t PinRemap)
+{
+  /* Check the parameter */
+  assert_param(IS_HAL_REMAP_PIN(PinRemap));
+  CLEAR_BIT(SYSCFG->CFGR1, PinRemap);
+}
+
+#if defined(SYSCFG_CDEN_SUPPORT)
+/**
+  * @brief  Enable Clamping Diode on specified IO
+  * @param  PinConfig specifies on which pins clamping Diode has to be enabled
+  *         This parameter can be any combination of the following values:
+  *         @arg @ref SYSCFG_ClampingDiode
+  * @retval None
+  */
+void HAL_SYSCFG_EnableClampingDiode(uint32_t PinConfig)
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_CLAMPINGDIODE(PinConfig));
+  SET_BIT(SYSCFG->CFGR2, PinConfig);
+}
+
+/**
+  * @brief  Disable Clamping Diode on specified IO
+  * @param  PinConfig specifies on which pins clamping Diode has to be disabled
+  *         This parameter can be any combination of the following values:
+  *         @arg @ref SYSCFG_ClampingDiode
+  * @retval None
+  */
+void HAL_SYSCFG_DisableClampingDiode(uint32_t PinConfig)
+{
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_CLAMPINGDIODE(PinConfig));
+  CLEAR_BIT(SYSCFG->CFGR2, PinConfig);
+}
+#endif /* SYSCFG_CDEN_SUPPORT */
+
+#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
+/**
+  * @brief  Strobe configuration of GPIO depending on UCPDx dead battery settings
+  * @param  ConfigDeadBattery specifies on which pins to make effective or not Dead Battery sw configuration
+  *         This parameter can be any combination of the following values:
+  *         @arg @ref SYSCFG_UCPD1_STROBE
+  *         @arg @ref SYSCFG_UCPD2_STROBE
+  * @retval None
+  */
+void HAL_SYSCFG_StrobeDBattpinsConfig(uint32_t ConfigDeadBattery)
+{
+  assert_param(IS_SYSCFG_DBATT_CONFIG(ConfigDeadBattery));
+
+  /* Change strobe configuration of GPIO depending on UCPDx dead battery settings */
+  MODIFY_REG(SYSCFG->CFGR1, (SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE), ConfigDeadBattery);
+}
+#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c

@@ -0,0 +1,417 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_cortex.c
+  * @author  MCD Application Team
+  * @brief   CORTEX HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the CORTEX:
+  *           + Initialization and Configuration functions
+  *           + Peripheral Control functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    *** How to configure Interrupts using CORTEX HAL driver ***
+    ===========================================================
+    [..]
+    This section provides functions allowing to configure the NVIC interrupts (IRQ).
+    The Cortex M0+ exceptions are managed by CMSIS functions.
+      (#) Enable and Configure the priority of the selected IRQ Channels.
+             The priority can be 0..3.
+
+        -@- Lower priority values gives higher priority.
+        -@- Priority Order:
+            (#@) Lowest priority.
+            (#@) Lowest hardware priority (IRQn position).
+
+      (#)  Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
+
+      (#)  Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
+
+      -@-  Negative value of IRQn_Type are not allowed.
+
+    *** How to configure Systick using CORTEX HAL driver ***
+    ========================================================
+    [..]
+    Setup SysTick Timer for time base.
+
+   (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
+       is a CMSIS function that:
+        (++) Configures the SysTick Reload register with value passed as function parameter.
+        (++) Configures the SysTick IRQ priority to the lowest value (0x03).
+        (++) Resets the SysTick Counter register.
+        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+        (++) Enables the SysTick Interrupt.
+        (++) Starts the SysTick Counter.
+
+   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+       inside the stm32g0xx_hal_cortex.h file.
+
+   (+) You can change the SysTick IRQ priority by calling the
+       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+   (+) To adjust the SysTick time base, use the following formula:
+
+       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
+       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+       (++) Reload Value should not exceed 0xFFFFFF
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CORTEX
+  * @{
+  */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CORTEX_Exported_Functions
+  * @{
+  */
+
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+  ==============================================================================
+              ##### Initialization and Configuration functions #####
+  ==============================================================================
+    [..]
+      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+      Systick functionalities
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Sets the priority of an interrupt.
+  * @param IRQn External interrupt number .
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32g0xx.h file)
+  * @param PreemptPriority The preemption priority for the IRQn channel.
+  *         This parameter can be a value between 0 and 3.
+  *         A lower priority value indicates a higher priority
+  * @param SubPriority the subpriority level for the IRQ channel.
+  *         with stm32g0xx devices, this parameter is a dummy value and it is ignored, because
+  *         no subpriority supported in Cortex M0+ based products.
+  * @retval None
+  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+  NVIC_SetPriority(IRQn,PreemptPriority);
+}
+
+/**
+  * @brief  Enable a device specific interrupt in the NVIC interrupt controller.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Enable interrupt */
+  NVIC_EnableIRQ(IRQn);
+}
+
+/**
+  * @brief  Disable a device specific interrupt in the NVIC interrupt controller.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Disable interrupt */
+  NVIC_DisableIRQ(IRQn);
+}
+
+/**
+  * @brief  Initiate a system reset request to reset the MCU.
+  * @retval None
+  */
+void HAL_NVIC_SystemReset(void)
+{
+  /* System Reset */
+  NVIC_SystemReset();
+}
+
+/**
+  * @brief  Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
+  *         Counter is in free running mode to generate periodic interrupts.
+  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
+  * @retval status:  - 0  Function succeeded.
+  *                  - 1  Function failed.
+  */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+  return SysTick_Config(TicksNumb);
+}
+/**
+  * @}
+  */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ *  @brief   Cortex control functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+    [..]
+      This subsection provides a set of functions allowing to control the CORTEX
+      (NVIC, SYSTICK, MPU) functionalities.
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the priority of an interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
+  * @retval None
+  */
+uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
+{
+  /* Get priority for Cortex-M system or device specific interrupts */
+  return NVIC_GetPriority(IRQn);
+}
+
+/**
+  * @brief  Set Pending bit of an external interrupt.
+  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Set interrupt pending */
+  NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Get Pending Interrupt (read the pending register in the NVIC
+  *         and return the pending bit for the specified interrupt).
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
+  * @retval status: - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Return 1 if pending else 0 */
+  return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Clear the pending bit of an external interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Clear pending interrupt */
+  NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Configure the SysTick clock source.
+  * @param CLKSource specifies the SysTick clock source.
+  *         This parameter can be one of the following values:
+  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+  {
+    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+  }
+}
+
+/**
+  * @brief  Handle SYSTICK interrupt request.
+  * @retval None
+  */
+void HAL_SYSTICK_IRQHandler(void)
+{
+  HAL_SYSTICK_Callback();
+}
+
+/**
+  * @brief  SYSTICK callback.
+  * @retval None
+  */
+__weak void HAL_SYSTICK_Callback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SYSTICK_Callback could be implemented in the user file
+   */
+}
+
+#if (__MPU_PRESENT == 1U)
+/**
+  * @brief  Enable the MPU.
+  * @param  MPU_Control Specifies the control mode of the MPU during hard fault,
+  *          NMI, FAULTMASK and privileged access to the default memory
+  *          This parameter can be one of the following values:
+  *            @arg MPU_HFNMI_PRIVDEF_NONE
+  *            @arg MPU_HARDFAULT_NMI
+  *            @arg MPU_PRIVILEGED_DEFAULT
+  *            @arg MPU_HFNMI_PRIVDEF
+  * @retval None
+  */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+  /* Enable the MPU */
+  MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
+
+  /* Ensure MPU setting take effects */
+  __DSB();
+  __ISB();
+}
+
+
+/**
+  * @brief  Disable the MPU.
+  * @retval None
+  */
+void HAL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+
+  /* Disable the MPU and clear the control register*/
+  MPU->CTRL  = 0;
+}
+
+
+/**
+  * @brief  Initialize and configure the Region and the memory to be protected.
+  * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+  *                the initialization and configuration information.
+  * @retval None
+  */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+  /* Set the Region number */
+  MPU->RNR = MPU_Init->Number;
+
+  if ((MPU_Init->Enable) != 0U)
+  {
+    /* Check the parameters */
+    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+    MPU->RBAR = MPU_Init->BaseAddress;
+    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
+                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
+                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
+                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
+                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
+                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
+                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
+                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
+  }
+  else
+  {
+    MPU->RBAR = 0x00U;
+    MPU->RASR = 0x00U;
+  }
+}
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c

@@ -0,0 +1,320 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_dma_ex.c
+  * @author  MCD Application Team
+  * @brief   DMA Extension HAL module driver
+  *         This file provides firmware functions to manage the following
+  *         functionalities of the DMA Extension peripheral:
+  *           + Extended features functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+  The DMA Extension HAL driver can be used as follows:
+   (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
+   (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
+       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
+       to respectively enable/disable the request generator.
+
+   (+) To handle the DMAMUX Interrupts, the function  HAL_DMAEx_MUX_IRQHandler should be called from
+       the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler.
+       As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be
+       called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
+      (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMAEx DMAEx
+  * @brief DMA Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private Constants ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
+  * @{
+  */
+
+/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions
+ *  @brief   Extended features functions
+ *
+@verbatim
+ ===============================================================================
+                #####  Extended features functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+
+    (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
+    (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
+       Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
+       to respectively enable/disable the request generator.
+    (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from
+        the DMAMUX IRQ handler
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
+  * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *             the configuration information for the specified DMA channel.
+  * @param pSyncConfig Pointer to HAL_DMA_MuxSyncConfigTypeDef contains the DMAMUX synchronization parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
+
+  assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity));
+  assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
+  assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
+  assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
+
+  /*Check if the DMA state is ready */
+  if (hdma->State == HAL_DMA_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+
+    /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
+    MODIFY_REG(hdma->DMAmuxChannel->CCR, \
+               (~DMAMUX_CxCR_DMAREQ_ID), \
+               (pSyncConfig->SyncSignalID | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
+                pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \
+                ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)));
+
+    /* Process UnLocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* Return error status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance).
+  * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *             the configuration information for the specified DMA channel.
+  * @param pRequestGeneratorConfig Pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef
+  *                                contains the request generator parameters.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
+{
+  HAL_StatusTypeDef status;
+  HAL_DMA_StateTypeDef temp_state = hdma->State;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
+
+  assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
+  assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
+
+  /* check if the DMA state is ready
+     and DMA is using a DMAMUX request generator block
+  */
+  if (hdma->DMAmuxRequestGen == 0U)
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+
+    /* error status */
+    status = HAL_ERROR;
+  }
+  else if (((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY))
+  {
+    /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */
+
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+
+    /* Set the request generator new parameters*/
+    hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
+                                   ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos) | \
+                                   pRequestGeneratorConfig->Polarity;
+    /* Process UnLocked */
+    __HAL_UNLOCK(hdma);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+    /* error status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief Enable the DMAMUX request generator block used by the given DMA channel (instance).
+  * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *             the configuration information for the specified DMA channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  /* check if the DMA state is ready
+     and DMA is using a DMAMUX request generator block
+  */
+  if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
+  {
+
+    /* Enable the request generator*/
+    hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief Disable the DMAMUX request generator block used by the given DMA channel (instance).
+  * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *             the configuration information for the specified DMA channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  /* check if the DMA state is ready
+     and DMA is using a DMAMUX request generator block
+  */
+  if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
+  {
+
+    /* Disable the request generator*/
+    hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief Handles DMAMUX interrupt request.
+  * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *             the configuration information for the specified DMA channel.
+  * @retval None
+  */
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+  /* Check for DMAMUX Synchronization overrun */
+  if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
+  {
+    /* Disable the synchro overrun interrupt */
+    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+
+    /* Clear the DMAMUX synchro overrun flag */
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+    /* Update error code */
+    hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
+
+    if (hdma->XferErrorCallback != NULL)
+    {
+      /* Transfer error callback */
+      hdma->XferErrorCallback(hdma);
+    }
+  }
+
+  if (hdma->DMAmuxRequestGen != 0)
+  {
+    /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
+    if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
+    {
+      /* Disable the request gen overrun interrupt */
+      hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
+
+      if (hdma->XferErrorCallback != NULL)
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+      }
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c

@@ -0,0 +1,681 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_exti.c
+  * @author  MCD Application Team
+  * @brief   EXTI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (EXTI) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### EXTI Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each Exti line can be configured within this driver.
+
+    (+) Exti line can be configured in 3 different modes
+        (++) Interrupt
+        (++) Event
+        (++) Both of them
+
+    (+) Configurable Exti lines can be configured with 3 different triggers
+        (++) Rising
+        (++) Falling
+        (++) Both of them
+
+    (+) When set in interrupt mode, configurable Exti lines have two diffenrents
+        interrupt pending registers which allow to distinguish which transition
+        occurs:
+        (++) Rising edge pending interrupt
+        (++) Falling
+
+    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+        be selected through multiplexer.
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+
+    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
+        (++) Choose the interrupt line number by setting "Line" member from
+             EXTI_ConfigTypeDef structure.
+        (++) Configure the interrupt and/or event mode using "Mode" member from
+             EXTI_ConfigTypeDef structure.
+        (++) For configurable lines, configure rising and/or falling trigger
+             "Trigger" member from EXTI_ConfigTypeDef structure.
+        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+             member from GPIO_InitTypeDef structure.
+
+    (#) Get current Exti configuration of a dedicated line using
+        HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
+
+    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+
+    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
+        (++) Provide exiting handle as first parameter.
+        (++) Provide which callback will be registered using one value from
+             EXTI_CallbackIDTypeDef.
+        (++) Provide callback function pointer.
+
+    (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+
+    (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
+
+    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+/** MISRA C:2012 deviation rule has been granted for following rule:
+  * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
+  * of bounds [0,3] in following API :
+  * HAL_EXTI_SetConfigLine
+  * HAL_EXTI_GetConfigLine
+  * HAL_EXTI_ClearConfigLine
+  */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+#define EXTI_MODE_OFFSET                    0x04u   /* 0x10: offset between CPU IMR/EMR registers */
+#define EXTI_CONFIG_OFFSET                  0x08u   /* 0x20: offset between CPU Rising/Falling configuration registers */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group1
+ *  @brief    Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on EXTI configuration to be set.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+  assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
+
+  /* Assign line number to handle */
+  hexti->Line = pExtiConfig->Line;
+
+  /* compute line register offset and line mask */
+  offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  /* Configure triggers for configurable lines */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+  {
+    assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+    /* Configure rising trigger */
+    regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
+    {
+      regval |= maskline;
+    }
+    else
+    {
+      regval &= ~maskline;
+    }
+
+    /* Store rising trigger mode */
+    *regaddr = regval;
+
+    /* Configure falling trigger */
+    regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
+    {
+      regval |= maskline;
+    }
+    else
+    {
+      regval &= ~maskline;
+    }
+
+    /* Store falling trigger mode */
+    *regaddr = regval;
+
+    /* Configure gpio port selection in case of gpio exti line */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = EXTI->EXTICR[linepos >> 2u];
+      regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+      regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+      EXTI->EXTICR[linepos >> 2u] = regval;
+    }
+  }
+
+  /* Configure interrupt mode : read current mode */
+  regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store interrupt mode */
+  *regaddr = regval;
+
+  /* Configure event mode : read current mode */
+  regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
+  {
+    regval |= maskline;
+  }
+  else
+  {
+    regval &= ~maskline;
+  }
+
+  /* Store event mode */
+  *regaddr = regval;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Get configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on structure to store Exti configuration.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* Store handle line number to configiguration structure */
+  pExtiConfig->Line = hexti->Line;
+
+  /* compute line register offset and line mask */
+  offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  /* 1] Get core mode : interrupt */
+  regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00u)
+  {
+    pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
+  }
+  else
+  {
+    pExtiConfig->Mode = EXTI_MODE_NONE;
+  }
+
+  /* Get event mode */
+  regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = *regaddr;
+
+  /* Check if selected line is enable */
+  if ((regval & maskline) != 0x00u)
+  {
+    pExtiConfig->Mode |= EXTI_MODE_EVENT;
+  }
+
+  /* 2] Get trigger for configurable lines : rising */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+  {
+    regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Check if configuration of selected line is enable */
+    if ((regval & maskline) != 0x00u)
+    {
+      pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+    }
+    else
+    {
+      pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+    }
+
+    /* Get falling configuration */
+    regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = *regaddr;
+
+    /* Check if configuration of selected line is enable */
+    if ((regval & maskline) != 0x00u)
+    {
+      pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+    }
+
+    /* Get Gpio port selection for gpio lines */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = EXTI->EXTICR[linepos >> 2u];
+      pExtiConfig->GPIOSel = ((regval << (EXTI_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
+    }
+    else
+    {
+      pExtiConfig->GPIOSel = 0x00u;
+    }
+  }
+  else
+  {
+    pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+    pExtiConfig->GPIOSel = 0x00u;
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Clear whole configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  /* 1] Clear interrupt mode */
+  regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+
+  /* 2] Clear event mode */
+  regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
+  regval = (*regaddr & ~maskline);
+  *regaddr = regval;
+
+  /* 3] Clear triggers in case of configurable lines */
+  if ((hexti->Line & EXTI_CONFIG) != 0x00u)
+  {
+    regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = (*regaddr & ~maskline);
+    *regaddr = regval;
+
+    regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+    regval = (*regaddr & ~maskline);
+    *regaddr = regval;
+
+    /* Get Gpio port selection for gpio lines */
+    if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = EXTI->EXTICR[linepos >> 2u];
+      regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+      EXTI->EXTICR[linepos >> 2u] = regval;
+    }
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Register callback for a dedicaated Exti line.
+  * @param  hexti Exti handle.
+  * @param  CallbackID User callback identifier.
+  *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+  * @param  pPendingCbfn function pointer to be stored as callback.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  switch (CallbackID)
+  {
+    case  HAL_EXTI_COMMON_CB_ID:
+      hexti->RisingCallback = pPendingCbfn;
+      hexti->FallingCallback = pPendingCbfn;
+      break;
+
+    case  HAL_EXTI_RISING_CB_ID:
+      hexti->RisingCallback = pPendingCbfn;
+      break;
+
+    case  HAL_EXTI_FALLING_CB_ID:
+      hexti->FallingCallback = pPendingCbfn;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  Store line number as handle private field.
+  * @param  hexti Exti handle.
+  * @param  ExtiLine Exti line number.
+  *         This parameter can be from 0 to @ref EXTI_LINE_NB.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(ExtiLine));
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Store line number as handle private field */
+    hexti->Line = ExtiLine;
+
+    return HAL_OK;
+  }
+}
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group2
+ *  @brief EXTI IO functions.
+ *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Handle EXTI interrupt request.
+  * @param  hexti Exti handle.
+  * @retval none.
+  */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+  /* Get rising edge pending bit  */
+  regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
+  regval = (*regaddr & maskline);
+
+  if (regval != 0x00u)
+  {
+    /* Clear pending bit */
+    *regaddr = maskline;
+
+    /* Call rising callback */
+    if (hexti->RisingCallback != NULL)
+    {
+      hexti->RisingCallback();
+    }
+  }
+
+  /* Get falling edge pending bit  */
+  regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
+  regval = (*regaddr & maskline);
+
+  if (regval != 0x00u)
+  {
+    /* Clear pending bit */
+    *regaddr = maskline;
+
+    /* Call rising callback */
+    if (hexti->FallingCallback != NULL)
+    {
+      hexti->FallingCallback();
+    }
+  }
+}
+
+
+/**
+  * @brief  Get interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge Specify which pending edge as to be checked.
+  *         This parameter can be one of the following values:
+  *           @arg @ref EXTI_TRIGGER_RISING
+  *           @arg @ref EXTI_TRIGGER_FALLING
+  * @retval 1 if interrupt is pending else 0.
+  */
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  __IO uint32_t *regaddr;
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  if (Edge != EXTI_TRIGGER_RISING)
+  {
+    /* Get falling edge pending bit */
+    regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
+  }
+  else
+  {
+    /* Get rising edge pending bit */
+    regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
+  }
+
+  /* return 1 if bit is set else 0 */
+  regval = ((*regaddr & maskline) >> linepos);
+  return regval;
+}
+
+
+/**
+  * @brief  Clear interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge Specify which pending edge as to be clear.
+  *         This parameter can be one of the following values:
+  *           @arg @ref EXTI_TRIGGER_RISING
+  *           @arg @ref EXTI_TRIGGER_FALLING
+  * @retval None.
+  */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  __IO uint32_t *regaddr;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+  if (Edge != EXTI_TRIGGER_RISING)
+  {
+    /* Get falling edge pending register address */
+    regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
+  }
+  else
+  {
+    /* Get falling edge pending register address */
+    regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
+  }
+
+  /* Clear Pending bit */
+  *regaddr =  maskline;
+}
+
+
+/**
+  * @brief  Generate a software interrupt for a dedicated line.
+  * @param  hexti Exti handle.
+  * @retval None.
+  */
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
+{
+  __IO uint32_t *regaddr;
+  uint32_t maskline;
+  uint32_t offset;
+
+  /* Check parameterd */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+
+  /* compute line register offset and line mask */
+  offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+  regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
+  *regaddr = maskline;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_EXTI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c

@@ -0,0 +1,719 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_flash.c
+  * @author  MCD Application Team
+  * @brief   FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the internal FLASH memory:
+  *           + Program operations functions
+  *           + Memory Control functions
+  *           + Peripheral Errors functions
+  *
+ @verbatim
+  ==============================================================================
+                        ##### FLASH peripheral features #####
+  ==============================================================================
+
+  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
+       to the Flash memory. It implements the erase and program Flash memory operations
+       and the read and write protection mechanisms.
+
+  [..] The Flash memory interface accelerates code execution with a system of instruction
+       prefetch and cache lines.
+
+  [..] The FLASH main features are:
+      (+) Flash memory read operations
+      (+) Flash memory program/erase operations
+      (+) Read / write protections
+      (+) Option bytes programming
+      (+) Prefetch on I-Code
+      (+) 32 cache lines of 4*64 bits on I-Code
+      (+) Error code correction (ECC) : Data in flash are 72-bits word
+          (8 bits added per double word)
+
+                        ##### How to use this driver #####
+ ==============================================================================
+    [..]
+      This driver provides functions and macros to configure and program the FLASH
+      memory of all STM32G0xx devices.
+
+      (#) Flash Memory IO Programming functions:
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+                HAL_FLASH_Lock() functions
+           (++) Program functions: double word and fast program (full row programming)
+           (++) There are two modes of programming:
+            (+++) Polling mode using HAL_FLASH_Program() function
+            (+++) Interrupt mode using HAL_FLASH_Program_IT() function
+
+      (#) Interrupts and flags management functions:
+           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
+           (++) Callback functions are called when the flash operations are finished :
+                HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
+                HAL_FLASH_OperationErrorCallback()
+           (++) Get error flag status by calling HAL_GetError()
+
+      (#) Option bytes management functions :
+           (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
+                HAL_FLASH_OB_Lock() functions
+           (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function.
+                In this case, a reset is generated
+
+    [..]
+      In addition to these functions, this driver includes a set of macros allowing
+      to handle the following operations:
+       (+) Set the latency
+       (+) Enable/Disable the prefetch buffer
+       (+) Enable/Disable the Instruction cache
+       (+) Reset the Instruction cache
+       (+) Enable/Disable the Flash power-down during low-power run and sleep modes
+       (+) Enable/Disable the Flash interrupts
+       (+) Monitor the Flash flags status
+
+ @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASH FLASH
+  * @brief FLASH HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+ * @{
+ */
+/**
+  * @brief  Variable used for Program/Erase sectors under interruption
+  */
+FLASH_ProcessTypeDef pFlash  = {.Lock = HAL_UNLOCKED, \
+                                .ErrorCode = HAL_FLASH_ERROR_NONE, \
+                                .ProcedureOnGoing = FLASH_TYPENONE, \
+                                .Address = 0U, \
+                                .Banks = 0U, \
+                                .Page = 0U, \
+                                .NbPagesToErase = 0U
+                               };
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private Functions
+ * @{
+ */
+static void          FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
+static void          FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
+  * @{
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
+ *  @brief   Programming operation functions
+ *
+@verbatim
+ ===============================================================================
+                  ##### Programming operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the FLASH
+    program operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Program double word or fast program of a row at a specified address.
+  * @param  TypeProgram Indicate the way to program at a specified address.
+  *                      This parameter can be a value of @ref FLASH_Type_Program
+  * @param  Address Specifies the address to be programmed.
+  * @param  Data Specifies the data to be programmed
+  *               This parameter is the data for the double word program and the address where
+  *               are stored the data for the row fast program.
+  *
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Reset error code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
+    {
+      /* Check the parameters */
+      assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+      /* Program double-word (64-bit) at a specified address */
+      FLASH_Program_DoubleWord(Address, Data);
+    }
+    else
+    {
+      /* Check the parameters */
+      assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address));
+
+      /* Fast program a 32 row double-word (64-bit) at a specified address */
+      FLASH_Program_Fast(Address, (uint32_t)Data);
+    }
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+    /* If the program operation is completed, disable the PG or FSTPG Bit */
+    CLEAR_BIT(FLASH->CR, TypeProgram);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  /* return status */
+  return status;
+}
+
+/**
+  * @brief  Program double word or fast program of a row at a specified address with interrupt enabled.
+  * @param  TypeProgram Indicate the way to program at a specified address.
+  *                      This parameter can be a value of @ref FLASH_Type_Program
+  * @param  Address Specifies the address to be programmed.
+  * @param  Data Specifies the data to be programmed
+  *               This parameter is the data for the double word program and the address where
+  *               are stored the data for the row fast program.
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Reset error code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
+  if (status != HAL_OK)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+  else
+  {
+    /* Set internal variables used by the IRQ handler */
+    pFlash.ProcedureOnGoing = TypeProgram;
+    pFlash.Address = Address;
+
+    /* Enable End of Operation and Error interrupts */
+    FLASH->CR |= FLASH_CR_EOPIE | FLASH_CR_ERRIE;
+
+    if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
+    {
+      /* Check the parameters */
+      assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+      /* Program double-word (64-bit) at a specified address */
+      FLASH_Program_DoubleWord(Address, Data);
+    }
+    else
+    {
+      /* Check the parameters */
+      assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address));
+
+      /* Fast program a 32 row double-word (64-bit) at a specified address */
+      FLASH_Program_Fast(Address, (uint32_t)Data);
+    }
+  }
+
+  /* return status */
+  return status;
+}
+
+/**
+  * @brief Handle FLASH interrupt request.
+  * @retval None
+  */
+void HAL_FLASH_IRQHandler(void)
+{
+  uint32_t param;
+  uint32_t error;
+
+  /* Save flash errors. */
+  error = (FLASH->SR & FLASH_SR_ERRORS);
+
+  /* A] Set parameter for user or error callbacks */
+  /* check operation was a program or erase */
+  if ((pFlash.ProcedureOnGoing & FLASH_TYPEERASE_MASS) != 0x00U)
+  {
+    /* return bank number */
+    param = pFlash.Banks;
+  }
+  else
+  {
+    /* Clear operation only for page erase or program */
+    CLEAR_BIT(FLASH->CR, pFlash.ProcedureOnGoing);
+
+    if ((pFlash.ProcedureOnGoing & (FLASH_TYPEPROGRAM_DOUBLEWORD | FLASH_TYPEPROGRAM_FAST)) != 0x00U)
+    {
+      /* return address being programmed */
+      param = pFlash.Address;
+    }
+    else
+    {
+      /* return page number being erased */
+      param = pFlash.Page;
+    }
+  }
+
+  /* B] Check errors */
+  if (error != 0x00U)
+  {
+    /*Save the error code*/
+    pFlash.ErrorCode |= error;
+
+    /* clear error flags */
+    FLASH->SR = FLASH_SR_ERRORS;
+
+    /*Stop the procedure ongoing*/
+    pFlash.ProcedureOnGoing = FLASH_TYPENONE;
+
+    /* Error callback */
+    HAL_FLASH_OperationErrorCallback(param);
+  }
+
+  /* C] Check FLASH End of Operation flag */
+  if ((FLASH->SR & FLASH_SR_EOP) != 0x00U)
+  {
+    /* Clear FLASH End of Operation pending bit */
+    FLASH->SR = FLASH_SR_EOP;
+
+    if (pFlash.ProcedureOnGoing == FLASH_TYPEERASE_PAGES)
+    {
+      /* Nb of pages to erased can be decreased */
+      pFlash.NbPagesToErase--;
+
+      /* Check if there are still pages to erase*/
+      if (pFlash.NbPagesToErase != 0x00U)
+      {
+        /* Increment page number */
+        pFlash.Page++;
+        FLASH_PageErase(pFlash.Banks, pFlash.Page);
+      }
+      else
+      {
+        /* No more pages to erase: stop erase pages procedure */
+        pFlash.ProcedureOnGoing = FLASH_TYPENONE;
+      }
+    }
+    else
+    {
+      /*Stop the ongoing procedure */
+      pFlash.ProcedureOnGoing = FLASH_TYPENONE;
+    }
+
+    /* User callback */
+    HAL_FLASH_EndOfOperationCallback(param);
+  }
+
+  if (pFlash.ProcedureOnGoing == FLASH_TYPENONE)
+  {
+    /* Disable End of Operation and Error interrupts */
+    FLASH->CR &= ~(FLASH_CR_EOPIE | FLASH_CR_ERRIE);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+}
+
+/**
+  * @brief  FLASH end of operation interrupt callback.
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+  *                  Mass Erase: 0
+  *                  Page Erase: Page which has been erased
+  *                  Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  FLASH operation error interrupt callback.
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+  *                 Mass Erase: 0
+  *                 Page Erase: Page number which returned an error
+  *                 Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   Management functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the FLASH
+    memory operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlock the FLASH control register access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U)
+  {
+    /* Authorize the FLASH Registers access */
+    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+
+    /* verify Flash is unlock */
+    if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Lock the FLASH control register access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+
+  /* Set the LOCK Bit to lock the FLASH Registers access */
+  SET_BIT(FLASH->CR, FLASH_CR_LOCK);
+
+  /* verify Flash is locked */
+  if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00u)
+  {
+    status = HAL_OK;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unlock the FLASH Option Bytes Registers access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+
+  if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0x00U)
+  {
+    /* Authorizes the Option Byte register programming */
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
+
+    /* verify option bytes are unlocked */
+    if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) == 0x00U)
+    {
+      status = HAL_OK;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Lock the FLASH Option Bytes Registers access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+
+  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+  SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
+
+  /* verify option bytes are locked */
+  if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0x00u)
+  {
+    status = HAL_OK;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Launch the option byte loading.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+  /* Set the bit to force the option byte reloading */
+  SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
+
+  /* We should not reach here : Option byte launch generates Option byte reset
+     so return error */
+  return HAL_ERROR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
+ *  @brief   Peripheral Errors functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Peripheral Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time Errors of the FLASH peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the specific FLASH error flag.
+  * @retval FLASH_ErrorCode The returned value can be
+  *            @arg @ref HAL_FLASH_ERROR_NONE No error set
+  *            @arg @ref HAL_FLASH_ERROR_OP Operation error
+  *            @arg @ref HAL_FLASH_ERROR_PROG Programming error
+  *            @arg @ref HAL_FLASH_ERROR_WRP Write protection error
+  *            @arg @ref HAL_FLASH_ERROR_PGA Programming alignment error
+  *            @arg @ref HAL_FLASH_ERROR_SIZ Size error
+  *            @arg @ref HAL_FLASH_ERROR_PGS Programming sequence error
+  *            @arg @ref HAL_FLASH_ERROR_MIS Fast programming data miss error
+  *            @arg @ref HAL_FLASH_ERROR_FAST Fast programming error
+  *            @arg @ref HAL_FLASH_ERROR_RD Read Protection error (PCROP)(*)
+  *            @arg @ref HAL_FLASH_ERROR_OPTV Option validity error
+  *            @arg @ref HAL_FLASH_ERROR_ECCD two ECC errors have been detected
+  * @note (*) availability depends on devices
+  */
+uint32_t HAL_FLASH_GetError(void)
+{
+  return pFlash.ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASH_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Wait for a FLASH operation to complete.
+  * @param  Timeout maximum flash operation timeout
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+  uint32_t error;
+  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+     Even if the FLASH operation fails, the BUSY flag will be reset and an error
+     flag will be set */
+  uint32_t timeout = HAL_GetTick() + Timeout;
+
+  /* Wait if any operation is ongoing */
+#if defined(FLASH_DBANK_SUPPORT)
+  error = (FLASH_SR_BSY1 | FLASH_SR_BSY2);
+#else
+  error = FLASH_SR_BSY1;
+#endif
+
+  while ((FLASH->SR & error) != 0x00U)
+  {
+    if (HAL_GetTick() >= timeout)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* check flash errors */
+  error = (FLASH->SR & FLASH_SR_ERRORS);
+
+  /* Clear SR register */
+  FLASH->SR = FLASH_SR_CLEAR;
+
+  if (error != 0x00U)
+  {
+    /*Save the error code*/
+    pFlash.ErrorCode = error;
+    return HAL_ERROR;
+  }
+
+  /* Wait for control register to be written */
+  timeout = HAL_GetTick() + Timeout;
+
+  while ((FLASH->SR & FLASH_SR_CFGBSY) != 0x00U)
+  {
+    if (HAL_GetTick() >= timeout)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Program double-word (64-bit) at a specified address.
+  * @param  Address Specifies the address to be programmed.
+  * @param  Data Specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
+{
+  /* Set PG bit */
+  SET_BIT(FLASH->CR, FLASH_CR_PG);
+
+  /* Program first word */
+  *(uint32_t *)Address = (uint32_t)Data;
+
+  /* Barrier to ensure programming is performed in 2 steps, in right order
+    (independently of compiler optimization behavior) */
+  __ISB();
+
+  /* Program second word */
+  *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U);
+}
+
+/**
+  * @brief  Fast program a 32 row double-word (64-bit) at a specified address.
+  * @param  Address Specifies the address to be programmed.
+  * @param  DataAddress Specifies the address where the data are stored.
+  * @retval None
+  */
+static __RAM_FUNC void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
+{
+  uint8_t index = 0;
+  uint32_t dest = Address;
+  uint32_t src = DataAddress;
+  uint32_t primask_bit;
+
+  /* Set FSTPG bit */
+  SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
+
+  /* Enter critical section: row programming should not be longer than 7 ms */
+  primask_bit = __get_PRIMASK();
+  __disable_irq();
+
+  /* Fast Program : 64 words */
+  while (index < 64U)
+  {
+    *(uint32_t *)dest = *(uint32_t *)src;
+    src += 4U;
+    dest += 4U;
+    index++;
+  }
+
+  /* wait for BSY1 in order to be sure that flash operation is ended befoire
+     allowing prefetch in flash. Timeout does not return status, as it will
+     be anyway done later */
+
+#if defined(FLASH_DBANK_SUPPORT)
+  while ((FLASH->SR & (FLASH_SR_BSY1 | FLASH_SR_BSY2)) != 0x00U)
+#else
+  while ((FLASH->SR & FLASH_SR_BSY1) != 0x00U)
+#endif
+  {
+  }
+
+  /* Exit critical section: restore previous priority mask */
+  __set_PRIMASK(primask_bit);
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c

@@ -0,0 +1,554 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_gpio.c
+  * @author  MCD Application Team
+  * @brief   GPIO HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### GPIO Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
+        configured by software in several modes:
+        (++) Input mode
+        (++) Analog mode
+        (++) Output mode
+        (++) Alternate function mode
+        (++) External interrupt/event lines
+
+    (+) During and just after reset, the alternate functions and external interrupt
+        lines are not active and the I/O ports are configured in input floating mode.
+
+    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+        activated or not.
+
+    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+        type and the IO speed can be selected depending on the VDD value.
+
+    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
+        multiplexer that allows only one peripheral alternate function (AF) connected
+       to an IO pin at a time. In this way, there can be no conflict between peripherals
+       sharing the same IO pin.
+
+    (+) All ports have external interrupt/event capability. To use external interrupt
+        lines, the port must be configured in input mode. All available GPIO pins are
+        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+    (+) The external interrupt/event controller consists of up to 28 edge detectors
+        (16 lines are connected to GPIO) for generating event/interrupt requests (each
+        input line can be independently configured to select the type (interrupt or event)
+        and the corresponding trigger event (rising or falling or both). Each line can
+        also be masked independently.
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
+
+    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+             structure.
+        (++) In case of Output or alternate function mode selection: the speed is
+             configured through "Speed" member from GPIO_InitTypeDef structure.
+        (++) In alternate mode is selection, the alternate function connected to the IO
+             is configured through "Alternate" member from GPIO_InitTypeDef structure.
+        (++) Analog mode is required when a pin is to be used as ADC channel
+             or DAC output.
+        (++) In case of external interrupt/event selection the "Mode" member from
+             GPIO_InitTypeDef structure select the type (interrupt or event) and
+             the corresponding trigger event (rising or falling or both).
+
+    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+        HAL_NVIC_EnableIRQ().
+
+    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+    (#) To set/reset the level of a pin configured in output mode use
+        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+    (#) During and just after reset, the alternate functions are not
+        active and the GPIO pins are configured in input floating mode (except JTAG
+        pins).
+
+    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+        priority over the GPIO function.
+
+    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+        general purpose PF0 and PF1, respectively, when the HSE oscillator is off.
+        The HSE has priority over the GPIO function.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+/** MISRA C:2012 deviation rule has been granted for following rules:
+  * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
+  * range of the shift operator in following API :
+  * HAL_GPIO_Init
+  * HAL_GPIO_DeInit
+  */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+  * @{
+  */
+#define GPIO_MODE             (0x00000003u)
+#define EXTI_MODE             (0x10000000u)
+#define GPIO_MODE_IT          (0x00010000u)
+#define GPIO_MODE_EVT         (0x00020000u)
+#define RISING_EDGE           (0x00100000u)
+#define FALLING_EDGE          (0x00200000u)
+#define GPIO_OUTPUT_TYPE      (0x00000010u)
+
+#define GPIO_NUMBER           (16u)
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup GPIO_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group1
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family
+  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+  uint32_t position = 0x00u;
+  uint32_t iocurrent;
+  uint32_t temp;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+  assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+  /* Configure the port pins */
+  while (((GPIO_Init->Pin) >> position) != 0x00u)
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Init->Pin) & (1uL << position);
+
+    if (iocurrent != 0x00u)
+    {
+      /*--------------------- GPIO Mode Configuration ------------------------*/
+      /* In case of Output or Alternate function mode selection */
+      if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+      {
+        /* Check the Speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+        /* Configure the IO Speed */
+        temp = GPIOx->OSPEEDR;
+        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
+        temp |= (GPIO_Init->Speed << (position * 2u));
+        GPIOx->OSPEEDR = temp;
+
+        /* Configure the IO Output Type */
+        temp = GPIOx->OTYPER;
+        temp &= ~(GPIO_OTYPER_OT0 << position) ;
+        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position);
+        GPIOx->OTYPER = temp;
+      }
+
+      /* Activate the Pull-up or Pull down resistor for the current IO */
+      temp = GPIOx->PUPDR;
+      temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
+      temp |= ((GPIO_Init->Pull) << (position * 2u));
+      GPIOx->PUPDR = temp;
+
+      /* In case of Alternate function mode selection */
+      if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+      {
+        /* Check the Alternate function parameters */
+        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+        /* Configure Alternate function mapped with the current IO */
+        temp = GPIOx->AFR[position >> 3u];
+        temp &= ~(0xFu << ((position & 0x07u) * 4u));
+        temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
+        GPIOx->AFR[position >> 3u] = temp;
+      }
+
+      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+      temp = GPIOx->MODER;
+      temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
+      GPIOx->MODER = temp;
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+      {
+        temp = EXTI->EXTICR[position >> 2u];
+        temp &= ~(0x0FuL << (8u * (position & 0x03u)));
+        temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)));
+        EXTI->EXTICR[position >> 2u] = temp;
+
+        /* Clear EXTI line configuration */
+        temp = EXTI->IMR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->IMR1 = temp;
+
+        temp = EXTI->EMR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->EMR1 = temp;
+
+        /* Clear Rising Falling edge configuration */
+        temp = EXTI->RTSR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->RTSR1 = temp;
+
+        temp = EXTI->FTSR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->FTSR1 = temp;
+      }
+    }
+
+    position++;
+  }
+}
+
+/**
+  * @brief  De-initialize the GPIOx peripheral registers to their default reset values.
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family
+  * @param  GPIO_Pin specifies the port bit to be written.
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
+{
+  uint32_t position = 0x00u;
+  uint32_t iocurrent;
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Configure the port pins */
+  while ((GPIO_Pin >> position) != 0x00u)
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Pin) & (1uL << position);
+
+    if (iocurrent != 0x00u)
+    {
+      /*------------------------- EXTI Mode Configuration --------------------*/
+      /* Clear the External Interrupt or Event for the current IO */
+
+      tmp = EXTI->EXTICR[position >> 2u];
+      tmp &= (0x0FuL << (8u * (position & 0x03u)));
+      if (tmp == (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u))))
+      {
+        /* Clear EXTI line configuration */
+        EXTI->IMR1 &= ~(iocurrent);
+        EXTI->EMR1 &= ~(iocurrent);
+
+        /* Clear Rising Falling edge configuration */
+        EXTI->RTSR1 &= ~(iocurrent);
+        EXTI->FTSR1 &= ~(iocurrent);
+
+        tmp = 0x0FuL << (8u * (position & 0x03u));
+        EXTI->EXTICR[position >> 2u] &= ~tmp;
+      }
+
+      /*------------------------- GPIO Mode Configuration --------------------*/
+      /* Configure IO in Analog Mode */
+      GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));
+
+      /* Configure the default Alternate Function in current IO */
+      GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ;
+
+      /* Configure the default value for IO Speed */
+      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
+
+      /* Configure the default value IO Output Type */
+      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT0 << position) ;
+
+      /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
+    }
+
+    position++;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group2
+ *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
+ *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read the specified input port pin.
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family
+  * @param  GPIO_Pin specifies the port bit to read.
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  GPIO_PinState bitstatus;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->IDR & GPIO_Pin) != 0x00u)
+  {
+    bitstatus = GPIO_PIN_SET;
+  }
+  else
+  {
+    bitstatus = GPIO_PIN_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Set or clear the selected data port bit.
+  *
+  * @note   This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
+  *         accesses. In this way, there is no risk of an IRQ occurring between
+  *         the read and the modify access.
+  *
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family
+  * @param  GPIO_Pin specifies the port bit to be written.
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @param  PinState specifies the value to be written to the selected bit.
+  *         This parameter can be one of the GPIO_PinState enum values:
+  *            @arg GPIO_PIN_RESET: to clear the port pin
+  *            @arg GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if (PinState != GPIO_PIN_RESET)
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BRR = (uint32_t)GPIO_Pin;
+  }
+}
+
+/**
+  * @brief  Toggle the specified GPIO pin.
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family
+  * @param  GPIO_Pin specifies the pin to be toggled.
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  uint32_t odr;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* get current Output Data Register value */
+  odr = GPIOx->ODR;
+
+  /* Set selected pins that were at low level, and reset ones that were high */
+  GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
+}
+
+/**
+* @brief  Lock GPIO Pins configuration registers.
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+  * @note   The configuration of the locked GPIO pins can no longer be modified
+  *         until the next reset.
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family
+  * @param  GPIO_Pin specifies the port bits to be locked.
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Apply lock key write sequence */
+  tmp |= GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+  GPIOx->LCKR = GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK register. This read is mandatory to complete key lock sequence */
+  tmp = GPIOx->LCKR;
+
+  /* read again in order to confirm lock is active */
+  if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Handle EXTI interrupt request.
+  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+  /* EXTI line interrupt detected */
+  if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0x00u)
+  {
+    __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin);
+  }
+
+  if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0x00u)
+  {
+    __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin);
+  }
+}
+
+/**
+  * @brief  EXTI line detection callback.
+  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+__weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(GPIO_Pin);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  EXTI line detection callback.
+  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+__weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(GPIO_Pin);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c

@@ -0,0 +1,335 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_i2c_ex.c
+  * @author  MCD Application Team
+  * @brief   I2C Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of I2C Extended peripheral:
+  *           + Extended features functions
+  *
+  @verbatim
+  ==============================================================================
+               ##### I2C peripheral Extended features  #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the I2C interface for STM32G0xx
+       devices contains the following additional features
+
+       (+) Possibility to disable or enable Analog Noise Filter
+       (+) Use of a configured Digital Noise Filter
+       (+) Disable or enable wakeup from Stop mode(s)
+       (+) Disable or enable Fast Mode Plus
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..] This driver provides functions to configure Noise Filter and Wake Up Feature
+    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
+    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
+    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
+          (++) HAL_I2CEx_EnableWakeUp()
+          (++) HAL_I2CEx_DisableWakeUp()
+    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+          (++) HAL_I2CEx_EnableFastModePlus()
+          (++) HAL_I2CEx_DisableFastModePlus()
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2CEx I2CEx
+  * @brief I2C Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
+  * @brief    Extended features functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Extended features functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Noise Filters
+      (+) Configure Wake Up Feature
+      (+) Configure Fast Mode Plus
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure I2C Analog noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  AnalogFilter New state of the Analog filter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Reset I2Cx ANOFF bit */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+    /* Set analog filter bit*/
+    hi2c->Instance->CR1 |= AnalogFilter;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Configure I2C Digital noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+{
+  uint32_t tmpreg;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Get the old register value */
+    tmpreg = hi2c->Instance->CR1;
+
+    /* Reset I2Cx DNF bits [11:8] */
+    tmpreg &= ~(I2C_CR1_DNF);
+
+    /* Set I2Cx DNF coefficient */
+    tmpreg |= DigitalFilter << 8U;
+
+    /* Store the new register value */
+    hi2c->Instance->CR1 = tmpreg;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Enable I2C wakeup from Stop mode(s).
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Enable wakeup from stop mode */
+    hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable I2C wakeup from Stop mode(s).
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Enable wakeup from stop mode */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Enable the I2C fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @retval None
+  */
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Enable fast mode plus driving capability for selected pin */
+  SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @brief Disable the I2C fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @retval None
+  */
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Disable fast mode plus driving capability for selected pin */
+  CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_iwdg.c

@@ -0,0 +1,278 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_iwdg.c
+  * @author  MCD Application Team
+  * @brief   IWDG HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Independent Watchdog (IWDG) peripheral:
+  *           + Initialization and Start functions
+  *           + IO operation functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### IWDG Generic features #####
+  ==============================================================================
+  [..]
+    (+) The IWDG can be started by either software or hardware (configurable
+        through option byte).
+
+    (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
+        active even if the main clock fails.
+
+    (+) Once the IWDG is started, the LSI is forced ON and both cannot be
+        disabled. The counter starts counting down from the reset value (0xFFF).
+        When it reaches the end of count value (0x000) a reset signal is
+        generated (IWDG reset).
+
+    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
+        the IWDG_RLR value is reloaded into the counter and the watchdog reset
+        is prevented.
+
+    (+) The IWDG is implemented in the VDD voltage domain that is still functional
+        in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
+        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
+        reset occurs.
+
+    (+) Debug mode: When the microcontroller enters debug mode (core halted),
+        the IWDG counter either continues to work normally or stops, depending
+        on DBG_IWDG_STOP configuration bit in DBG module, accessible through
+        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
+
+    [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
+         The IWDG timeout may vary due to LSI clock frequency dispersion.
+         STM32G0xx devices provide the capability to measure the LSI clock
+         frequency (LSI clock is internally connected to TIM16 CH1 input capture).
+         The measured value can be used to have an IWDG timeout with an
+         acceptable accuracy.
+
+    [..] Default timeout value (necessary for IWDG_SR status register update):
+         Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
+         This frequency being subject to variations as mentioned above, the
+         default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
+         below) may become too short or too long.
+         In such cases, this default timeout value can be tuned by redefining
+         the constant LSI_VALUE at user-application level (based, for instance,
+         on the measured LSI clock frequency as explained above).
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#) Use IWDG using HAL_IWDG_Init() function to :
+      (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
+           clock is forced ON and IWDG counter starts counting down.
+      (++) Enable write access to configuration registers:
+          IWDG_PR, IWDG_RLR and IWDG_WINR.
+      (++) Configure the IWDG prescaler and counter reload value. This reload
+           value will be loaded in the IWDG counter each time the watchdog is
+           reloaded, then the IWDG will start counting down from this value.
+      (++) Wait for status flags to be reset.
+      (++) Depending on window parameter:
+        (+++) If Window Init parameter is same as Window register value,
+             nothing more is done but reload counter value in order to exit
+             function with exact time base.
+        (+++) Else modify Window register. This will automatically reload
+             watchdog counter.
+
+    (#) Then the application program must refresh the IWDG counter at regular
+        intervals during normal operation to prevent an MCU reset, using
+        HAL_IWDG_Refresh() function.
+
+     *** IWDG HAL driver macros list ***
+     ====================================
+     [..]
+       Below the list of most used macros in IWDG HAL driver:
+      (+) __HAL_IWDG_START: Enable the IWDG peripheral
+      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
+          the reload register
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+/** @addtogroup IWDG
+  * @brief IWDG HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Defines IWDG Private Defines
+  * @{
+  */
+/* Status register needs up to 5 LSI clock periods divided by the clock
+   prescaler to be updated. The number of LSI clock periods is upper-rounded to
+   6 for the timeout value calculation.
+   The timeout value is also calculated using the highest prescaler (256) and
+   the LSI_VALUE constant. The value of this constant can be changed by the user
+   to take into account possible LSI clock period variations.
+   The timeout value is multiplied by 1000 to be converted in milliseconds. */
+#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup IWDG_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup IWDG_Exported_Functions_Group1
+  *  @brief    Initialization and Start functions.
+  *
+@verbatim
+ ===============================================================================
+          ##### Initialization and Start functions #####
+ ===============================================================================
+ [..]  This section provides functions allowing to:
+      (+) Initialize the IWDG according to the specified parameters in the
+          IWDG_InitTypeDef of associated handle.
+      (+) Manage Window option.
+      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
+          is reloaded in order to exit function with correct time base.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the IWDG according to the specified parameters in the
+  *         IWDG_InitTypeDef and start watchdog. Before exiting function,
+  *         watchdog is refreshed in order to have correct time base.
+  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified IWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
+{
+  uint32_t tickstart;
+
+  /* Check the IWDG handle allocation */
+  if (hiwdg == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
+  assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
+  assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
+  assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
+
+  /* Enable IWDG. LSI is turned on automatically */
+  __HAL_IWDG_START(hiwdg);
+
+  /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
+  0x5555 in KR */
+  IWDG_ENABLE_WRITE_ACCESS(hiwdg);
+
+  /* Write to IWDG registers the Prescaler & Reload values to work with */
+  hiwdg->Instance->PR = hiwdg->Init.Prescaler;
+  hiwdg->Instance->RLR = hiwdg->Init.Reload;
+
+  /* Check pending flag, if previous update not done, return timeout */
+  tickstart = HAL_GetTick();
+
+  /* Wait for register to be updated */
+  while (hiwdg->Instance->SR != 0x00u)
+  {
+    if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* If window parameter is different than current value, modify window
+  register */
+  if (hiwdg->Instance->WINR != hiwdg->Init.Window)
+  {
+    /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
+    even if window feature is disabled, Watchdog will be reloaded by writing
+    windows register */
+    hiwdg->Instance->WINR = hiwdg->Init.Window;
+  }
+  else
+  {
+    /* Reload IWDG counter with value defined in the reload register */
+    __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup IWDG_Exported_Functions_Group2
+  *  @brief   IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+ [..]  This section provides functions allowing to:
+      (+) Refresh the IWDG.
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Refresh the IWDG.
+  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified IWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
+{
+  /* Reload IWDG counter with value defined in the reload register */
+  __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_IWDG_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c

@@ -0,0 +1,545 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_pwr.c
+  * @author  MCD Application Team
+  * @brief   PWR HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Power Controller (PWR) peripheral:
+  *           + Initialization/de-initialization functions
+  *           + Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup PWR_Private_Defines PWR Private Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_Exported_Functions  PWR Exported Functions
+  * @{
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group1  Initialization and de-initialization functions
+  * @brief  Initialization and de-initialization functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitialize the HAL PWR peripheral registers to their default reset
+            values.
+  * @retval None
+  */
+void HAL_PWR_DeInit(void)
+{
+  __HAL_RCC_PWR_FORCE_RESET();
+  __HAL_RCC_PWR_RELEASE_RESET();
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group2  Peripheral Control functions
+  *  @brief Low Power modes configuration functions
+  *
+@verbatim
+
+ ===============================================================================
+                 ##### Peripheral Control functions #####
+ ===============================================================================
+
+    [..]
+    *** WakeUp pin configuration ***
+    ================================
+    [..]
+      (+) WakeUp pins are used to wakeup the system from Standby mode or
+          Shutdown mode. WakeUp pins polarity can be set to configure event
+          detection on high level (rising edge) or low level (falling edge).
+
+    *** Low Power mode configuration ***
+    =====================================
+    [..]
+      The devices feature 7 low-power modes:
+      (+) Low-power run mode: core and peripherals are running at low frequency.
+          Regulator is in low power mode.
+      (+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running,
+          regulator is main mode.
+      (+) Low-power Sleep mode: Cortex-M0+ core stopped, peripherals kept running
+          and regulator in low power mode.
+      (+) Stop 0 mode: all clocks are stopped except LSI and LSE, regulator is
+           main mode.
+      (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator
+          off, low power regulator on.
+      (+) Standby mode: all clocks are stopped except LSI and LSE, regulator is
+          disable.
+      (+) Shutdown mode: all clocks are stopped except LSE, regulator is
+          disable.
+
+   *** Low-power run mode ***
+   ==========================
+    [..]
+      (+) Entry: (from main run mode)
+          (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after
+               having decreased the system clock below 2 MHz.
+      (+) Exit:
+          (++) clear LPR bit then wait for REGLPF bit to be reset with
+               HAL_PWREx_DisableLowPowerRunMode() API. Only then can the
+               system clock frequency be increased above 2 MHz.
+
+   *** Sleep mode / Low-power sleep mode ***
+   =========================================
+    [..]
+      (+) Entry:
+          The Sleep & Low-power Sleep modes are entered through
+          HAL_PWR_EnterSLEEPMode() API specifying whether or not the regulator
+          is forced to low-power mode and if exit is interrupt or event
+          triggered.
+          (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
+          (++) PWR_LOWPOWERREGULATOR_ON: Low-power Sleep mode (regulator in low
+               power mode). In this case, the system clock frequency must have
+               been decreased below 2 MHz beforehand.
+          (++) PWR_SLEEPENTRY_WFI: Core enters sleep mode with WFI instruction
+          (++) PWR_SLEEPENTRY_WFE: Core enters sleep mode with WFE instruction
+      (+) WFI Exit:
+        (++) Any interrupt enabled in nested vectored interrupt controller (NVIC)
+      (+) WFE Exit:
+        (++) Any wakeup event if cortex is configured with SEVONPEND = 0
+        (++) Interrupt even when disabled in NVIC if cortex is configured with
+             SEVONPEND = 1
+    [..]  When exiting the Low-power Sleep mode by issuing an interrupt or a wakeup event,
+          the MCU is in Low-power Run mode.
+
+   *** Stop 0 & Stop 1 modes ***
+   =============================
+    [..]
+      (+) Entry:
+          The Stop modes are entered through the following APIs:
+          (++) HAL_PWR_EnterSTOPMode() with following settings:
+              (+++) PWR_MAINREGULATOR_ON to enter STOP0 mode.
+              (+++) PWR_LOWPOWERREGULATOR_ON to enter STOP1 mode.
+      (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
+          (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
+          (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
+      (+) WFI Exit:
+          (++) Any EXTI line (internal or external) configured in interrupt mode
+               with corresponding interrupt enable in NVIC
+      (+) WFE Exit:
+          (++) Any EXTI line (internal or external) configured in event mode if
+               cortex is configured with SEVONPEND = 0
+          (++) Any EXTI line configured in interrupt mode (even if the
+               corresponding EXTI Interrupt vector is disabled in the NVIC) if
+               cortex is configured with SEVONPEND = 0. The interrupt source can
+               be external interrupts or peripherals with wakeup capability.
+    [..]  When exiting Stop, the MCU is either in Run mode or in Low-power Run mode
+          depending on the LPR bit setting.
+
+   *** Standby mode ***
+   ====================
+    [..] In Standby mode, it is possible to keep backup SRAM content (defined as
+         full SRAM) keeping low power regulator on. This is achievable by setting
+         Ram retention bit calling HAL_PWREx_EnableSRAMRetention API. This increases
+         power consumption.
+         Its also possible to define I/O states using APIs:
+         HAL_PWREx_EnableGPIOPullUp, HAL_PWREx_EnableGPIOPullDown &
+         HAL_PWREx_EnablePullUpPullDownConfig
+      (+) Entry:
+          (++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API, by
+               setting SLEEPDEEP in Cortex control register.
+      (+) Exit:
+          (++) WKUP pin edge detection, RTC event (wakeup, alarm, timestamp),
+               tamper event (internal & external), LSE CSS detection, reset on
+               NRST pin, IWDG reset & BOR reset.
+    [..] Exiting Standby generates a power reset: Cortex is reset and execute
+         Reset handler vector, all registers in the Vcore domain are set to
+         their reset value. Registers outside the VCORE domain (RTC, WKUP, IWDG,
+         and Standby/Shutdown modes control) are not impacted.
+
+    *** Shutdown mode ***
+   ======================
+    [..]
+      In Shutdown mode,
+        voltage regulator is disabled, all clocks are off except LSE, RRS bit is
+        cleared. SRAM and registers contents are lost except for backup domain
+        registers.
+      (+) Entry:
+          (++) The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API,
+               by setting SLEEPDEEP in Cortex control register.
+      (+) Exit:
+          (++) WKUP pin edge detection, RTC event (wakeup, alarm, timestamp),
+               tamper event (internal & external), LSE CSS detection, reset on
+               NRST pin.
+    [..] Exiting Shutdown generates a brown out reset: Cortex is reset and execute
+         Reset handler vector, all registers are set to their reset value but ones
+         in backup domain.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable access to the backup domain
+  *         (RTC & TAMP registers, backup registers, RCC BDCR register).
+  * @note   After reset, the backup domain is protected against
+  *         possible unwanted write accesses. All RTC & TAMP registers (backup
+  *         registers included) and RCC BDCR register are concerned.
+  * @retval None
+  */
+void HAL_PWR_EnableBkUpAccess(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+
+/**
+  * @brief  Disable access to the backup domain
+  * @retval None
+  */
+void HAL_PWR_DisableBkUpAccess(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+  * @brief  Enable the WakeUp PINx functionality.
+  * @param  WakeUpPinPolarity Specifies which Wake-Up pin to enable.
+  *         This parameter can be one of the following legacy values which set
+  *         the default polarity i.e. detection on high level (rising edge):
+  *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3(*), 
+  *                     PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5(*),PWR_WAKEUP_PIN6
+  *         or one of the following value where the user can explicitly specify
+  *         the enabled pin and the chosen polarity:
+  *           @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
+  *           @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
+  *           @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW (*)
+  *           @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
+  *           @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW (*)
+  *           @arg @ref PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
+  * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
+  * @note (*) availability depends on devices
+  * @retval None
+  */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
+{
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
+
+  /* Specifies the Wake-Up pin polarity for the event detection
+    (rising or falling edge) */
+  MODIFY_REG(PWR->CR4, (PWR_CR4_WP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
+
+  /* Enable wake-up pin */
+  SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
+}
+
+
+/**
+  * @brief  Disable the WakeUp PINx functionality.
+  * @param  WakeUpPinx Specifies the Power Wake-Up pin to disable.
+  *         This parameter can be one of the following values:
+  *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2,PWR_WAKEUP_PIN3(*),
+  *                     PWR_WAKEUP_PIN4,PWR_WAKEUP_PIN5(*),PWR_WAKEUP_PIN6
+  * @note (*) availability depends on devices
+  * @retval None
+  */
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
+{
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+
+  CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
+}
+
+
+/**
+  * @brief  Enter Sleep or Low-power Sleep mode.
+  * @note   In Sleep/Low-power Sleep mode, all I/O pins keep the same state as
+  *         in Run mode.
+  * @param  Regulator Specifies the regulator state in Sleep/Low-power Sleep
+  *         mode. This parameter can be one of the following values:
+  *           @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
+  *           @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator
+  *                     in low-power mode)
+  * @note   Low-power Sleep mode is entered from Low-power Run mode only. In
+  *         case Regulator parameter is set to Low Power but MCU is in Run mode,
+  *         we will first enter in Low-power Run mode. Therefore, user should
+  *         take care that HCLK frequency is less than 2 MHz.
+  * @note   When exiting Low-power Sleep mode, the MCU is in Low-power Run mode.
+  *         To switch back to Run mode, user must call
+  *         HAL_PWREx_DisableLowPowerRunMode() API.
+  * @param  SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE
+  *         instruction. This parameter can be one of the following values:
+  *           @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep
+  *                     mode with WFI instruction
+  *           @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep
+  *                     mode with WFE instruction
+  * @note   When WFI entry is used, tick interrupt have to be disabled if not
+  *         desired as the interrupt wake up source.
+  * @retval None
+  */
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(Regulator));
+  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+
+  /* Set Regulator parameter */
+  if(Regulator != PWR_MAINREGULATOR_ON)
+  {
+    /* If in run mode, first move to low-power run mode.
+       The system clock frequency must be below 2 MHz at this point. */
+    if((PWR->SR2 & PWR_SR2_REGLPF) == 0x00u)
+    {
+      HAL_PWREx_EnableLowPowerRunMode();
+    }
+  }
+  else
+  {
+    /* If in low-power run mode at this point, exit it */
+    if((PWR->SR2 & PWR_SR2_REGLPF) != 0x00u)
+    {
+      if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
+      {
+        return ;
+      }
+    }
+  }
+
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+  /* Select SLEEP mode entry -------------------------------------------------*/
+  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+}
+
+
+/**
+  * @brief  Enter Stop mode
+  * @note   This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with
+  *         legacy code running on devices where only "Stop mode" is mentioned
+  *         with main or low power regulator ON.
+  * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
+  * @note   All clocks in the VCORE domain are stopped; the PLL, the HSI and the
+  *         HSE oscillators are disabled. Some peripherals with the wakeup
+  *         capability can switch on the HSI to receive a frame, and switch off
+  *         the HSI after receiving the frame if it is not a wakeup frame.
+  *         SRAM and register contents are preserved.
+  *         The BOR is available.
+  *         The voltage regulator can be configured either in normal (Stop 0) or
+  *         low-power mode (Stop 1).
+  * @note   When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a
+  *         wakeup event, the HSI RC oscillator is selected as system clock
+  * @note   When the voltage regulator operates in low power mode (Stop 1),
+  *         an additional startup delay is incurred when waking up. By keeping
+  *         the internal regulator ON during Stop mode (Stop 0), the consumption
+  *         is higher although the startup time is reduced.
+  * @param  Regulator Specifies the regulator state in Stop mode
+  *         This parameter can be one of the following values:
+  *            @arg @ref PWR_MAINREGULATOR_ON  Stop 0 mode (main regulator ON)
+  *            @arg @ref PWR_LOWPOWERREGULATOR_ON  Stop 1 mode (low power
+  *                                                regulator ON)
+  * @param  STOPEntry Specifies Stop 0 or Stop 1 mode is entered with WFI or
+  *         WFE instruction. This parameter can be one of the following values:
+  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop 0 or Stop 1 mode with WFI
+  *                                         instruction.
+  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop 0 or Stop 1 mode with WFE
+  *                                         instruction.
+  * @retval None
+  */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+  if (Regulator != PWR_MAINREGULATOR_ON)
+  {
+    /* Stop mode with Low-Power Regulator */
+    MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP1);
+  }
+  else
+  {
+    /* Stop mode with Main Regulator */
+    MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP0);
+  }
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+  /* Select Stop mode entry --------------------------------------------------*/
+  if(STOPEntry == PWR_STOPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+
+/**
+  * @brief  Enter Standby mode.
+  * @note   In Standby mode, the PLL, the HSI and the HSE oscillators are
+  *         switched off. The voltage regulator is disabled. SRAM and register
+  *         contents are lost except for registers in the Backup domain and
+  *         Standby circuitry. BOR is available.
+  * @note   The I/Os can be configured either with a pull-up or pull-down or can
+  *         be kept in analog state.
+  *         HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown()
+  *         respectively enable Pull Up and PullDown state.
+  *         HAL_PWREx_DisableGPIOPullUp() & HAL_PWREx_DisableGPIOPullDown()
+  *         disable the same. These states are effective in Standby mode only if
+  *         APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
+  * @note   Sram content can be kept setting RRS through HAL_PWREx_EnableSRAMRetention()
+  * @retval None
+  */
+void HAL_PWR_EnterSTANDBYMode(void)
+{
+  /* Set Stand-by mode */
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STANDBY);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+/* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+
+/**
+  * @brief  Enable Sleep-On-Exit Cortex feature
+  * @note   Set SLEEPONEXIT bit of SCR register. When this bit is set, the
+  *         processor enters SLEEP or DEEPSLEEP mode when an interruption
+  *         handling is over returning to thread mode. Setting this bit is
+  *         useful when the processor is expected to run only on interruptions
+  *         handling.
+  * @retval None
+  */
+void HAL_PWR_EnableSleepOnExit(void)
+{
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+/**
+  * @brief  Disable Sleep-On-Exit Cortex feature
+  * @note   Clear SLEEPONEXIT bit of SCR register. When this bit is set, the
+  *         processor enters SLEEP or DEEPSLEEP mode when an interruption
+  *         handling is over.
+  * @retval None
+  */
+void HAL_PWR_DisableSleepOnExit(void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+/**
+  * @brief  Enable Cortex Sev On Pending feature.
+  * @note   Set SEVONPEND bit of SCR register. When this bit is set, enabled
+  *         events and all interrupts, including disabled ones can wakeup
+  *         processor from WFE.
+  * @retval None
+  */
+void HAL_PWR_EnableSEVOnPend(void)
+{
+  /* Set SEVONPEND bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+
+/**
+  * @brief  Disable Cortex Sev On Pending feature.
+  * @note   Clear SEVONPEND bit of SCR register. When this bit is clear, only
+  *         enable interrupts or events can wakeup processor from WFE
+  * @retval None
+  */
+void HAL_PWR_DisableSEVOnPend(void)
+{
+  /* Clear SEVONPEND bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c

@@ -0,0 +1,369 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_ll_dma.c
+  * @author  MCD Application Team
+  * @brief   DMA LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_ll_dma.h"
+#include "stm32g0xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32G0xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup DMA_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
+                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
+                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
+
+#define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
+                                                 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
+
+#define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
+                                                 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
+
+#define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
+                                                 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
+
+#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
+                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
+                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
+
+#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
+                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
+                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
+
+#define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
+
+#define IS_LL_DMA_PERIPHREQUEST(__VALUE__)      ((__VALUE__) <= LL_DMAMUX_MAX_REQ)
+
+#define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
+                                                 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
+                                                 ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
+                                                 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
+
+#if defined(DMA2)
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
+                                                            (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
+                                                            (((INSTANCE) == DMA2) && \
+                                                            (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_5))))
+#else /* DMA1 */
+#if   defined(DMA1_Channel7)
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
+                                                            (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_7))))
+#else
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
+                                                            (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+                                                             ((CHANNEL) == LL_DMA_CHANNEL_5))))
+#endif
+#endif /* DMA2 */
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the DMA registers to their default reset values.
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  *         @arg @ref LL_DMA_CHANNEL_ALL
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DMA registers are de-initialized
+  *          - ERROR: DMA registers are not de-initialized
+  */
+ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the DMA Instance DMAx and Channel parameters*/
+  assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));
+
+  if (Channel == LL_DMA_CHANNEL_ALL)
+  {
+    if (DMAx == DMA1)
+    {
+      /* Force reset of DMA clock */
+      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
+
+      /* Release reset of DMA clock */
+      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
+    }
+#if defined(DMA2)
+    else if (DMAx == DMA2)
+    {
+      /* Force reset of DMA clock */
+      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
+
+      /* Release reset of DMA clock */
+      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
+    }
+#endif
+    else
+    {
+      status = ERROR;
+    }
+  }
+  else
+  {
+    DMA_Channel_TypeDef *tmp;
+
+    tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
+
+    /* Disable the selected DMAx_Channely */
+    CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
+
+    /* Reset DMAx_Channely control register */
+    WRITE_REG(tmp->CCR, 0U);
+
+    /* Reset DMAx_Channely remaining bytes register */
+    WRITE_REG(tmp->CNDTR, 0U);
+
+    /* Reset DMAx_Channely peripheral address register */
+    WRITE_REG(tmp->CPAR, 0U);
+
+    /* Reset DMAx_Channely memory address register */
+    WRITE_REG(tmp->CMAR, 0U);
+
+    /* Reset Request register field for DMAx Channel */
+    LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQ_MEM2MEM);
+
+    if (Channel == LL_DMA_CHANNEL_1)
+    {
+      /* Reset interrupt pending bits for DMAx Channel1 */
+      LL_DMA_ClearFlag_GI1(DMAx);
+    }
+    else if (Channel == LL_DMA_CHANNEL_2)
+    {
+      /* Reset interrupt pending bits for DMAx Channel2 */
+      LL_DMA_ClearFlag_GI2(DMAx);
+    }
+    else if (Channel == LL_DMA_CHANNEL_3)
+    {
+      /* Reset interrupt pending bits for DMAx Channel3 */
+      LL_DMA_ClearFlag_GI3(DMAx);
+    }
+    else if (Channel == LL_DMA_CHANNEL_4)
+    {
+      /* Reset interrupt pending bits for DMAx Channel4 */
+      LL_DMA_ClearFlag_GI4(DMAx);
+    }
+    else if (Channel == LL_DMA_CHANNEL_5)
+    {
+      /* Reset interrupt pending bits for DMAx Channel5 */
+      LL_DMA_ClearFlag_GI5(DMAx);
+    }
+#if defined(DMA1_Channel6)
+    else if (Channel == LL_DMA_CHANNEL_6)
+    {
+      /* Reset interrupt pending bits for DMAx Channel6 */
+      LL_DMA_ClearFlag_GI6(DMAx);
+    }
+#endif
+#if defined(DMA1_Channel7)
+    else if (Channel == LL_DMA_CHANNEL_7)
+    {
+      /* Reset interrupt pending bits for DMAx Channel7 */
+      LL_DMA_ClearFlag_GI7(DMAx);
+    }
+#endif
+    else
+    {
+      status = ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
+  * @note   To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
+  *         @arg @ref __LL_DMA_GET_INSTANCE
+  *         @arg @ref __LL_DMA_GET_CHANNEL
+  * @param  DMAx DMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DMA registers are initialized
+  *          - ERROR: Not applicable
+  */
+ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+  /* Check the DMA Instance DMAx and Channel parameters*/
+  assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
+
+  /* Check the DMA parameters from DMA_InitStruct */
+  assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
+  assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
+  assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
+  assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
+  assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
+  assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
+  assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
+  assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
+  assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
+
+  /*---------------------------- DMAx CCR Configuration ------------------------
+   * Configure DMAx_Channely: data transfer direction, data transfer mode,
+   *                          peripheral and memory increment mode,
+   *                          data size alignment and  priority level with parameters :
+   * - Direction:      DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
+   * - Mode:           DMA_CCR_CIRC bit
+   * - PeriphOrM2MSrcIncMode:  DMA_CCR_PINC bit
+   * - MemoryOrM2MDstIncMode:  DMA_CCR_MINC bit
+   * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
+   * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
+   * - Priority:               DMA_CCR_PL[1:0] bits
+   */
+  LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction              | \
+                        DMA_InitStruct->Mode                   | \
+                        DMA_InitStruct->PeriphOrM2MSrcIncMode  | \
+                        DMA_InitStruct->MemoryOrM2MDstIncMode  | \
+                        DMA_InitStruct->PeriphOrM2MSrcDataSize | \
+                        DMA_InitStruct->MemoryOrM2MDstDataSize | \
+                        DMA_InitStruct->Priority);
+
+  /*-------------------------- DMAx CMAR Configuration -------------------------
+   * Configure the memory or destination base address with parameter :
+   * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
+   */
+  LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
+
+  /*-------------------------- DMAx CPAR Configuration -------------------------
+   * Configure the peripheral or source base address with parameter :
+   * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
+   */
+  LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
+
+  /*--------------------------- DMAx CNDTR Configuration -----------------------
+   * Configure the peripheral base address with parameter :
+   * - NbData: DMA_CNDTR_NDT[15:0] bits
+   */
+  LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
+
+  /*--------------------------- DMAMUXx CCR Configuration ----------------------
+   * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter :
+   * - PeriphRequest: DMA_CxCR[7:0] bits
+   */
+  LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
+  * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
+  * @retval None
+  */
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+  /* Set DMA_InitStruct fields to default values */
+  DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
+  DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
+  DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
+  DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
+  DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
+  DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
+  DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
+  DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
+  DMA_InitStruct->NbData                 = 0x00000000U;
+  DMA_InitStruct->PeriphRequest          = LL_DMAMUX_REQ_MEM2MEM;
+  DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Makefile

@@ -5,29 +5,52 @@ OPT = -O0
 
 BUILD_DIR = build
 
-SRC_DIRS := $(shell find src -type d)
+C_SOURCES =  \
-CC_SOURCES = $(foreach folder, $(SRC_DIRS), $(wildcard $(folder)/*.cc))
+Core/Src/main.c \
-C_SOURCES = $(foreach folder, $(SRC_DIRS), $(wildcard $(folder)/*.c))
+Core/Src/stm32g0xx_it.c \
-ASM_SOURCES = $(foreach folder, $(SRC_DIRS), $(wildcard $(folder)/*.s))
+Core/Src/stm32g0xx_hal_msp.c \
+Core/Src/system_stm32g0xx.c \
+Core/Src/syscalls.c \
+Core/Src/sysmem.c \
+Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c \
+Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c \
+Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c \
+Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c \
+Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c \
+Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c \
+Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c \
+Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c \
+Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c \
+Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c \
+Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c \
+Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c
+
+ASM_SOURCES = \
+Core/Startup/startup_stm32g031y8yx.s
 
 PREFIX = arm-none-eabi-
 CC = $(PREFIX)gcc
-CXX = $(PREFIX)g++
 AS = $(PREFIX)gcc -x assembler-with-cpp
 CP = $(PREFIX)objcopy
 SZ = $(PREFIX)size
 
-HEX = $(CP) -O ihex
-BIN = $(CP) -O binary -S
- 
 CPU = -mcpu=cortex-m0plus
 MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
 
-C_DEFS = -DSTM32G031xx
+C_DEFS = \
-LDSCRIPT = src/platform/stm32g0xx/STM32G031Y8YX_FLASH.ld
+-DUSE_HAL_DRIVER \
+-DSTM32G071xx
+
+C_INCLUDES = \
+-ICore/Inc \
+-IDrivers/STM32G0xx_HAL_Driver/Inc \
+-IDrivers/STM32G0xx_HAL_Driver/Inc/Legacy \
+-IDrivers/CMSIS/Device/ST/STM32G0xx/Include \
+-IDrivers/CMSIS/Include
+
 
 ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
-CFLAGS = $(MCU) $(C_DEFS) $(addprefix -I,$(SRC_DIRS)) $(OPT) -Wall -fdata-sections -ffunction-sections
+CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
 
 ifeq ($(DEBUG), 1)
 CFLAGS += -ggdb3
@@ -35,44 +58,34 @@ endif
 
 CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
 
+LDSCRIPT = STM32G031Y8YX_Flash.ld
+
 LIBS = -lc -lm -lnosys
 LIBDIR =
 LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
 
-all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
+all: $(BUILD_DIR)/$(TARGET).elf
 
-OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(CC_SOURCES:.cc=.o)))
+OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o)))
-vpath %.cc $(sort $(dir $(CC_SOURCES)))
-
-OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o)))
 vpath %.c $(sort $(dir $(C_SOURCES)))
 
 OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o)))
 vpath %.s $(sort $(dir $(ASM_SOURCES)))
 
-$(BUILD_DIR)/%.o: %.cc Makefile | $(BUILD_DIR) 
-	$(CXX) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.cc=.lst)) $< -o $@
-
 $(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) 
 	$(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@
 
 $(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)
 	$(AS) -c $(CFLAGS) $< -o $@
 
-$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) | Makefile
+$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile
-	$(CXX) $(OBJECTS) $(LDFLAGS) -o $@
+	$(CC) $(OBJECTS) $(LDFLAGS) -o $@
 	$(SZ) $@
 
-$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
-	$(HEX) $< $@
-
-$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
-	$(BIN) $< $@
-
 $(BUILD_DIR):
 	mkdir $@
 
 clean:
-	-rm -fR $(BUILD_DIR)
+	-rm -rf $(BUILD_DIR)
 
 -include $(wildcard $(BUILD_DIR)/*.d)

openocd.cfg

@@ -1,2 +0,0 @@
-source [find interface/stlink.cfg]
-source [find target/stm32g0x.cfg]

src/arch/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h

@@ -1,49 +0,0 @@
-#ifndef STM32G0xx_H
-#define STM32G0xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define __STM32G0_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
-#define __STM32G0_CMSIS_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
-#define __STM32G0_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
-#define __STM32G0_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
-#define __STM32G0_CMSIS_VERSION        ((__STM32G0_CMSIS_VERSION_MAIN << 24)\
-                                       |(__STM32G0_CMSIS_VERSION_SUB1 << 16)\
-                                       |(__STM32G0_CMSIS_VERSION_SUB2 << 8 )\
-                                       |(__STM32G0_CMSIS_VERSION_RC))
-
-#if defined(STM32G0B1xx)
-  #include "stm32g0b1xx.h"
-#elif defined(STM32G0C1xx)
-  #include "stm32g0c1xx.h"
-#elif defined(STM32G0B0xx)
-  #include "stm32g0b0xx.h"
-#elif defined(STM32G071xx)
-  #include "stm32g071xx.h"
-#elif defined(STM32G081xx)
-  #include "stm32g081xx.h"
-#elif defined(STM32G070xx)
-  #include "stm32g070xx.h"
-#elif defined(STM32G031xx)
-  #include "stm32g031xx.h"
-#elif defined(STM32G041xx)
-  #include "stm32g041xx.h"
-#elif defined(STM32G030xx)
-  #include "stm32g030xx.h"
-#elif defined(STM32G051xx)
-  #include "stm32g051xx.h"
-#elif defined(STM32G061xx)
-  #include "stm32g061xx.h"
-#elif defined(STM32G050xx)
-  #include "stm32g050xx.h"
-#else
- #error "Please select first the target STM32G0xx device used in your application (in stm32g0xx.h file)"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

src/delay.h

@@ -1,8 +0,0 @@
-#ifndef __CORE_DELAY_H__
-#define __CORE_DELAY_H__
-
-#include <stdint.h>
-
-void delay_ms(uint32_t);
-
-#endif

src/main.cc

@@ -1,29 +0,0 @@
-#include <cstring>
-#include <cstdint>
-#include <cstdio>
-
-#include "delay.h"
-#include "platform/stm32g0xx/Gpio.h"
-#include "platform/stm32g0xx/Uart.h"
-
-
-using namespace perinet::platform::stm32g0xx;
-
-Uart uart1(Uart::UartDevice::UART_1, 115200);
-Uart uart2(Uart::UartDevice::UART_2, 115200);
-
-int main(void)
-{
-    char tx_buf[] = "\r\rProgram: UART bridge\r\n\n Receive on uart2 and transmit it on uart 1\r\n";
-    uint8_t rec;
-    uart1.sync_send((const uint8_t *)tx_buf, strlen(tx_buf));
-
-    while(true) {
-        if(uart2.sync_receive(&rec)) {
-            uart1.sync_send(&rec, 1);
-        }
-        if(uart1.sync_receive(&rec)) {
-            uart2.sync_send(&rec, 1);
-        }
-    }
-}

src/platform/stm32g0xx/Gpio.cc

@@ -1,86 +0,0 @@
-#include "stm32g0xx.h"
-
-#include "platform/stm32g0xx/Gpio.h"
-
-using namespace perinet::platform::stm32g0xx;
-
-Gpio::Gpio(Port port, uint32_t pin, Mode mode, Pullup pullup, AlternateFunction alternate_function)
-{
-    switch(port) {
-        case Port::PORT_A:
-            this->port = GPIOA;
-            RCC->IOPENR |= RCC_IOPENR_GPIOAEN;  // Enable PORT A clock
-            break;
-        case Port::PORT_B:
-            this->port = GPIOB;
-            RCC->IOPENR |= RCC_IOPENR_GPIOBEN;  // Enable PORT B clock
-            break;
-        case Port::PORT_C:
-            this->port = GPIOC;
-            RCC->IOPENR |= RCC_IOPENR_GPIOCEN;  // Enable PORT C clock
-            break;
-        case Port::PORT_D:
-            this->port = GPIOD;
-            RCC->IOPENR |= RCC_IOPENR_GPIODEN;  // Enable PORT D clock
-            break;
-        case Port::PORT_F:
-            this->port = GPIOF;
-            RCC->IOPENR |= RCC_IOPENR_GPIOFEN;  // Enable PORT F clock
-            break;
-    }
-    this->pin = pin;
-
-    /* Configure the IO Speed */
-    volatile uint32_t temp = this->port->OSPEEDR;
-    temp &= ~(GPIO_OSPEEDR_OSPEED0 << (this->pin * 2u));
-    temp |= (static_cast<uint32_t>(Speed::FREQ_HIGH) << (this->pin * 2u));
-    this->port->OSPEEDR = temp;
-
-    /* Configure the IO Output Type */
-    temp = this->port->OTYPER;
-    temp &= ~(GPIO_OTYPER_OT0 << this->pin);
-    temp |= (((static_cast<uint32_t>(mode) & 0x00000010u) >> 4u) << this->pin);
-    this->port->OTYPER = temp;
-
-    /* Activate the Pull-up or Pull down resistor for the current IO */
-    temp = this->port->PUPDR;
-    temp &= ~(GPIO_PUPDR_PUPD0 << (this->pin * 2u));
-    temp |= ((static_cast<uint32_t>(pullup)) << (this->pin * 2u));
-    this->port->PUPDR = temp;
-
-    /* Configure Alternate function mapped with the current IO */
-    temp = this->port->AFR[this->pin >> 3u];
-    temp &= ~(0xFu << ((this->pin & 0x07u) * 4u));
-    temp |= ((static_cast<uint32_t>(alternate_function)) << ((this->pin & 0x07u) * 4u));
-    this->port->AFR[this->pin >> 3u] = temp;
-
-    /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
-    temp = this->port->MODER;
-    temp &= ~(GPIO_MODER_MODE0 << (this->pin * 2u));
-    temp |= ((static_cast<uint32_t>(mode) & 0x00000003u) << (this->pin * 2u));
-    this->port->MODER = temp;
-}
-
-void Gpio::set()
-{
-    this->port->BSRR = 1 << this->pin;
-}
-
-void Gpio::clear()
-{
-    this->port->BRR = 1 << this->pin;
-}
-
-void Gpio::toggle()
-{
-  // get current Output Data Register value
-  volatile uint32_t odr = this->port->ODR;
-
-  // Set selected pins that were at low level, and reset ones that were high
-  this->port->BSRR = ((odr & (1 << this->pin)) << 16) | (~odr & (1 << this->pin));
-}
-
-uint32_t Gpio::get()
-{
-    return (this->port->IDR & (1 << this->pin)) >> this->pin;
-}

src/platform/stm32g0xx/Gpio.h

@@ -1,76 +0,0 @@
-#ifndef __PLATFORM_STM32G0XX_GPIO_H__
-#define __PLATFORM_STM32G0XX_GPIO_H__
-
-#include <cstdint>
-
-#include "stm32g0xx.h"
-
-namespace perinet::platform::stm32g0xx {
-
-class Gpio
-{
-public:
-    enum class Port
-    {
-        PORT_A,
-        PORT_B,
-        PORT_C,
-        PORT_D,
-        PORT_F
-    };
-
-    enum class Speed
-    {
-        FREQ_LOW = 0,       // Low speed
-        FREQ_MEDIUM,        // Medium speed
-        FREQ_HIGH,          // High speed
-        FREQ_VERY_HIGH      // Very high speed
-    };
-
-    enum class Mode
-    {
-        MODE_INPUT      = 0x00, // Input Floating Mode
-        MODE_OUTPUT_PP  = 0x01, // Output Push Pull Mode
-        MODE_AF_PP      = 0x02, // Alternate Function Push Pull Mode
-        MODE_ANALOG     = 0x03, // Analog Mode
-        MODE_OUTPUT_OD  = 0x11, // Output Open Drain Mode
-        MODE_AF_OD      = 0x12, // Alternate Function Open Drain Mode
-    };
-
-    enum class Pullup
-    {
-        NOPULL = 0,    // No Pull-up or Pull-down activation
-        PULLUP,        // Pull-up activation
-        PULLDOWN       // Pull-down activation
-    };
-
-    enum class AlternateFunction
-    {
-        ALTERNATE_FUNCTION_0 = 0,
-        ALTERNATE_FUNCTION_1,
-        ALTERNATE_FUNCTION_2,
-        ALTERNATE_FUNCTION_3,
-        ALTERNATE_FUNCTION_4,
-        ALTERNATE_FUNCTION_5,
-        ALTERNATE_FUNCTION_6,
-        ALTERNATE_FUNCTION_7,
-        ALTERNATE_FUNCTION_8,
-        ALTERNATE_FUNCTION_9,
-        ALTERNATE_FUNCTION_10,
-    };
-
-    Gpio(Port, uint32_t, Mode=Mode::MODE_INPUT, Pullup=Pullup::NOPULL, AlternateFunction=AlternateFunction::ALTERNATE_FUNCTION_0);
-
-    uint32_t get();
-    void set();
-    void clear();
-    void toggle();
-
-private:
-    GPIO_TypeDef *port;
-    uint32_t pin;
-};
-
-}
-
-#endif

src/platform/stm32g0xx/IndependentWatchdog.cc

@@ -1,45 +0,0 @@
-#include "platform/stm32g0xx/IndependentWatchdog.h"
-
-using namespace perinet::platform::stm32g0xx;
-
-#define IWDG_KEY_RELOAD                 0x0000AAAAu  /*!< IWDG Reload Counter Enable   */
-#define IWDG_KEY_ENABLE                 0x0000CCCCu  /*!< IWDG Peripheral Enable       */
-#define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555u  /*!< IWDG KR Write Access Enable  */
-
-IndependentWatchdog::IndependentWatchdog(uint32_t window, uint32_t reload)
-    : window(window)
-    , reload(reload)
-{
-}
-
-void IndependentWatchdog::enable()
-{
-    // Enable IWDG. LSI is turned on automatically
-    IWDG->KR = IWDG_KEY_ENABLE;
-
-    // Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing 0x5555 in KR
-    IWDG->KR = IWDG_KEY_WRITE_ACCESS_ENABLE;
-
-    // Write to IWDG registers the Prescaler & Reload values to work with
-    IWDG->PR = 0;               // IWDG prescaler set to 4
-    IWDG->RLR = this->reload;
-
-    // If window parameter is different than current value, modify window register
-    if (IWDG->WINR != this->window) {
-        // Write to IWDG WINR the IWDG_Window value to compare with. In any case,
-        // even if window feature is disabled, Watchdog will be reloaded by writing
-        // windows register
-        IWDG->WINR = this->window;
-    }
-    else {
-        // Reload IWDG counter with value defined in the reload register
-        IWDG->KR = IWDG_KEY_RELOAD;
-    }
-
-}
-
-void IndependentWatchdog::trigger()
-{
-    // Reload IWDG counter with value defined in the reload register
-    IWDG->KR = IWDG_KEY_RELOAD;
-}

src/platform/stm32g0xx/IndependentWatchdog.h

@@ -1,24 +0,0 @@
-#ifndef __PLATFORM_STM32G0XX_INDEPENDENTWATCHDOG_H__
-#define __PLATFORM_STM32G0XX_INDEPENDENTWATCHDOG_H__
-
-#include <cstdint>
-
-#include "stm32g0xx.h"
-
-namespace perinet::platform::stm32g0xx {
-
-class IndependentWatchdog
-{
-public:
-    IndependentWatchdog(uint32_t, uint32_t);
-    void enable();
-    void trigger();
-
-private:
-    uint32_t window;
-    uint32_t reload;
-};
-
-}
-
-#endif

src/platform/stm32g0xx/Uart.cc

@@ -1,84 +0,0 @@
-#include "platform/stm32g0xx/Gpio.h"
-#include "platform/stm32g0xx/Uart.h"
-
-using namespace perinet::platform::stm32g0xx;
-
-Uart::Uart(UartDevice device, uint32_t baud_rate)
-{
-    uint32_t tx_pin = 2;
-    uint32_t rx_pin = 15;
-    Gpio::Port port = Gpio::Port::PORT_A;
-    Gpio::AlternateFunction alt_func = Gpio::AlternateFunction::ALTERNATE_FUNCTION_0;
-    switch(device) {
-        case UartDevice::UART_1:
-            uart = USART1;
-            RCC->APBENR2 |= RCC_APBENR2_USART1EN;
-            tx_pin = 6;
-            rx_pin = 7;
-            port = Gpio::Port::PORT_B;
-            break;
-
-        case UartDevice::UART_2:
-            uart = USART2;
-            RCC->APBENR1 |= RCC_APBENR1_USART2EN;
-            alt_func = Gpio::AlternateFunction::ALTERNATE_FUNCTION_1;
-            break;
-    }
-
-    Gpio tx_gpio(port, tx_pin, Gpio::Mode::MODE_AF_PP, Gpio::Pullup::PULLUP, alt_func);
-    Gpio rx_gpio(port, rx_pin, Gpio::Mode::MODE_AF_PP, Gpio::Pullup::PULLUP, alt_func);
-
-    // Disable UART
-    uart->CR1 &= ~USART_CR1_UE;
-
-    // USART CR1 Configuration
-    uint32_t tmp = uart->CR1;
-    tmp &= ~((USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| USART_CR1_FIFOEN));
-    tmp |= (USART_CR1_TE | USART_CR1_RE);  // RX and TX mode
-    uart->CR1 = tmp;
-
-    // USART CR2 Configuration
-    tmp = uart->CR2;
-    tmp &= ~(USART_CR2_STOP);
-    uart->CR2 = tmp;
-
-    // USART CR3 Configuration
-
-    // USART PRESC Configuration
-
-    // USART BRR Configuration
-    tmp = ((64000000 + (baud_rate / 2)) / baud_rate);
-    uart->BRR = tmp;
-
-    // In asynchronous mode, the following bits must be kept cleared:
-    //   - LINEN and CLKEN bits in the USART_CR2 register,
-    //   - SCEN, HDSEL and IREN  bits in the USART_CR3 register.
-    uart->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
-    uart->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
-
-    // Enable UART
-    uart->CR1 |= USART_CR1_UE;
-}
-
-void Uart::sync_send(const uint8_t *buffer, uint32_t len)
-{
-    if (buffer == nullptr) {
-        return;
-    }
-
-    for (uint32_t i = 0; i < len; i++) {
-        // wait for tx not full
-        while ((uart->ISR & USART_ISR_TXE_TXFNF) == 0);
-        uart->TDR = buffer[i];
-    }
-}
-
-bool Uart::sync_receive(uint8_t* res)
-{
-        if((uart->ISR & USART_ISR_RXNE_RXFNE) == 0) {
-            return false;
-        }
-
-        *res = (uint8_t)(uart->RDR);
-        return true;
-}

src/platform/stm32g0xx/Uart.h

@@ -1,29 +0,0 @@
-#ifndef __PLATFORM_STM32G0XX_UART_H__
-#define __PLATFORM_STM32G0XX_UART_H__
-
-#include <cstdint>
-
-#include "stm32g0xx.h"
-
-namespace perinet::platform::stm32g0xx {
-
-class Uart
-{
-public:
-    enum class UartDevice
-    {
-        UART_1,
-        UART_2
-    };
-
-    Uart(UartDevice, uint32_t);
-    void sync_send(const uint8_t *, uint32_t);
-    bool sync_receive(uint8_t*);
-
-private:
-    USART_TypeDef   * uart;
-};
-
-}
-
-#endif

src/platform/stm32g0xx/low_level_interrupt.cc

@@ -1,42 +0,0 @@
-#include "delay.h"
-
-extern "C"
-{
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void SVC_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-}
-
-volatile uint32_t tick_ms;
-
-void NMI_Handler(void)
-{
-    while (1);
-}
-
-void HardFault_Handler(void)
-{
-    while (1);
-}
-
-void SVC_Handler(void)
-{
-}
-
-void PendSV_Handler(void)
-{
-}
-
-void SysTick_Handler(void)
-{
-    tick_ms++;
-}
-
-void delay_ms(uint32_t time_ms)
-{
-    uint32_t tickstart = tick_ms;
-
-    while ((tick_ms - tickstart) < time_ms);
-}

src/platform/stm32g0xx/system_stm32g0xx.c

@@ -1,217 +0,0 @@
-#include "stm32g0xx.h"
-
-#define SYS_TICK_PRIO   0
-
-#if !defined  (HSE_VALUE)
-#define HSE_VALUE    (8000000UL)    /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE  (16000000UL)   /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE   (32000UL)     /*!< Value of LSI in Hz*/
-#endif /* LSI_VALUE */
-
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE  (32768UL)      /*!< Value of LSE in Hz*/
-#endif /* LSE_VALUE */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0U /*!< Vector Table base offset field.
-                                   This value must be a multiple of 0x100. */
-/* The SystemCoreClock variable is updated in three ways:
-  1) by calling CMSIS function SystemCoreClockUpdate()
-  2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-  3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-	 Note: If you use this function to configure the system clock; then there
-		   is no need to call the 2 first functions listed above, since SystemCoreClock
-		   variable is updated automatically.
-*/
-uint32_t SystemCoreClock = 16000000UL;
-
-const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};
-const uint32_t APBPrescTable[8UL] =  {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
-
-
-void SystemCoreClockUpdate(void)
-{
-    uint32_t tmp;
-    uint32_t pllvco;
-    uint32_t pllr;
-    uint32_t pllsource;
-    uint32_t pllm;
-    uint32_t hsidiv;
-
-    switch (RCC->CFGR & RCC_CFGR_SWS)
-    {
-        case RCC_CFGR_SWS_0:                /* HSE used as system clock */
-            SystemCoreClock = HSE_VALUE;
-            break;
-        case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0):  /* LSI used as system clock */
-            SystemCoreClock = LSI_VALUE;
-            break;
-        case RCC_CFGR_SWS_2:                /* LSE used as system clock */
-            SystemCoreClock = LSE_VALUE;
-            break;
-        case RCC_CFGR_SWS_1:  /* PLL used as system clock */
-            /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
-               SYSCLK = PLL_VCO / PLLR */
-            pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
-            pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL;
-
-            if(pllsource == 0x03UL) {
-                /* HSE used as PLL clock source */
-                pllvco = (HSE_VALUE / pllm);
-            }
-            else {
-                /* HSI used as PLL clock source */
-                pllvco = (HSI_VALUE / pllm);
-            }
-            pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
-            pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
-
-            SystemCoreClock = pllvco/pllr;
-            break;
-        case 0x00000000U:                   /* HSI used as system clock */
-        default:                            /* HSI used as system clock */
-            hsidiv = (1UL << ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos));
-            SystemCoreClock = (HSI_VALUE/hsidiv);
-            break;
-    }
-    /* Compute HCLK clock frequency --------------------------------------------*/
-    /* Get HCLK prescaler */
-    tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
-    /* HCLK clock frequency */
-    SystemCoreClock >>= tmp;
-}
-
-void SystemClock_Config(void)
-{
-    /* Modify voltage scaling range */
-    uint32_t tmp = PWR->CR1;
-    tmp &= ~(PWR_CR1_VOS);
-    tmp |= PWR_CR1_VOS_0;   //Voltage scaling range 1
-    PWR->CR1 = tmp;
-    /* Wait until VOSF is reset */
-    while((PWR->SR2 & PWR_SR2_VOSF) == PWR_SR2_VOSF);
-
-    /* HSI clock config */
-    tmp = RCC->ICSCR;
-    tmp &= ~(RCC_ICSCR_HSITRIM);
-    tmp |= (64U << RCC_ICSCR_HSITRIM_Pos);  // Default HSI calibration trimming value
-    RCC->ICSCR = tmp;
-    /* Adjust the HSI16 division factor */
-    tmp = RCC->CR;
-    tmp &= ~(RCC_CR_HSIDIV);    // HSI clock is not divided
-    RCC->CR = tmp;
-    /* Update the SystemCoreClock global variable with HSISYS value  */
-    SystemCoreClock = (HSI_VALUE / (1UL << ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos)));
-
-    /* Adapt Systick interrupt period */
-    SysTick_Config(SystemCoreClock / 1000U);    // 1kHz
-    NVIC_SetPriority(SysTick_IRQn, SYS_TICK_PRIO);
-
-    /* LSI config */
-    /* Disable the Internal Low Speed oscillator (LSI). */
-    RCC->CSR &= ~(RCC_CSR_LSION);
-    /* Wait till LSI is disabled */
-    while ((RCC->CSR & RCC_CSR_LSIRDY) != 0U);
-
-    /* PLL config */
-    /* Disable the main PLL. */
-    RCC->CR &= ~(RCC_CR_PLLON);
-    /* Wait till PLL is ready */
-    while ((RCC->CR & RCC_CR_PLLRDY) != 0U);
-    /* Configure the main PLL clock source, multiplication and division factors. */
-    tmp = RCC->PLLCFGR;
-    tmp &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR);
-    tmp |= RCC_PLLCFGR_PLLSRC_HSI;  // HSI clock selected as PLL entry clock source
-    tmp |= (8 << RCC_PLLCFGR_PLLN_Pos);
-    tmp |= RCC_PLLCFGR_PLLP_0;      // PLLP division factor = 2
-    tmp |= RCC_PLLCFGR_PLLQ_0;      // PLLQ division factor = 2
-    tmp |= RCC_PLLCFGR_PLLR_0;      // PLLR division factor = 2
-    RCC->PLLCFGR = tmp;
-
-    /* Enable the main PLL. */
-    RCC->CR |= RCC_CR_PLLON;
-    /* Enable PLLR Clock output. */
-    RCC->PLLCFGR |= RCC_PLLCFGR_PLLREN      /*!< PLLRCLK selection from main PLL */;
-    /* Wait till PLL is ready */
-    while ((RCC->CR & RCC_CR_PLLRDY) == 0U);
-
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    tmp = FLASH->ACR;
-    tmp &= ~(FLASH_ACR_LATENCY);
-    tmp |= FLASH_ACR_LATENCY_1; // FLASH Two wait states
-    FLASH->ACR = tmp;
-    /* Check that the new number of wait states is taken into account to access the Flash
-       memory by polling the FLASH_ACR register */
-    while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */);
-
-    /* HCLK config */
-    /* Set the highest APB divider in order to ensure that we do not go through
-       a non-spec phase whatever we decrease or increase HCLK. */
-    tmp = RCC->CFGR;
-    tmp &= ~(RCC_CFGR_PPRE);
-    tmp |= (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0);   // HCLK divided by 16
-    RCC->CFGR = tmp;
-
-    /* Set the new HCLK clock divider */
-    tmp = RCC->CFGR;
-    tmp &= ~(RCC_CFGR_HPRE);    // SYSCLK not divided
-    RCC->CFGR = tmp;
-
-    /* SYSCLK config */
-    tmp = RCC->CFGR;
-    tmp &= ~(RCC_CFGR_SW);
-    tmp |= RCC_CFGR_SW_1;   // PLL selection as system clock
-    RCC->CFGR = tmp;
-    while ((RCC->CFGR & RCC_CFGR_SWS) != (RCC_CFGR_SW_1 << RCC_CFGR_SWS_Pos));
-
-    /* PCLK1 Configuration */
-    tmp = RCC->CFGR;
-    tmp &= ~(RCC_CFGR_PPRE);    // HCLK not divided
-    RCC->CFGR = tmp;
-
-    /* Adapt Systick interrupt period */
-    SystemCoreClock = 64000000;
-    SysTick_Config(SystemCoreClock / 1000U);    // 1kHz
-    NVIC_SetPriority(SysTick_IRQn, SYS_TICK_PRIO);
-
-#ifdef STM32G071xx
-    /* Configure the USART2 clock source */
-    tmp = RCC->CCIPR;
-    tmp &= ~(RCC_CCIPR_USART2SEL);  // APB clock selected as USART2 clock
-    RCC->CCIPR = tmp;
-#endif
-}
-
-void SystemInit(void)
-{
-#ifdef VECT_TAB_SRAM
-    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-    FLASH->ACR |= FLASH_ACR_PRFTEN;
-    SysTick_Config(SystemCoreClock / 1000U);    // 1kHz
-    NVIC_SetPriority(SysTick_IRQn, SYS_TICK_PRIO);
-
-    RCC->APBENR2 |= RCC_APBENR2_SYSCFGEN;
-    RCC->APBENR1 |= RCC_APBENR1_PWREN;
-
-#ifdef STM32G071xx
-    /* Change strobe configuration of GPIO depending on UCPDx dead battery settings */
-    uint32_t tmp = SYSCFG->CFGR1;
-    tmp &= ~(SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE);
-    tmp |= (SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE);
-    SYSCFG->CFGR1 = tmp;
-#endif
-
-    SystemClock_Config();
-}