155 lines
5.3 KiB
C++
155 lines
5.3 KiB
C++
#include <string.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdbool.h>
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#include "main.h"
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#include "platform/stm32g0xx/Gpio.h"
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#include "platform/stm32g0xx/Uart.h"
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#include "platform/stm32g0xx/IndependentWatchdog.h"
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static void SystemClock_Config(void);
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#define SYS_TICK_PRIO 0
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// NOTE! The independent watchdog is clocked by a separate clock. this one
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// isn't controlled by JTAG. That's why the independent watchdog needs to
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// be disabled during JTAG debug sessions.
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#define JTAG_DEBUG
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using namespace perinet::platform::stm32g0xx;
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Gpio green_led(Gpio::Port::PORT_A, 5, Gpio::Mode::MODE_OUTPUT_PP);
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Uart uart(Uart::UartDevice::UART_2, 115200);
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#ifndef JTAG_DEBUG
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IndependentWatchdog watchdog(4095, 4095);
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#endif
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int main(void)
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{
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unsigned int i = 1, j = 40;
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SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
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SysTick_Config(SystemCoreClock / 1000U); // 1kHz
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NVIC_SetPriority(SysTick_IRQn, SYS_TICK_PRIO);
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SET_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN);
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/* Delay after an RCC peripheral clock enabling */
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READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN);
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SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN);
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/* Delay after an RCC peripheral clock enabling */
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READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN);
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/* Change strobe configuration of GPIO depending on UCPDx dead battery settings */
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MODIFY_REG(SYSCFG->CFGR1, (SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE), SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE);
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SystemClock_Config();
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char tx_buf[80];
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#ifndef JTAG_DEBUG
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watchdog.enable();
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#endif
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while (1) {
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if (j < 100) {
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j += 10;
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}
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else if (j < 200) {
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j += 20;
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}
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else if (j < 400) {
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j += 40;
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}
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if (j > 800) {
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j = 800;
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}
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sprintf(tx_buf, "%u: Hello World\r\n", i++);
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uart.sync_send((const uint8_t *)tx_buf, strlen(tx_buf));
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green_led.toggle();
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HAL_Delay(j);
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#ifndef JTAG_DEBUG
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watchdog.trigger();
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#endif
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}
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}
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void SystemClock_Config(void)
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{
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/* Modify voltage scaling range */
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MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
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/* Wait until VOSF is reset */
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while(HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF));
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/* HSI clock config */
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MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, RCC_HSICALIBRATION_DEFAULT << RCC_ICSCR_HSITRIM_Pos);
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/* Adjust the HSI16 division factor */
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MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, RCC_HSI_DIV1);
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/* Update the SystemCoreClock global variable with HSISYS value */
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SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
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/* Adapt Systick interrupt period */
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SysTick_Config(SystemCoreClock / 1000U); // 1kHz
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NVIC_SetPriority(SysTick_IRQn, SYS_TICK_PRIO);
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/* LSI config */
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/* Disable the Internal Low Speed oscillator (LSI). */
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CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
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/* Wait till LSI is disabled */
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while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U);
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/* PLL config */
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/* Disable the main PLL. */
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CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
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/* Wait till PLL is ready */
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while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U);
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/* Configure the main PLL clock source, multiplication and division factors. */
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MODIFY_REG(RCC->PLLCFGR, (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR),
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(RCC_PLLSOURCE_HSI | RCC_PLLM_DIV1 | (8 << RCC_PLLCFGR_PLLN_Pos) | RCC_PLLP_DIV2 | RCC_PLLQ_DIV2 | RCC_PLLR_DIV2));
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/* Enable the main PLL. */
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SET_BIT(RCC->CR, RCC_CR_PLLON);
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/* Enable PLLR Clock output. */
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SET_BIT(RCC->PLLCFGR, RCC_PLLRCLK);
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/* Wait till PLL is ready */
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while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U);
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/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
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MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, FLASH_LATENCY_2);
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/* Check that the new number of wait states is taken into account to access the Flash
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memory by polling the FLASH_ACR register */
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while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLASH_LATENCY_2);
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/* HCLK config */
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/* Set the highest APB divider in order to ensure that we do not go through
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a non-spec phase whatever we decrease or increase HCLK. */
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MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
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/* Set the new HCLK clock divider */
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MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
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/* SYSCLK config */
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MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_SYSCLKSOURCE_PLLCLK);
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while ((RCC->CFGR & RCC_CFGR_SWS) != (RCC_SYSCLKSOURCE_PLLCLK << RCC_CFGR_SWS_Pos));
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/* PCLK1 Configuration */
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MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV1);
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/* TODO: Update the SystemCoreClock global variable */
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SystemCoreClock = 64000000;
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/* Configure the USART2 clock source */
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MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, RCC_USART2CLKSOURCE_PCLK1);
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}
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#ifdef USE_FULL_ASSERT
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void assert_failed(uint8_t *file, uint32_t line)
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{
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/* User can add his own implementation to report the file name and line number,
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ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
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}
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#endif /* USE_FULL_ASSERT */
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